2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/spi/spi.h>
15 #include <linux/usb/atmel_usba_udc.h>
20 #include <asm/arch/at32ap700x.h>
21 #include <asm/arch/board.h>
22 #include <asm/arch/portmux.h>
23 #include <asm/arch/sram.h>
25 #include <video/atmel_lcdc.h>
36 .end = base + 0x3ff, \
37 .flags = IORESOURCE_MEM, \
43 .flags = IORESOURCE_IRQ, \
45 #define NAMED_IRQ(num, _name) \
50 .flags = IORESOURCE_IRQ, \
53 /* REVISIT these assume *every* device supports DMA, but several
54 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
56 #define DEFINE_DEV(_name, _id) \
57 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
58 static struct platform_device _name##_id##_device = { \
62 .dma_mask = &_name##_id##_dma_mask, \
63 .coherent_dma_mask = DMA_32BIT_MASK, \
65 .resource = _name##_id##_resource, \
66 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
68 #define DEFINE_DEV_DATA(_name, _id) \
69 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
70 static struct platform_device _name##_id##_device = { \
74 .dma_mask = &_name##_id##_dma_mask, \
75 .platform_data = &_name##_id##_data, \
76 .coherent_dma_mask = DMA_32BIT_MASK, \
78 .resource = _name##_id##_resource, \
79 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
82 #define select_peripheral(pin, periph, flags) \
83 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
85 #define DEV_CLK(_name, devname, bus, _index) \
86 static struct clk devname##_##_name = { \
88 .dev = &devname##_device.dev, \
89 .parent = &bus##_clk, \
90 .mode = bus##_clk_mode, \
91 .get_rate = bus##_clk_get_rate, \
95 static DEFINE_SPINLOCK(pm_lock);
97 static struct clk osc0;
98 static struct clk osc1;
100 static unsigned long osc_get_rate(struct clk *clk)
102 return at32_board_osc_rates[clk->index];
105 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
107 unsigned long div, mul, rate;
109 div = PM_BFEXT(PLLDIV, control) + 1;
110 mul = PM_BFEXT(PLLMUL, control) + 1;
112 rate = clk->parent->get_rate(clk->parent);
113 rate = (rate + div / 2) / div;
119 static long pll_set_rate(struct clk *clk, unsigned long rate,
123 unsigned long mul_best_fit = 0;
125 unsigned long div_min;
126 unsigned long div_max;
127 unsigned long div_best_fit = 0;
129 unsigned long pll_in;
130 unsigned long actual = 0;
131 unsigned long rate_error;
132 unsigned long rate_error_prev = ~0UL;
135 /* Rate must be between 80 MHz and 200 Mhz. */
136 if (rate < 80000000UL || rate > 200000000UL)
139 ctrl = PM_BF(PLLOPT, 4);
140 base = clk->parent->get_rate(clk->parent);
142 /* PLL input frequency must be between 6 MHz and 32 MHz. */
143 div_min = DIV_ROUND_UP(base, 32000000UL);
144 div_max = base / 6000000UL;
146 if (div_max < div_min)
149 for (div = div_min; div <= div_max; div++) {
150 pll_in = (base + div / 2) / div;
151 mul = (rate + pll_in / 2) / pll_in;
156 actual = pll_in * mul;
157 rate_error = abs(actual - rate);
159 if (rate_error < rate_error_prev) {
162 rate_error_prev = rate_error;
169 if (div_best_fit == 0)
172 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
173 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
174 ctrl |= PM_BF(PLLCOUNT, 16);
176 if (clk->parent == &osc1)
177 ctrl |= PM_BIT(PLLOSC);
184 static unsigned long pll0_get_rate(struct clk *clk)
188 control = pm_readl(PLL0);
190 return pll_get_rate(clk, control);
193 static void pll1_mode(struct clk *clk, int enabled)
195 unsigned long timeout;
199 ctrl = pm_readl(PLL1);
202 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
203 pr_debug("clk %s: failed to enable, rate not set\n",
208 ctrl |= PM_BIT(PLLEN);
209 pm_writel(PLL1, ctrl);
211 /* Wait for PLL lock. */
212 for (timeout = 10000; timeout; timeout--) {
213 status = pm_readl(ISR);
214 if (status & PM_BIT(LOCK1))
219 if (!(status & PM_BIT(LOCK1)))
220 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
223 ctrl &= ~PM_BIT(PLLEN);
224 pm_writel(PLL1, ctrl);
228 static unsigned long pll1_get_rate(struct clk *clk)
232 control = pm_readl(PLL1);
234 return pll_get_rate(clk, control);
237 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
240 unsigned long actual_rate;
242 actual_rate = pll_set_rate(clk, rate, &ctrl);
245 if (actual_rate != rate)
249 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
250 clk->name, rate, actual_rate);
251 pm_writel(PLL1, ctrl);
257 static int pll1_set_parent(struct clk *clk, struct clk *parent)
264 ctrl = pm_readl(PLL1);
265 WARN_ON(ctrl & PM_BIT(PLLEN));
268 ctrl &= ~PM_BIT(PLLOSC);
269 else if (parent == &osc1)
270 ctrl |= PM_BIT(PLLOSC);
274 pm_writel(PLL1, ctrl);
275 clk->parent = parent;
281 * The AT32AP7000 has five primary clock sources: One 32kHz
282 * oscillator, two crystal oscillators and two PLLs.
284 static struct clk osc32k = {
286 .get_rate = osc_get_rate,
290 static struct clk osc0 = {
292 .get_rate = osc_get_rate,
296 static struct clk osc1 = {
298 .get_rate = osc_get_rate,
301 static struct clk pll0 = {
303 .get_rate = pll0_get_rate,
306 static struct clk pll1 = {
309 .get_rate = pll1_get_rate,
310 .set_rate = pll1_set_rate,
311 .set_parent = pll1_set_parent,
316 * The main clock can be either osc0 or pll0. The boot loader may
317 * have chosen one for us, so we don't really know which one until we
318 * have a look at the SM.
320 static struct clk *main_clock;
323 * Synchronous clocks are generated from the main clock. The clocks
324 * must satisfy the constraint
325 * fCPU >= fHSB >= fPB
326 * i.e. each clock must not be faster than its parent.
328 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
330 return main_clock->get_rate(main_clock) >> shift;
333 static void cpu_clk_mode(struct clk *clk, int enabled)
338 spin_lock_irqsave(&pm_lock, flags);
339 mask = pm_readl(CPU_MASK);
341 mask |= 1 << clk->index;
343 mask &= ~(1 << clk->index);
344 pm_writel(CPU_MASK, mask);
345 spin_unlock_irqrestore(&pm_lock, flags);
348 static unsigned long cpu_clk_get_rate(struct clk *clk)
350 unsigned long cksel, shift = 0;
352 cksel = pm_readl(CKSEL);
353 if (cksel & PM_BIT(CPUDIV))
354 shift = PM_BFEXT(CPUSEL, cksel) + 1;
356 return bus_clk_get_rate(clk, shift);
359 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
362 unsigned long parent_rate, child_div, actual_rate, div;
364 parent_rate = clk->parent->get_rate(clk->parent);
365 control = pm_readl(CKSEL);
367 if (control & PM_BIT(HSBDIV))
368 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
372 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
373 actual_rate = parent_rate;
374 control &= ~PM_BIT(CPUDIV);
377 div = (parent_rate + rate / 2) / rate;
380 cpusel = (div > 1) ? (fls(div) - 2) : 0;
381 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
382 actual_rate = parent_rate / (1 << (cpusel + 1));
385 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
386 clk->name, rate, actual_rate);
389 pm_writel(CKSEL, control);
394 static void hsb_clk_mode(struct clk *clk, int enabled)
399 spin_lock_irqsave(&pm_lock, flags);
400 mask = pm_readl(HSB_MASK);
402 mask |= 1 << clk->index;
404 mask &= ~(1 << clk->index);
405 pm_writel(HSB_MASK, mask);
406 spin_unlock_irqrestore(&pm_lock, flags);
409 static unsigned long hsb_clk_get_rate(struct clk *clk)
411 unsigned long cksel, shift = 0;
413 cksel = pm_readl(CKSEL);
414 if (cksel & PM_BIT(HSBDIV))
415 shift = PM_BFEXT(HSBSEL, cksel) + 1;
417 return bus_clk_get_rate(clk, shift);
420 static void pba_clk_mode(struct clk *clk, int enabled)
425 spin_lock_irqsave(&pm_lock, flags);
426 mask = pm_readl(PBA_MASK);
428 mask |= 1 << clk->index;
430 mask &= ~(1 << clk->index);
431 pm_writel(PBA_MASK, mask);
432 spin_unlock_irqrestore(&pm_lock, flags);
435 static unsigned long pba_clk_get_rate(struct clk *clk)
437 unsigned long cksel, shift = 0;
439 cksel = pm_readl(CKSEL);
440 if (cksel & PM_BIT(PBADIV))
441 shift = PM_BFEXT(PBASEL, cksel) + 1;
443 return bus_clk_get_rate(clk, shift);
446 static void pbb_clk_mode(struct clk *clk, int enabled)
451 spin_lock_irqsave(&pm_lock, flags);
452 mask = pm_readl(PBB_MASK);
454 mask |= 1 << clk->index;
456 mask &= ~(1 << clk->index);
457 pm_writel(PBB_MASK, mask);
458 spin_unlock_irqrestore(&pm_lock, flags);
461 static unsigned long pbb_clk_get_rate(struct clk *clk)
463 unsigned long cksel, shift = 0;
465 cksel = pm_readl(CKSEL);
466 if (cksel & PM_BIT(PBBDIV))
467 shift = PM_BFEXT(PBBSEL, cksel) + 1;
469 return bus_clk_get_rate(clk, shift);
472 static struct clk cpu_clk = {
474 .get_rate = cpu_clk_get_rate,
475 .set_rate = cpu_clk_set_rate,
478 static struct clk hsb_clk = {
481 .get_rate = hsb_clk_get_rate,
483 static struct clk pba_clk = {
486 .mode = hsb_clk_mode,
487 .get_rate = pba_clk_get_rate,
490 static struct clk pbb_clk = {
493 .mode = hsb_clk_mode,
494 .get_rate = pbb_clk_get_rate,
499 /* --------------------------------------------------------------------
500 * Generic Clock operations
501 * -------------------------------------------------------------------- */
503 static void genclk_mode(struct clk *clk, int enabled)
507 control = pm_readl(GCCTRL(clk->index));
509 control |= PM_BIT(CEN);
511 control &= ~PM_BIT(CEN);
512 pm_writel(GCCTRL(clk->index), control);
515 static unsigned long genclk_get_rate(struct clk *clk)
518 unsigned long div = 1;
520 control = pm_readl(GCCTRL(clk->index));
521 if (control & PM_BIT(DIVEN))
522 div = 2 * (PM_BFEXT(DIV, control) + 1);
524 return clk->parent->get_rate(clk->parent) / div;
527 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
530 unsigned long parent_rate, actual_rate, div;
532 parent_rate = clk->parent->get_rate(clk->parent);
533 control = pm_readl(GCCTRL(clk->index));
535 if (rate > 3 * parent_rate / 4) {
536 actual_rate = parent_rate;
537 control &= ~PM_BIT(DIVEN);
539 div = (parent_rate + rate) / (2 * rate) - 1;
540 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
541 actual_rate = parent_rate / (2 * (div + 1));
544 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
545 clk->name, rate, actual_rate);
548 pm_writel(GCCTRL(clk->index), control);
553 int genclk_set_parent(struct clk *clk, struct clk *parent)
557 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
558 clk->name, parent->name, clk->parent->name);
560 control = pm_readl(GCCTRL(clk->index));
562 if (parent == &osc1 || parent == &pll1)
563 control |= PM_BIT(OSCSEL);
564 else if (parent == &osc0 || parent == &pll0)
565 control &= ~PM_BIT(OSCSEL);
569 if (parent == &pll0 || parent == &pll1)
570 control |= PM_BIT(PLLSEL);
572 control &= ~PM_BIT(PLLSEL);
574 pm_writel(GCCTRL(clk->index), control);
575 clk->parent = parent;
580 static void __init genclk_init_parent(struct clk *clk)
585 BUG_ON(clk->index > 7);
587 control = pm_readl(GCCTRL(clk->index));
588 if (control & PM_BIT(OSCSEL))
589 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
591 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
593 clk->parent = parent;
596 /* --------------------------------------------------------------------
598 * -------------------------------------------------------------------- */
599 static struct resource at32_pm0_resource[] = {
603 .flags = IORESOURCE_MEM,
608 static struct resource at32ap700x_rtc0_resource[] = {
612 .flags = IORESOURCE_MEM,
617 static struct resource at32_wdt0_resource[] = {
621 .flags = IORESOURCE_MEM,
625 static struct resource at32_eic0_resource[] = {
629 .flags = IORESOURCE_MEM,
634 DEFINE_DEV(at32_pm, 0);
635 DEFINE_DEV(at32ap700x_rtc, 0);
636 DEFINE_DEV(at32_wdt, 0);
637 DEFINE_DEV(at32_eic, 0);
640 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
643 static struct clk at32_pm_pclk = {
645 .dev = &at32_pm0_device.dev,
647 .mode = pbb_clk_mode,
648 .get_rate = pbb_clk_get_rate,
653 static struct resource intc0_resource[] = {
656 struct platform_device at32_intc0_device = {
659 .resource = intc0_resource,
660 .num_resources = ARRAY_SIZE(intc0_resource),
662 DEV_CLK(pclk, at32_intc0, pbb, 1);
664 static struct clk ebi_clk = {
667 .mode = hsb_clk_mode,
668 .get_rate = hsb_clk_get_rate,
671 static struct clk hramc_clk = {
674 .mode = hsb_clk_mode,
675 .get_rate = hsb_clk_get_rate,
679 static struct clk sdramc_clk = {
680 .name = "sdramc_clk",
682 .mode = pbb_clk_mode,
683 .get_rate = pbb_clk_get_rate,
688 static struct resource smc0_resource[] = {
692 DEV_CLK(pclk, smc0, pbb, 13);
693 DEV_CLK(mck, smc0, hsb, 0);
695 static struct platform_device pdc_device = {
699 DEV_CLK(hclk, pdc, hsb, 4);
700 DEV_CLK(pclk, pdc, pba, 16);
702 static struct clk pico_clk = {
705 .mode = cpu_clk_mode,
706 .get_rate = cpu_clk_get_rate,
710 static struct resource dmaca0_resource[] = {
714 .flags = IORESOURCE_MEM,
718 DEFINE_DEV(dmaca, 0);
719 DEV_CLK(hclk, dmaca0, hsb, 10);
721 /* --------------------------------------------------------------------
723 * -------------------------------------------------------------------- */
725 static struct clk hmatrix_clk = {
726 .name = "hmatrix_clk",
728 .mode = pbb_clk_mode,
729 .get_rate = pbb_clk_get_rate,
733 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
735 #define hmatrix_readl(reg) \
736 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
737 #define hmatrix_writel(reg,value) \
738 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
741 * Set bits in the HMATRIX Special Function Register (SFR) used by the
742 * External Bus Interface (EBI). This can be used to enable special
743 * features like CompactFlash support, NAND Flash support, etc. on
744 * certain chipselects.
746 static inline void set_ebi_sfr_bits(u32 mask)
750 clk_enable(&hmatrix_clk);
751 sfr = hmatrix_readl(SFR4);
753 hmatrix_writel(SFR4, sfr);
754 clk_disable(&hmatrix_clk);
757 /* --------------------------------------------------------------------
759 * -------------------------------------------------------------------- */
761 static struct resource at32_tcb0_resource[] = {
765 static struct platform_device at32_tcb0_device = {
768 .resource = at32_tcb0_resource,
769 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
771 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
773 static struct resource at32_tcb1_resource[] = {
777 static struct platform_device at32_tcb1_device = {
780 .resource = at32_tcb1_resource,
781 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
783 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
785 /* --------------------------------------------------------------------
787 * -------------------------------------------------------------------- */
789 static struct resource pio0_resource[] = {
794 DEV_CLK(mck, pio0, pba, 10);
796 static struct resource pio1_resource[] = {
801 DEV_CLK(mck, pio1, pba, 11);
803 static struct resource pio2_resource[] = {
808 DEV_CLK(mck, pio2, pba, 12);
810 static struct resource pio3_resource[] = {
815 DEV_CLK(mck, pio3, pba, 13);
817 static struct resource pio4_resource[] = {
822 DEV_CLK(mck, pio4, pba, 14);
824 void __init at32_add_system_devices(void)
826 platform_device_register(&at32_pm0_device);
827 platform_device_register(&at32_intc0_device);
828 platform_device_register(&at32ap700x_rtc0_device);
829 platform_device_register(&at32_wdt0_device);
830 platform_device_register(&at32_eic0_device);
831 platform_device_register(&smc0_device);
832 platform_device_register(&pdc_device);
833 platform_device_register(&dmaca0_device);
835 platform_device_register(&at32_tcb0_device);
836 platform_device_register(&at32_tcb1_device);
838 platform_device_register(&pio0_device);
839 platform_device_register(&pio1_device);
840 platform_device_register(&pio2_device);
841 platform_device_register(&pio3_device);
842 platform_device_register(&pio4_device);
845 /* --------------------------------------------------------------------
847 * -------------------------------------------------------------------- */
848 static struct resource atmel_psif0_resource[] __initdata = {
852 .flags = IORESOURCE_MEM,
856 static struct clk atmel_psif0_pclk = {
859 .mode = pba_clk_mode,
860 .get_rate = pba_clk_get_rate,
864 static struct resource atmel_psif1_resource[] __initdata = {
868 .flags = IORESOURCE_MEM,
872 static struct clk atmel_psif1_pclk = {
875 .mode = pba_clk_mode,
876 .get_rate = pba_clk_get_rate,
880 struct platform_device *__init at32_add_device_psif(unsigned int id)
882 struct platform_device *pdev;
884 if (!(id == 0 || id == 1))
887 pdev = platform_device_alloc("atmel_psif", id);
893 if (platform_device_add_resources(pdev, atmel_psif0_resource,
894 ARRAY_SIZE(atmel_psif0_resource)))
895 goto err_add_resources;
896 atmel_psif0_pclk.dev = &pdev->dev;
897 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
898 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
901 if (platform_device_add_resources(pdev, atmel_psif1_resource,
902 ARRAY_SIZE(atmel_psif1_resource)))
903 goto err_add_resources;
904 atmel_psif1_pclk.dev = &pdev->dev;
905 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
906 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
912 platform_device_add(pdev);
916 platform_device_put(pdev);
920 /* --------------------------------------------------------------------
922 * -------------------------------------------------------------------- */
924 static struct atmel_uart_data atmel_usart0_data = {
928 static struct resource atmel_usart0_resource[] = {
932 DEFINE_DEV_DATA(atmel_usart, 0);
933 DEV_CLK(usart, atmel_usart0, pba, 3);
935 static struct atmel_uart_data atmel_usart1_data = {
939 static struct resource atmel_usart1_resource[] = {
943 DEFINE_DEV_DATA(atmel_usart, 1);
944 DEV_CLK(usart, atmel_usart1, pba, 4);
946 static struct atmel_uart_data atmel_usart2_data = {
950 static struct resource atmel_usart2_resource[] = {
954 DEFINE_DEV_DATA(atmel_usart, 2);
955 DEV_CLK(usart, atmel_usart2, pba, 5);
957 static struct atmel_uart_data atmel_usart3_data = {
961 static struct resource atmel_usart3_resource[] = {
965 DEFINE_DEV_DATA(atmel_usart, 3);
966 DEV_CLK(usart, atmel_usart3, pba, 6);
968 static inline void configure_usart0_pins(void)
970 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
971 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
974 static inline void configure_usart1_pins(void)
976 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
977 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
980 static inline void configure_usart2_pins(void)
982 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
983 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
986 static inline void configure_usart3_pins(void)
988 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
989 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
992 static struct platform_device *__initdata at32_usarts[4];
994 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
996 struct platform_device *pdev;
1000 pdev = &atmel_usart0_device;
1001 configure_usart0_pins();
1004 pdev = &atmel_usart1_device;
1005 configure_usart1_pins();
1008 pdev = &atmel_usart2_device;
1009 configure_usart2_pins();
1012 pdev = &atmel_usart3_device;
1013 configure_usart3_pins();
1019 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1020 /* Addresses in the P4 segment are permanently mapped 1:1 */
1021 struct atmel_uart_data *data = pdev->dev.platform_data;
1022 data->regs = (void __iomem *)pdev->resource[0].start;
1026 at32_usarts[line] = pdev;
1029 struct platform_device *__init at32_add_device_usart(unsigned int id)
1031 platform_device_register(at32_usarts[id]);
1032 return at32_usarts[id];
1035 struct platform_device *atmel_default_console_device;
1037 void __init at32_setup_serial_console(unsigned int usart_id)
1039 atmel_default_console_device = at32_usarts[usart_id];
1042 /* --------------------------------------------------------------------
1044 * -------------------------------------------------------------------- */
1046 #ifdef CONFIG_CPU_AT32AP7000
1047 static struct eth_platform_data macb0_data;
1048 static struct resource macb0_resource[] = {
1052 DEFINE_DEV_DATA(macb, 0);
1053 DEV_CLK(hclk, macb0, hsb, 8);
1054 DEV_CLK(pclk, macb0, pbb, 6);
1056 static struct eth_platform_data macb1_data;
1057 static struct resource macb1_resource[] = {
1061 DEFINE_DEV_DATA(macb, 1);
1062 DEV_CLK(hclk, macb1, hsb, 9);
1063 DEV_CLK(pclk, macb1, pbb, 7);
1065 struct platform_device *__init
1066 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1068 struct platform_device *pdev;
1072 pdev = &macb0_device;
1074 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1075 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1076 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1077 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1078 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1079 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1080 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1081 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1082 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1083 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1085 if (!data->is_rmii) {
1086 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1087 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1088 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1089 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1090 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1091 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1092 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1093 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1094 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1099 pdev = &macb1_device;
1101 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1102 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1103 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1104 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1105 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1106 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1107 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1108 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1109 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1110 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1112 if (!data->is_rmii) {
1113 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1114 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1115 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1116 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1117 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1118 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1119 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1120 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1121 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1129 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1130 platform_device_register(pdev);
1136 /* --------------------------------------------------------------------
1138 * -------------------------------------------------------------------- */
1139 static struct resource atmel_spi0_resource[] = {
1143 DEFINE_DEV(atmel_spi, 0);
1144 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1146 static struct resource atmel_spi1_resource[] = {
1150 DEFINE_DEV(atmel_spi, 1);
1151 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1154 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1155 unsigned int n, const u8 *pins)
1157 unsigned int pin, mode;
1159 for (; n; n--, b++) {
1160 b->bus_num = bus_num;
1161 if (b->chip_select >= 4)
1163 pin = (unsigned)b->controller_data;
1165 pin = pins[b->chip_select];
1166 b->controller_data = (void *)pin;
1168 mode = AT32_GPIOF_OUTPUT;
1169 if (!(b->mode & SPI_CS_HIGH))
1170 mode |= AT32_GPIOF_HIGH;
1171 at32_select_gpio(pin, mode);
1175 struct platform_device *__init
1176 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1179 * Manage the chipselects as GPIOs, normally using the same pins
1180 * the SPI controller expects; but boards can use other pins.
1182 static u8 __initdata spi0_pins[] =
1183 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1184 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1185 static u8 __initdata spi1_pins[] =
1186 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1187 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1188 struct platform_device *pdev;
1192 pdev = &atmel_spi0_device;
1193 /* pullup MISO so a level is always defined */
1194 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1195 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1196 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1197 at32_spi_setup_slaves(0, b, n, spi0_pins);
1201 pdev = &atmel_spi1_device;
1202 /* pullup MISO so a level is always defined */
1203 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1204 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1205 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1206 at32_spi_setup_slaves(1, b, n, spi1_pins);
1213 spi_register_board_info(b, n);
1214 platform_device_register(pdev);
1218 /* --------------------------------------------------------------------
1220 * -------------------------------------------------------------------- */
1221 static struct resource atmel_twi0_resource[] __initdata = {
1225 static struct clk atmel_twi0_pclk = {
1228 .mode = pba_clk_mode,
1229 .get_rate = pba_clk_get_rate,
1233 struct platform_device *__init at32_add_device_twi(unsigned int id,
1234 struct i2c_board_info *b,
1237 struct platform_device *pdev;
1242 pdev = platform_device_alloc("atmel_twi", id);
1246 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1247 ARRAY_SIZE(atmel_twi0_resource)))
1248 goto err_add_resources;
1250 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1251 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1253 atmel_twi0_pclk.dev = &pdev->dev;
1256 i2c_register_board_info(id, b, n);
1258 platform_device_add(pdev);
1262 platform_device_put(pdev);
1266 /* --------------------------------------------------------------------
1268 * -------------------------------------------------------------------- */
1269 static struct resource atmel_mci0_resource[] __initdata = {
1273 static struct clk atmel_mci0_pclk = {
1276 .mode = pbb_clk_mode,
1277 .get_rate = pbb_clk_get_rate,
1281 struct platform_device *__init at32_add_device_mci(unsigned int id)
1283 struct platform_device *pdev;
1288 pdev = platform_device_alloc("atmel_mci", id);
1292 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1293 ARRAY_SIZE(atmel_mci0_resource)))
1294 goto err_add_resources;
1296 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1297 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1298 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1299 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1300 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1301 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1303 atmel_mci0_pclk.dev = &pdev->dev;
1305 platform_device_add(pdev);
1309 platform_device_put(pdev);
1313 /* --------------------------------------------------------------------
1315 * -------------------------------------------------------------------- */
1316 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1317 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1318 static struct resource atmel_lcdfb0_resource[] = {
1320 .start = 0xff000000,
1322 .flags = IORESOURCE_MEM,
1326 /* Placeholder for pre-allocated fb memory */
1327 .start = 0x00000000,
1332 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1333 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1334 static struct clk atmel_lcdfb0_pixclk = {
1336 .dev = &atmel_lcdfb0_device.dev,
1337 .mode = genclk_mode,
1338 .get_rate = genclk_get_rate,
1339 .set_rate = genclk_set_rate,
1340 .set_parent = genclk_set_parent,
1344 struct platform_device *__init
1345 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1346 unsigned long fbmem_start, unsigned long fbmem_len,
1347 unsigned int pin_config)
1349 struct platform_device *pdev;
1350 struct atmel_lcdfb_info *info;
1351 struct fb_monspecs *monspecs;
1352 struct fb_videomode *modedb;
1353 unsigned int modedb_size;
1356 * Do a deep copy of the fb data, monspecs and modedb. Make
1357 * sure all allocations are done before setting up the
1360 monspecs = kmemdup(data->default_monspecs,
1361 sizeof(struct fb_monspecs), GFP_KERNEL);
1365 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1366 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1368 goto err_dup_modedb;
1369 monspecs->modedb = modedb;
1373 pdev = &atmel_lcdfb0_device;
1375 switch (pin_config) {
1377 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1378 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1379 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1380 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1381 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1382 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1383 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1384 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1385 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1386 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1387 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1388 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1389 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1390 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1391 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1392 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1393 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1394 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1395 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1396 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1397 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1398 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1399 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1400 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1401 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1402 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1403 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1404 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1405 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1406 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1407 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1410 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1411 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1412 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1413 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1414 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1415 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1416 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1417 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1418 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1419 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1420 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1421 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1422 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1423 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1424 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1425 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1426 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1427 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1428 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1429 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1430 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1431 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1432 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1433 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1434 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1435 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1436 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1437 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1438 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1439 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1440 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1443 goto err_invalid_id;
1446 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1447 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1451 goto err_invalid_id;
1455 pdev->resource[2].start = fbmem_start;
1456 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1457 pdev->resource[2].flags = IORESOURCE_MEM;
1460 info = pdev->dev.platform_data;
1461 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1462 info->default_monspecs = monspecs;
1464 platform_device_register(pdev);
1475 /* --------------------------------------------------------------------
1477 * -------------------------------------------------------------------- */
1478 static struct resource atmel_pwm0_resource[] __initdata = {
1482 static struct clk atmel_pwm0_mck = {
1485 .mode = pbb_clk_mode,
1486 .get_rate = pbb_clk_get_rate,
1490 struct platform_device *__init at32_add_device_pwm(u32 mask)
1492 struct platform_device *pdev;
1497 pdev = platform_device_alloc("atmel_pwm", 0);
1501 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1502 ARRAY_SIZE(atmel_pwm0_resource)))
1505 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1508 if (mask & (1 << 0))
1509 select_peripheral(PA(28), PERIPH_A, 0);
1510 if (mask & (1 << 1))
1511 select_peripheral(PA(29), PERIPH_A, 0);
1512 if (mask & (1 << 2))
1513 select_peripheral(PA(21), PERIPH_B, 0);
1514 if (mask & (1 << 3))
1515 select_peripheral(PA(22), PERIPH_B, 0);
1517 atmel_pwm0_mck.dev = &pdev->dev;
1519 platform_device_add(pdev);
1524 platform_device_put(pdev);
1528 /* --------------------------------------------------------------------
1530 * -------------------------------------------------------------------- */
1531 static struct resource ssc0_resource[] = {
1536 DEV_CLK(pclk, ssc0, pba, 7);
1538 static struct resource ssc1_resource[] = {
1543 DEV_CLK(pclk, ssc1, pba, 8);
1545 static struct resource ssc2_resource[] = {
1550 DEV_CLK(pclk, ssc2, pba, 9);
1552 struct platform_device *__init
1553 at32_add_device_ssc(unsigned int id, unsigned int flags)
1555 struct platform_device *pdev;
1559 pdev = &ssc0_device;
1560 if (flags & ATMEL_SSC_RF)
1561 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1562 if (flags & ATMEL_SSC_RK)
1563 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1564 if (flags & ATMEL_SSC_TK)
1565 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1566 if (flags & ATMEL_SSC_TF)
1567 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1568 if (flags & ATMEL_SSC_TD)
1569 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1570 if (flags & ATMEL_SSC_RD)
1571 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1574 pdev = &ssc1_device;
1575 if (flags & ATMEL_SSC_RF)
1576 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1577 if (flags & ATMEL_SSC_RK)
1578 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1579 if (flags & ATMEL_SSC_TK)
1580 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1581 if (flags & ATMEL_SSC_TF)
1582 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1583 if (flags & ATMEL_SSC_TD)
1584 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1585 if (flags & ATMEL_SSC_RD)
1586 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1589 pdev = &ssc2_device;
1590 if (flags & ATMEL_SSC_TD)
1591 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1592 if (flags & ATMEL_SSC_RD)
1593 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1594 if (flags & ATMEL_SSC_TK)
1595 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1596 if (flags & ATMEL_SSC_TF)
1597 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1598 if (flags & ATMEL_SSC_RF)
1599 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1600 if (flags & ATMEL_SSC_RK)
1601 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1607 platform_device_register(pdev);
1611 /* --------------------------------------------------------------------
1612 * USB Device Controller
1613 * -------------------------------------------------------------------- */
1614 static struct resource usba0_resource[] __initdata = {
1616 .start = 0xff300000,
1618 .flags = IORESOURCE_MEM,
1620 .start = 0xfff03000,
1622 .flags = IORESOURCE_MEM,
1626 static struct clk usba0_pclk = {
1629 .mode = pbb_clk_mode,
1630 .get_rate = pbb_clk_get_rate,
1633 static struct clk usba0_hclk = {
1636 .mode = hsb_clk_mode,
1637 .get_rate = hsb_clk_get_rate,
1641 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1645 .fifo_size = maxpkt, \
1646 .nr_banks = maxbk, \
1651 static struct usba_ep_data at32_usba_ep[] __initdata = {
1652 EP("ep0", 0, 64, 1, 0, 0),
1653 EP("ep1", 1, 512, 2, 1, 1),
1654 EP("ep2", 2, 512, 2, 1, 1),
1655 EP("ep3-int", 3, 64, 3, 1, 0),
1656 EP("ep4-int", 4, 64, 3, 1, 0),
1657 EP("ep5", 5, 1024, 3, 1, 1),
1658 EP("ep6", 6, 1024, 3, 1, 1),
1663 struct platform_device *__init
1664 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1667 * pdata doesn't have room for any endpoints, so we need to
1668 * append room for the ones we need right after it.
1671 struct usba_platform_data pdata;
1672 struct usba_ep_data ep[7];
1674 struct platform_device *pdev;
1679 pdev = platform_device_alloc("atmel_usba_udc", 0);
1683 if (platform_device_add_resources(pdev, usba0_resource,
1684 ARRAY_SIZE(usba0_resource)))
1688 usba_data.pdata.vbus_pin = data->vbus_pin;
1690 usba_data.pdata.vbus_pin = -EINVAL;
1692 data = &usba_data.pdata;
1693 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1694 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1696 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1699 if (data->vbus_pin >= 0)
1700 at32_select_gpio(data->vbus_pin, 0);
1702 usba0_pclk.dev = &pdev->dev;
1703 usba0_hclk.dev = &pdev->dev;
1705 platform_device_add(pdev);
1710 platform_device_put(pdev);
1714 /* --------------------------------------------------------------------
1715 * IDE / CompactFlash
1716 * -------------------------------------------------------------------- */
1717 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1718 static struct resource at32_smc_cs4_resource[] __initdata = {
1720 .start = 0x04000000,
1722 .flags = IORESOURCE_MEM,
1724 IRQ(~0UL), /* Magic IRQ will be overridden */
1726 static struct resource at32_smc_cs5_resource[] __initdata = {
1728 .start = 0x20000000,
1730 .flags = IORESOURCE_MEM,
1732 IRQ(~0UL), /* Magic IRQ will be overridden */
1735 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1736 unsigned int cs, unsigned int extint)
1738 static unsigned int extint_pin_map[4] __initdata = {
1744 static bool common_pins_initialized __initdata = false;
1745 unsigned int extint_pin;
1748 if (extint >= ARRAY_SIZE(extint_pin_map))
1750 extint_pin = extint_pin_map[extint];
1754 ret = platform_device_add_resources(pdev,
1755 at32_smc_cs4_resource,
1756 ARRAY_SIZE(at32_smc_cs4_resource));
1760 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1761 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1764 ret = platform_device_add_resources(pdev,
1765 at32_smc_cs5_resource,
1766 ARRAY_SIZE(at32_smc_cs5_resource));
1770 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1771 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1777 if (!common_pins_initialized) {
1778 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1779 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1780 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1781 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1782 common_pins_initialized = true;
1785 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1787 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1788 pdev->resource[1].end = pdev->resource[1].start;
1793 struct platform_device *__init
1794 at32_add_device_ide(unsigned int id, unsigned int extint,
1795 struct ide_platform_data *data)
1797 struct platform_device *pdev;
1799 pdev = platform_device_alloc("at32_ide", id);
1803 if (platform_device_add_data(pdev, data,
1804 sizeof(struct ide_platform_data)))
1807 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1810 platform_device_add(pdev);
1814 platform_device_put(pdev);
1818 struct platform_device *__init
1819 at32_add_device_cf(unsigned int id, unsigned int extint,
1820 struct cf_platform_data *data)
1822 struct platform_device *pdev;
1824 pdev = platform_device_alloc("at32_cf", id);
1828 if (platform_device_add_data(pdev, data,
1829 sizeof(struct cf_platform_data)))
1832 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1835 if (data->detect_pin != GPIO_PIN_NONE)
1836 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1837 if (data->reset_pin != GPIO_PIN_NONE)
1838 at32_select_gpio(data->reset_pin, 0);
1839 if (data->vcc_pin != GPIO_PIN_NONE)
1840 at32_select_gpio(data->vcc_pin, 0);
1841 /* READY is used as extint, so we can't select it as gpio */
1843 platform_device_add(pdev);
1847 platform_device_put(pdev);
1852 /* --------------------------------------------------------------------
1854 * -------------------------------------------------------------------- */
1855 static struct resource atmel_ac97c0_resource[] __initdata = {
1859 static struct clk atmel_ac97c0_pclk = {
1862 .mode = pbb_clk_mode,
1863 .get_rate = pbb_clk_get_rate,
1867 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1869 struct platform_device *pdev;
1874 pdev = platform_device_alloc("atmel_ac97c", id);
1878 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1879 ARRAY_SIZE(atmel_ac97c0_resource)))
1880 goto err_add_resources;
1882 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1883 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1884 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1885 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1887 atmel_ac97c0_pclk.dev = &pdev->dev;
1889 platform_device_add(pdev);
1893 platform_device_put(pdev);
1897 /* --------------------------------------------------------------------
1899 * -------------------------------------------------------------------- */
1900 static struct resource abdac0_resource[] __initdata = {
1904 static struct clk abdac0_pclk = {
1907 .mode = pbb_clk_mode,
1908 .get_rate = pbb_clk_get_rate,
1911 static struct clk abdac0_sample_clk = {
1912 .name = "sample_clk",
1913 .mode = genclk_mode,
1914 .get_rate = genclk_get_rate,
1915 .set_rate = genclk_set_rate,
1916 .set_parent = genclk_set_parent,
1920 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1922 struct platform_device *pdev;
1927 pdev = platform_device_alloc("abdac", id);
1931 if (platform_device_add_resources(pdev, abdac0_resource,
1932 ARRAY_SIZE(abdac0_resource)))
1933 goto err_add_resources;
1935 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1936 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1937 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1938 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1940 abdac0_pclk.dev = &pdev->dev;
1941 abdac0_sample_clk.dev = &pdev->dev;
1943 platform_device_add(pdev);
1947 platform_device_put(pdev);
1951 /* --------------------------------------------------------------------
1953 * -------------------------------------------------------------------- */
1954 static struct clk gclk0 = {
1956 .mode = genclk_mode,
1957 .get_rate = genclk_get_rate,
1958 .set_rate = genclk_set_rate,
1959 .set_parent = genclk_set_parent,
1962 static struct clk gclk1 = {
1964 .mode = genclk_mode,
1965 .get_rate = genclk_get_rate,
1966 .set_rate = genclk_set_rate,
1967 .set_parent = genclk_set_parent,
1970 static struct clk gclk2 = {
1972 .mode = genclk_mode,
1973 .get_rate = genclk_get_rate,
1974 .set_rate = genclk_set_rate,
1975 .set_parent = genclk_set_parent,
1978 static struct clk gclk3 = {
1980 .mode = genclk_mode,
1981 .get_rate = genclk_get_rate,
1982 .set_rate = genclk_set_rate,
1983 .set_parent = genclk_set_parent,
1986 static struct clk gclk4 = {
1988 .mode = genclk_mode,
1989 .get_rate = genclk_get_rate,
1990 .set_rate = genclk_set_rate,
1991 .set_parent = genclk_set_parent,
1995 struct clk *at32_clock_list[] = {
2026 &atmel_usart0_usart,
2027 &atmel_usart1_usart,
2028 &atmel_usart2_usart,
2029 &atmel_usart3_usart,
2031 #if defined(CONFIG_CPU_AT32AP7000)
2037 &atmel_spi0_spi_clk,
2038 &atmel_spi1_spi_clk,
2041 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2043 &atmel_lcdfb0_pixclk,
2059 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2061 void __init setup_platform(void)
2063 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2066 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2068 cpu_clk.parent = &pll0;
2071 cpu_clk.parent = &osc0;
2074 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2075 pll0.parent = &osc1;
2076 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2077 pll1.parent = &osc1;
2079 genclk_init_parent(&gclk0);
2080 genclk_init_parent(&gclk1);
2081 genclk_init_parent(&gclk2);
2082 genclk_init_parent(&gclk3);
2083 genclk_init_parent(&gclk4);
2084 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2085 genclk_init_parent(&atmel_lcdfb0_pixclk);
2087 genclk_init_parent(&abdac0_sample_clk);
2090 * Turn on all clocks that have at least one user already, and
2091 * turn off everything else. We only do this for module
2092 * clocks, and even though it isn't particularly pretty to
2093 * check the address of the mode function, it should do the
2096 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2097 struct clk *clk = at32_clock_list[i];
2099 if (clk->users == 0)
2102 if (clk->mode == &cpu_clk_mode)
2103 cpu_mask |= 1 << clk->index;
2104 else if (clk->mode == &hsb_clk_mode)
2105 hsb_mask |= 1 << clk->index;
2106 else if (clk->mode == &pba_clk_mode)
2107 pba_mask |= 1 << clk->index;
2108 else if (clk->mode == &pbb_clk_mode)
2109 pbb_mask |= 1 << clk->index;
2112 pm_writel(CPU_MASK, cpu_mask);
2113 pm_writel(HSB_MASK, hsb_mask);
2114 pm_writel(PBA_MASK, pba_mask);
2115 pm_writel(PBB_MASK, pbb_mask);
2117 /* Initialize the port muxes */
2118 at32_init_pio(&pio0_device);
2119 at32_init_pio(&pio1_device);
2120 at32_init_pio(&pio2_device);
2121 at32_init_pio(&pio3_device);
2122 at32_init_pio(&pio4_device);
2125 struct gen_pool *sram_pool;
2127 static int __init sram_init(void)
2129 struct gen_pool *pool;
2131 /* 1KiB granularity */
2132 pool = gen_pool_create(10, -1);
2136 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2143 gen_pool_destroy(pool);
2145 pr_err("Failed to create SRAM pool\n");
2148 core_initcall(sram_init);