2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
275 comment "Clock/PLL Setup"
278 int "Crystal Frequency in Hz"
279 default "11059200" if BFIN533_STAMP
280 default "27000000" if BFIN533_EZKIT
281 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
282 default "30000000" if BFIN561_EZKIT
283 default "24576000" if PNAV10
285 The frequency of CLKIN crystal oscillator on the board in Hz.
287 config BFIN_KERNEL_CLOCK
288 bool "Re-program Clocks while Kernel boots?"
291 This option decides if kernel clocks are re-programed from the
292 bootloader settings. If the clocks are not set, the SDRAM settings
293 are also not changed, and the Bootloader does 100% of the hardware
297 int "Memory Address Width"
298 depends on BFIN_KERNEL_CLOCK
300 default 9 if BFIN533_EZKIT
301 default 9 if BFIN561_EZKIT
302 default 9 if H8606_HVSISTEMAS
303 default 10 if BFIN527_EZKIT
304 default 10 if BFIN537_STAMP
305 default 11 if BFIN533_STAMP
310 depends on BFIN_KERNEL_CLOCK
315 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
318 If this is set the clock will be divided by 2, before it goes to the PLL.
322 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
324 default "22" if BFIN533_EZKIT
325 default "45" if BFIN533_STAMP
326 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
327 default "22" if BFIN533_BLUETECHNIX_CM
328 default "20" if BFIN537_BLUETECHNIX_CM
329 default "20" if BFIN561_BLUETECHNIX_CM
330 default "20" if BFIN561_EZKIT
331 default "16" if H8606_HVSISTEMAS
333 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
334 PLL Frequency = (Crystal Frequency) * (this setting)
337 prompt "Core Clock Divider"
338 depends on BFIN_KERNEL_CLOCK
341 This sets the frequency of the core. It can be 1, 2, 4 or 8
342 Core Frequency = (PLL frequency) / (this setting)
358 int "System Clock Divider"
359 depends on BFIN_KERNEL_CLOCK
361 default 5 if BFIN533_EZKIT
362 default 5 if BFIN533_STAMP
363 default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
364 default 5 if BFIN533_BLUETECHNIX_CM
365 default 4 if BFIN537_BLUETECHNIX_CM
366 default 4 if BFIN561_BLUETECHNIX_CM
367 default 5 if BFIN561_EZKIT
368 default 3 if H8606_HVSISTEMAS
370 This sets the frequency of the system clock (including SDRAM or DDR).
371 This can be between 1 and 15
372 System Clock = (PLL frequency) / (this setting)
375 # Max & Min Speeds for various Chips
379 default 600000000 if BF522
380 default 400000000 if BF523
381 default 400000000 if BF524
382 default 600000000 if BF525
383 default 400000000 if BF526
384 default 600000000 if BF527
385 default 400000000 if BF531
386 default 400000000 if BF532
387 default 750000000 if BF533
388 default 500000000 if BF534
389 default 400000000 if BF536
390 default 600000000 if BF537
391 default 533333333 if BF538
392 default 533333333 if BF539
393 default 600000000 if BF542
394 default 533333333 if BF544
395 default 600000000 if BF547
396 default 600000000 if BF548
397 default 533333333 if BF549
398 default 600000000 if BF561
412 comment "Kernel Timer/Scheduler"
414 source kernel/Kconfig.hz
420 config GENERIC_CLOCKEVENTS
421 bool "Generic clock events"
422 depends on GENERIC_TIME
425 config CYCLES_CLOCKSOURCE
426 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
427 depends on EXPERIMENTAL
428 depends on GENERIC_CLOCKEVENTS
429 depends on !BFIN_SCRATCH_REG_CYCLES
432 If you say Y here, you will enable support for using the 'cycles'
433 registers as a clock source. Doing so means you will be unable to
434 safely write to the 'cycles' register during runtime. You will
435 still be able to read it (such as for performance monitoring), but
436 writing the registers will most likely crash the kernel.
438 source kernel/time/Kconfig
440 comment "Memory Setup"
443 int "SDRAM Memory Size in MBytes"
444 default 32 if BFIN533_EZKIT
445 default 64 if BFIN527_EZKIT
446 default 64 if BFIN537_STAMP
447 default 64 if BFIN548_EZKIT
448 default 64 if BFIN561_EZKIT
449 default 128 if BFIN533_STAMP
451 default 32 if H8606_HVSISTEMAS
454 prompt "DDR SDRAM Chip Type"
455 depends on BFIN548_EZKIT
456 default MEM_MT46V32M16_5B
458 config MEM_MT46V32M16_6T
461 config MEM_MT46V32M16_5B
465 config ENET_FLASH_PIN
466 int "PF port/pin used for flash and ethernet sharing"
467 depends on (BFIN533_STAMP)
470 PF port/pin used for flash and ethernet sharing to allow other PF
471 pins to be used on other platforms without having to touch common
473 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
476 hex "Kernel load address for booting"
478 range 0x1000 0x20000000
480 This option allows you to set the load address of the kernel.
481 This can be useful if you are on a board which has a small amount
482 of memory or you wish to reserve some memory at the beginning of
485 Note that you need to keep this value above 4k (0x1000) as this
486 memory region is used to capture NULL pointer references as well
487 as some core kernel functions.
490 prompt "Blackfin Exception Scratch Register"
491 default BFIN_SCRATCH_REG_RETN
493 Select the resource to reserve for the Exception handler:
494 - RETN: Non-Maskable Interrupt (NMI)
495 - RETE: Exception Return (JTAG/ICE)
496 - CYCLES: Performance counter
498 If you are unsure, please select "RETN".
500 config BFIN_SCRATCH_REG_RETN
503 Use the RETN register in the Blackfin exception handler
504 as a stack scratch register. This means you cannot
505 safely use NMI on the Blackfin while running Linux, but
506 you can debug the system with a JTAG ICE and use the
507 CYCLES performance registers.
509 If you are unsure, please select "RETN".
511 config BFIN_SCRATCH_REG_RETE
514 Use the RETE register in the Blackfin exception handler
515 as a stack scratch register. This means you cannot
516 safely use a JTAG ICE while debugging a Blackfin board,
517 but you can safely use the CYCLES performance registers
520 If you are unsure, please select "RETN".
522 config BFIN_SCRATCH_REG_CYCLES
525 Use the CYCLES register in the Blackfin exception handler
526 as a stack scratch register. This means you cannot
527 safely use the CYCLES performance registers on a Blackfin
528 board at anytime, but you can debug the system with a JTAG
531 If you are unsure, please select "RETN".
538 menu "Blackfin Kernel Optimizations"
540 comment "Memory Optimizations"
543 bool "Locate interrupt entry code in L1 Memory"
546 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
547 into L1 instruction memory. (less latency)
549 config EXCPT_IRQ_SYSC_L1
550 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
553 If enabled, the entire ASM lowlevel exception and interrupt entry code
554 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
558 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
561 If enabled, the frequently called do_irq dispatcher function is linked
562 into L1 instruction memory. (less latency)
564 config CORE_TIMER_IRQ_L1
565 bool "Locate frequently called timer_interrupt() function in L1 Memory"
568 If enabled, the frequently called timer_interrupt() function is linked
569 into L1 instruction memory. (less latency)
572 bool "Locate frequently idle function in L1 Memory"
575 If enabled, the frequently called idle function is linked
576 into L1 instruction memory. (less latency)
579 bool "Locate kernel schedule function in L1 Memory"
582 If enabled, the frequently called kernel schedule is linked
583 into L1 instruction memory. (less latency)
585 config ARITHMETIC_OPS_L1
586 bool "Locate kernel owned arithmetic functions in L1 Memory"
589 If enabled, arithmetic functions are linked
590 into L1 instruction memory. (less latency)
593 bool "Locate access_ok function in L1 Memory"
596 If enabled, the access_ok function is linked
597 into L1 instruction memory. (less latency)
600 bool "Locate memset function in L1 Memory"
603 If enabled, the memset function is linked
604 into L1 instruction memory. (less latency)
607 bool "Locate memcpy function in L1 Memory"
610 If enabled, the memcpy function is linked
611 into L1 instruction memory. (less latency)
613 config SYS_BFIN_SPINLOCK_L1
614 bool "Locate sys_bfin_spinlock function in L1 Memory"
617 If enabled, sys_bfin_spinlock function is linked
618 into L1 instruction memory. (less latency)
620 config IP_CHECKSUM_L1
621 bool "Locate IP Checksum function in L1 Memory"
624 If enabled, the IP Checksum function is linked
625 into L1 instruction memory. (less latency)
627 config CACHELINE_ALIGNED_L1
628 bool "Locate cacheline_aligned data to L1 Data Memory"
633 If enabled, cacheline_anligned data is linked
634 into L1 data memory. (less latency)
636 config SYSCALL_TAB_L1
637 bool "Locate Syscall Table L1 Data Memory"
641 If enabled, the Syscall LUT is linked
642 into L1 data memory. (less latency)
644 config CPLB_SWITCH_TAB_L1
645 bool "Locate CPLB Switch Tables L1 Data Memory"
649 If enabled, the CPLB Switch Tables are linked
650 into L1 data memory. (less latency)
656 prompt "Kernel executes from"
658 Choose the memory type that the kernel will be running in.
663 The kernel will be resident in RAM when running.
668 The kernel will be resident in FLASH/ROM when running.
675 tristate "Enable Blackfin General Purpose Timers API"
678 Enable support for the General Purpose Timers API. If you
681 To compile this driver as a module, choose M here: the module
682 will be called gptimers.ko.
685 bool "Enable DMA Support"
686 depends on (BF52x || BF53x || BF561 || BF54x)
689 DMA driver for BF5xx.
692 prompt "Uncached SDRAM region"
693 default DMA_UNCACHED_1M
694 depends on BFIN_DMA_5XX
695 config DMA_UNCACHED_2M
696 bool "Enable 2M DMA region"
697 config DMA_UNCACHED_1M
698 bool "Enable 1M DMA region"
699 config DMA_UNCACHED_NONE
700 bool "Disable DMA region"
704 comment "Cache Support"
709 config BFIN_DCACHE_BANKA
710 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
711 depends on BFIN_DCACHE && !BF531
713 config BFIN_ICACHE_LOCK
714 bool "Enable Instruction Cache Locking"
718 depends on BFIN_DCACHE
724 Cached data will be written back to SDRAM only when needed.
725 This can give a nice increase in performance, but beware of
726 broken drivers that do not properly invalidate/flush their
729 Write Through Policy:
730 Cached data will always be written back to SDRAM when the
731 cache is updated. This is a completely safe setting, but
732 performance is worse than Write Back.
734 If you are unsure of the options and you want to be safe,
735 then go with Write Through.
741 Cached data will be written back to SDRAM only when needed.
742 This can give a nice increase in performance, but beware of
743 broken drivers that do not properly invalidate/flush their
746 Write Through Policy:
747 Cached data will always be written back to SDRAM when the
748 cache is updated. This is a completely safe setting, but
749 performance is worse than Write Back.
751 If you are unsure of the options and you want to be safe,
752 then go with Write Through.
757 int "Set the max L1 SRAM pieces"
760 Set the max memory pieces for the L1 SRAM allocation algorithm.
761 Min value is 16. Max value is 1024.
765 bool "Enable the memory protection unit (EXPERIMENTAL)"
768 Use the processor's MPU to protect applications from accessing
769 memory they do not own. This comes at a performance penalty
770 and is recommended only for debugging.
772 comment "Asynchonous Memory Configuration"
774 menu "EBIU_AMGCTL Global Control"
780 bool "DMA has priority over core for ext. accesses"
785 bool "Bank 0 16 bit packing enable"
790 bool "Bank 1 16 bit packing enable"
795 bool "Bank 2 16 bit packing enable"
800 bool "Bank 3 16 bit packing enable"
804 prompt"Enable Asynchonous Memory Banks"
808 bool "Disable All Banks"
814 bool "Enable Bank 0 & 1"
816 config C_AMBEN_B0_B1_B2
817 bool "Enable Bank 0 & 1 & 2"
820 bool "Enable All Banks"
824 menu "EBIU_AMBCTL Control"
842 config EBIU_MBSCTLVAL
843 hex "EBIU Bank Select Control Register"
848 hex "Flash Memory Mode Control Register"
853 hex "Flash Memory Bank Control Register"
858 #############################################################################
859 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
866 source "drivers/pci/Kconfig"
869 bool "Support for hot-pluggable device"
871 Say Y here if you want to plug devices into your computer while
872 the system is running, and be able to use them quickly. In many
873 cases, the devices can likewise be unplugged at any time too.
875 One well known example of this is PCMCIA- or PC-cards, credit-card
876 size devices such as network cards, modems or hard drives which are
877 plugged into slots found on all modern laptop computers. Another
878 example, used on modern desktops as well as laptops, is USB.
880 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
881 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
882 Then your kernel will automatically call out to a user mode "policy
883 agent" (/sbin/hotplug) to load modules and set up software needed
884 to use devices as you hotplug them.
886 source "drivers/pcmcia/Kconfig"
888 source "drivers/pci/hotplug/Kconfig"
892 menu "Executable file formats"
894 source "fs/Kconfig.binfmt"
898 menu "Power management options"
899 source "kernel/power/Kconfig"
901 config ARCH_SUSPEND_POSSIBLE
906 prompt "Default Power Saving Mode"
908 default PM_BFIN_SLEEP_DEEPER
909 config PM_BFIN_SLEEP_DEEPER
912 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
913 power dissipation by disabling the clock to the processor core (CCLK).
914 Furthermore, Standby sets the internal power supply voltage (VDDINT)
915 to 0.85 V to provide the greatest power savings, while preserving the
917 The PLL and system clock (SCLK) continue to operate at a very low
918 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
919 the SDRAM is put into Self Refresh Mode. Typically an external event
920 such as GPIO interrupt or RTC activity wakes up the processor.
921 Various Peripherals such as UART, SPORT, PPI may not function as
922 normal during Sleep Deeper, due to the reduced SCLK frequency.
923 When in the sleep mode, system DMA access to L1 memory is not supported.
928 Sleep Mode (High Power Savings) - The sleep mode reduces power
929 dissipation by disabling the clock to the processor core (CCLK).
930 The PLL and system clock (SCLK), however, continue to operate in
931 this mode. Typically an external event or RTC activity will wake
932 up the processor. When in the sleep mode,
933 system DMA access to L1 memory is not supported.
936 config PM_WAKEUP_BY_GPIO
937 bool "Cause Wakeup Event by GPIO"
939 config PM_WAKEUP_GPIO_NUMBER
940 int "Wakeup GPIO number"
942 depends on PM_WAKEUP_BY_GPIO
943 default 2 if BFIN537_STAMP
946 prompt "GPIO Polarity"
947 depends on PM_WAKEUP_BY_GPIO
948 default PM_WAKEUP_GPIO_POLAR_H
949 config PM_WAKEUP_GPIO_POLAR_H
951 config PM_WAKEUP_GPIO_POLAR_L
953 config PM_WAKEUP_GPIO_POLAR_EDGE_F
955 config PM_WAKEUP_GPIO_POLAR_EDGE_R
957 config PM_WAKEUP_GPIO_POLAR_EDGE_B
963 if (BF537 || BF533 || BF54x)
965 menu "CPU Frequency scaling"
967 source "drivers/cpufreq/Kconfig"
973 If you want to enable this option, you should select the
974 DPMC driver from Character Devices.
981 source "drivers/Kconfig"
985 source "arch/blackfin/Kconfig.debug"
987 source "security/Kconfig"
989 source "crypto/Kconfig"