1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
25 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
27 static int cachesize_override __cpuinitdata = -1;
28 static int disable_x86_fxsr __cpuinitdata;
29 static int disable_x86_serial_nr __cpuinitdata = 1;
30 static int disable_x86_sep __cpuinitdata;
32 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
34 extern int disable_pse;
36 static void __cpuinit default_init(struct cpuinfo_x86 * c)
38 /* Not much we can do here... */
39 /* Check if at least it has cpuid */
40 if (c->cpuid_level == -1) {
41 /* No cpuid. It must be an ancient CPU */
43 strcpy(c->x86_model_id, "486");
45 strcpy(c->x86_model_id, "386");
49 static struct cpu_dev __cpuinitdata default_cpu = {
50 .c_init = default_init,
51 .c_vendor = "Unknown",
53 static struct cpu_dev * this_cpu = &default_cpu;
55 static int __init cachesize_setup(char *str)
57 get_option (&str, &cachesize_override);
60 __setup("cachesize=", cachesize_setup);
62 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
67 if (cpuid_eax(0x80000000) < 0x80000004)
70 v = (unsigned int *) c->x86_model_id;
71 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
72 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
73 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
74 c->x86_model_id[48] = 0;
76 /* Intel chips right-justify this string for some dumb reason;
77 undo that brain damage */
78 p = q = &c->x86_model_id[0];
84 while ( q <= &c->x86_model_id[48] )
85 *q++ = '\0'; /* Zero-pad the rest */
92 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
94 unsigned int n, dummy, ecx, edx, l2size;
96 n = cpuid_eax(0x80000000);
98 if (n >= 0x80000005) {
99 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
100 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
101 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
102 c->x86_cache_size=(ecx>>24)+(edx>>24);
105 if (n < 0x80000006) /* Some chips just has a large L1. */
108 ecx = cpuid_ecx(0x80000006);
111 /* do processor-specific cache resizing */
112 if (this_cpu->c_size_cache)
113 l2size = this_cpu->c_size_cache(c,l2size);
115 /* Allow user to override all this if necessary. */
116 if (cachesize_override != -1)
117 l2size = cachesize_override;
120 return; /* Again, no L2 cache is possible */
122 c->x86_cache_size = l2size;
124 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
128 /* Naming convention should be: <Name> [(<Codename>)] */
129 /* This table only is used unless init_<vendor>() below doesn't set it; */
130 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
132 /* Look up CPU names by table lookup. */
133 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
135 struct cpu_model_info *info;
137 if ( c->x86_model >= 16 )
138 return NULL; /* Range check */
143 info = this_cpu->c_models;
145 while (info && info->family) {
146 if (info->family == c->x86)
147 return info->model_names[c->x86_model];
150 return NULL; /* Not found */
154 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
156 char *v = c->x86_vendor_id;
160 for (i = 0; i < X86_VENDOR_NUM; i++) {
162 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
163 (cpu_devs[i]->c_ident[1] &&
164 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
167 this_cpu = cpu_devs[i];
174 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
175 printk(KERN_ERR "CPU: Your system may be unstable.\n");
177 c->x86_vendor = X86_VENDOR_UNKNOWN;
178 this_cpu = &default_cpu;
182 static int __init x86_fxsr_setup(char * s)
184 /* Tell all the other CPU's to not use it... */
185 disable_x86_fxsr = 1;
188 * ... and clear the bits early in the boot_cpu_data
189 * so that the bootup process doesn't try to do this
192 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
193 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
196 __setup("nofxsr", x86_fxsr_setup);
199 static int __init x86_sep_setup(char * s)
204 __setup("nosep", x86_sep_setup);
207 /* Standard macro to see if a specific flag is changeable */
208 static inline int flag_is_changeable_p(u32 flag)
222 : "=&r" (f1), "=&r" (f2)
225 return ((f1^f2) & flag) != 0;
229 /* Probe for the CPUID instruction */
230 static int __cpuinit have_cpuid_p(void)
232 return flag_is_changeable_p(X86_EFLAGS_ID);
235 /* Do minimum CPU detection early.
236 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
237 The others are not touched to avoid unwanted side effects.
239 WARNING: this function is only called on the BP. Don't add code here
240 that is supposed to run on all CPUs. */
241 static void __init early_cpu_detect(void)
243 struct cpuinfo_x86 *c = &boot_cpu_data;
245 c->x86_cache_alignment = 32;
250 /* Get vendor name */
251 cpuid(0x00000000, &c->cpuid_level,
252 (int *)&c->x86_vendor_id[0],
253 (int *)&c->x86_vendor_id[8],
254 (int *)&c->x86_vendor_id[4]);
256 get_cpu_vendor(c, 1);
259 if (c->cpuid_level >= 0x00000001) {
260 u32 junk, tfms, cap0, misc;
261 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
262 c->x86 = (tfms >> 8) & 15;
263 c->x86_model = (tfms >> 4) & 15;
265 c->x86 += (tfms >> 20) & 0xff;
267 c->x86_model += ((tfms >> 16) & 0xF) << 4;
268 c->x86_mask = tfms & 15;
270 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
274 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
279 if (have_cpuid_p()) {
280 /* Get vendor name */
281 cpuid(0x00000000, &c->cpuid_level,
282 (int *)&c->x86_vendor_id[0],
283 (int *)&c->x86_vendor_id[8],
284 (int *)&c->x86_vendor_id[4]);
286 get_cpu_vendor(c, 0);
287 /* Initialize the standard set of capabilities */
288 /* Note that the vendor-specific code below might override */
290 /* Intel-defined flags: level 0x00000001 */
291 if ( c->cpuid_level >= 0x00000001 ) {
292 u32 capability, excap;
293 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
294 c->x86_capability[0] = capability;
295 c->x86_capability[4] = excap;
296 c->x86 = (tfms >> 8) & 15;
297 c->x86_model = (tfms >> 4) & 15;
299 c->x86 += (tfms >> 20) & 0xff;
301 c->x86_model += ((tfms >> 16) & 0xF) << 4;
302 c->x86_mask = tfms & 15;
304 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
306 c->apicid = (ebx >> 24) & 0xFF;
309 /* Have CPUID level 0 only - unheard of */
313 /* AMD-defined flags: level 0x80000001 */
314 xlvl = cpuid_eax(0x80000000);
315 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
316 if ( xlvl >= 0x80000001 ) {
317 c->x86_capability[1] = cpuid_edx(0x80000001);
318 c->x86_capability[6] = cpuid_ecx(0x80000001);
320 if ( xlvl >= 0x80000004 )
321 get_model_name(c); /* Default name */
325 early_intel_workaround(c);
328 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
332 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
334 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
335 /* Disable processor serial number */
337 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
339 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
340 printk(KERN_NOTICE "CPU serial number disabled.\n");
341 clear_bit(X86_FEATURE_PN, c->x86_capability);
343 /* Disabling the serial number may affect the cpuid level */
344 c->cpuid_level = cpuid_eax(0);
348 static int __init x86_serial_nr_setup(char *s)
350 disable_x86_serial_nr = 0;
353 __setup("serialnumber", x86_serial_nr_setup);
358 * This does the hard work of actually picking apart the CPU stuff...
360 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
364 c->loops_per_jiffy = loops_per_jiffy;
365 c->x86_cache_size = -1;
366 c->x86_vendor = X86_VENDOR_UNKNOWN;
367 c->cpuid_level = -1; /* CPUID not detected */
368 c->x86_model = c->x86_mask = 0; /* So far unknown... */
369 c->x86_vendor_id[0] = '\0'; /* Unset */
370 c->x86_model_id[0] = '\0'; /* Unset */
371 c->x86_max_cores = 1;
372 memset(&c->x86_capability, 0, sizeof c->x86_capability);
374 if (!have_cpuid_p()) {
375 /* First of all, decide if this is a 486 or higher */
376 /* It's a 486 if we can modify the AC flag */
377 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
385 printk(KERN_DEBUG "CPU: After generic identify, caps:");
386 for (i = 0; i < NCAPINTS; i++)
387 printk(" %08lx", c->x86_capability[i]);
390 if (this_cpu->c_identify) {
391 this_cpu->c_identify(c);
393 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
394 for (i = 0; i < NCAPINTS; i++)
395 printk(" %08lx", c->x86_capability[i]);
400 * Vendor-specific initialization. In this section we
401 * canonicalize the feature flags, meaning if there are
402 * features a certain CPU supports which CPUID doesn't
403 * tell us, CPUID claiming incorrect flags, or other bugs,
404 * we handle them here.
406 * At the end of this section, c->x86_capability better
407 * indicate the features this CPU genuinely supports!
409 if (this_cpu->c_init)
412 /* Disable the PN if appropriate */
413 squash_the_stupid_serial_number(c);
416 * The vendor-specific functions might have changed features. Now
417 * we do "generic changes."
422 clear_bit(X86_FEATURE_TSC, c->x86_capability);
425 if (disable_x86_fxsr) {
426 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
427 clear_bit(X86_FEATURE_XMM, c->x86_capability);
432 clear_bit(X86_FEATURE_SEP, c->x86_capability);
435 clear_bit(X86_FEATURE_PSE, c->x86_capability);
437 /* If the model name is still unset, do table lookup. */
438 if ( !c->x86_model_id[0] ) {
440 p = table_lookup_model(c);
442 strcpy(c->x86_model_id, p);
445 sprintf(c->x86_model_id, "%02x/%02x",
446 c->x86, c->x86_model);
449 /* Now the feature flags better reflect actual CPU features! */
451 printk(KERN_DEBUG "CPU: After all inits, caps:");
452 for (i = 0; i < NCAPINTS; i++)
453 printk(" %08lx", c->x86_capability[i]);
457 * On SMP, boot_cpu_data holds the common feature set between
458 * all CPUs; so make sure that we indicate which features are
459 * common between the CPUs. The first time this routine gets
460 * executed, c == &boot_cpu_data.
462 if ( c != &boot_cpu_data ) {
463 /* AND the already accumulated flags with these */
464 for ( i = 0 ; i < NCAPINTS ; i++ )
465 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
468 /* Init Machine Check Exception if available. */
471 if (c == &boot_cpu_data)
475 if (c == &boot_cpu_data)
482 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
484 u32 eax, ebx, ecx, edx;
485 int index_msb, core_bits;
487 cpuid(1, &eax, &ebx, &ecx, &edx);
489 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
492 smp_num_siblings = (ebx & 0xff0000) >> 16;
494 if (smp_num_siblings == 1) {
495 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
496 } else if (smp_num_siblings > 1 ) {
498 if (smp_num_siblings > NR_CPUS) {
499 printk(KERN_WARNING "CPU: Unsupported number of the "
500 "siblings %d", smp_num_siblings);
501 smp_num_siblings = 1;
505 index_msb = get_count_order(smp_num_siblings);
506 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
508 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
511 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
513 index_msb = get_count_order(smp_num_siblings) ;
515 core_bits = get_count_order(c->x86_max_cores);
517 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
518 ((1 << core_bits) - 1);
520 if (c->x86_max_cores > 1)
521 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
527 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
531 if (c->x86_vendor < X86_VENDOR_NUM)
532 vendor = this_cpu->c_vendor;
533 else if (c->cpuid_level >= 0)
534 vendor = c->x86_vendor_id;
536 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
537 printk("%s ", vendor);
539 if (!c->x86_model_id[0])
540 printk("%d86", c->x86);
542 printk("%s", c->x86_model_id);
544 if (c->x86_mask || c->cpuid_level >= 0)
545 printk(" stepping %02x\n", c->x86_mask);
550 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
553 * We're emulating future behavior.
554 * In the future, the cpu-specific init functions will be called implicitly
555 * via the magic of initcalls.
556 * They will insert themselves into the cpu_devs structure.
557 * Then, when cpu_init() is called, we can just iterate over that array.
560 extern int intel_cpu_init(void);
561 extern int cyrix_init_cpu(void);
562 extern int nsc_init_cpu(void);
563 extern int amd_init_cpu(void);
564 extern int centaur_init_cpu(void);
565 extern int transmeta_init_cpu(void);
566 extern int rise_init_cpu(void);
567 extern int nexgen_init_cpu(void);
568 extern int umc_init_cpu(void);
570 void __init early_cpu_init(void)
577 transmeta_init_cpu();
583 #ifdef CONFIG_DEBUG_PAGEALLOC
584 /* pse is not compatible with on-the-fly unmapping,
585 * disable it even if the cpus claim to support it.
587 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
592 * cpu_init() initializes state that is per-CPU. Some data is already
593 * initialized (naturally) in the bootstrap process, such as the GDT
594 * and IDT. We reload them nevertheless, this function acts as a
595 * 'CPU state barrier', nothing should get across.
597 void __cpuinit cpu_init(void)
599 int cpu = smp_processor_id();
600 struct tss_struct * t = &per_cpu(init_tss, cpu);
601 struct thread_struct *thread = ¤t->thread;
602 struct desc_struct *gdt;
603 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
605 if (cpu_test_and_set(cpu, cpu_initialized)) {
606 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
607 for (;;) local_irq_enable();
609 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
611 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
612 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
613 if (tsc_disable && cpu_has_tsc) {
614 printk(KERN_NOTICE "Disabling TSC...\n");
615 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
616 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
617 set_in_cr4(X86_CR4_TSD);
620 /* The CPU hotplug case */
621 if (cpu_gdt_descr->address) {
622 gdt = (struct desc_struct *)cpu_gdt_descr->address;
623 memset(gdt, 0, PAGE_SIZE);
627 * This is a horrible hack to allocate the GDT. The problem
628 * is that cpu_init() is called really early for the boot CPU
629 * (and hence needs bootmem) but much later for the secondary
630 * CPUs, when bootmem will have gone away
632 if (NODE_DATA(0)->bdata->node_bootmem_map) {
633 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
634 /* alloc_bootmem_pages panics on failure, so no check */
635 memset(gdt, 0, PAGE_SIZE);
637 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
638 if (unlikely(!gdt)) {
639 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
646 * Initialize the per-CPU GDT with the boot GDT,
647 * and set up the GDT descriptor:
649 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
650 cpu_gdt_descr->size = GDT_SIZE - 1;
651 cpu_gdt_descr->address = (unsigned long)gdt;
653 load_gdt(cpu_gdt_descr);
654 load_idt(&idt_descr);
657 * Set up and load the per-CPU TSS and LDT
659 atomic_inc(&init_mm.mm_count);
660 current->active_mm = &init_mm;
662 enter_lazy_tlb(&init_mm, current);
664 load_esp0(t, thread);
667 load_LDT(&init_mm.context);
669 #ifdef CONFIG_DOUBLEFAULT
670 /* Set up doublefault TSS pointer in the GDT */
671 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
674 /* Clear %fs and %gs. */
675 asm volatile ("movl %0, %%fs; movl %0, %%gs" : : "r" (0));
677 /* Clear all 6 debug registers: */
686 * Force FPU initialization:
688 current_thread_info()->status = 0;
690 mxcsr_feature_mask_init();
693 #ifdef CONFIG_HOTPLUG_CPU
694 void __cpuinit cpu_uninit(void)
696 int cpu = raw_smp_processor_id();
697 cpu_clear(cpu, cpu_initialized);
700 per_cpu(cpu_tlbstate, cpu).state = 0;
701 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;