2 * Pentium 4/Xeon CPU on demand clock modulation/speed scaling
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
5 * (C) 2002 Arjan van de Ven <arjanv@redhat.com>
6 * (C) 2002 Tora T. Engstad
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * The author(s) of this software shall not be held liable for damages
15 * of any nature resulting due to the use of this software. This
16 * software is provided AS-IS with no warranties.
18 * Date Errata Description
19 * 20020525 N44, O17 12.5% or 25% DC causes lockup
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/smp.h>
28 #include <linux/cpufreq.h>
29 #include <linux/slab.h>
30 #include <linux/cpumask.h>
32 #include <asm/processor.h>
34 #include <asm/timex.h>
36 #include "speedstep-lib.h"
38 #define PFX "p4-clockmod: "
39 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)
42 * Duty Cycle (3bits), note DC_DISABLE is not specified in
43 * intel docs i just use it to mean disable
46 DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
47 DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
53 static int has_N44_O17_errata[NR_CPUS];
54 static unsigned int stock_freq;
55 static struct cpufreq_driver p4clockmod_driver;
56 static unsigned int cpufreq_p4_get(unsigned int cpu);
58 static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
62 if (!cpu_online(cpu) || (newstate > DC_DISABLE) || (newstate == DC_RESV))
65 rdmsr(MSR_IA32_THERM_STATUS, l, h);
68 dprintk("CPU#%d currently thermal throttled\n", cpu);
70 if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
73 rdmsr(MSR_IA32_THERM_CONTROL, l, h);
74 if (newstate == DC_DISABLE) {
75 dprintk("CPU#%d disabling modulation\n", cpu);
76 wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
78 dprintk("CPU#%d setting duty cycle to %d%%\n",
79 cpu, ((125 * newstate) / 10));
80 /* bits 63 - 5 : reserved
81 * bit 4 : enable/disable
82 * bits 3-1 : duty cycle
86 l = l | (1<<4) | ((newstate & 0x7)<<1);
87 wrmsr(MSR_IA32_THERM_CONTROL, l, h);
94 static struct cpufreq_frequency_table p4clockmod_table[] = {
95 {DC_RESV, CPUFREQ_ENTRY_INVALID},
104 {DC_RESV, CPUFREQ_TABLE_END},
108 static int cpufreq_p4_target(struct cpufreq_policy *policy,
109 unsigned int target_freq,
110 unsigned int relation)
112 unsigned int newstate = DC_RESV;
113 struct cpufreq_freqs freqs;
114 cpumask_t cpus_allowed;
117 if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
120 freqs.old = cpufreq_p4_get(policy->cpu);
121 freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
123 if (freqs.new == freqs.old)
127 for_each_cpu_mask(i, policy->cpus) {
129 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
132 /* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
133 * Developer's Manual, Volume 3
135 cpus_allowed = current->cpus_allowed;
137 for_each_cpu_mask(i, policy->cpus) {
138 cpumask_t this_cpu = cpumask_of_cpu(i);
140 set_cpus_allowed(current, this_cpu);
141 BUG_ON(smp_processor_id() != i);
143 cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
145 set_cpus_allowed(current, cpus_allowed);
148 for_each_cpu_mask(i, policy->cpus) {
150 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
157 static int cpufreq_p4_verify(struct cpufreq_policy *policy)
159 return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
163 static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
165 if ((c->x86 == 0x06) && (c->x86_model == 0x09)) {
166 /* Pentium M (Banias) */
167 printk(KERN_WARNING PFX "Warning: Pentium M detected. "
168 "The speedstep_centrino module offers voltage scaling"
169 " in addition of frequency scaling. You should use "
170 "that instead of p4-clockmod, if possible.\n");
171 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
174 if ((c->x86 == 0x06) && (c->x86_model == 0x0D)) {
175 /* Pentium M (Dothan) */
176 printk(KERN_WARNING PFX "Warning: Pentium M detected. "
177 "The speedstep_centrino module offers voltage scaling"
178 " in addition of frequency scaling. You should use "
179 "that instead of p4-clockmod, if possible.\n");
180 /* on P-4s, the TSC runs with constant frequency independent whether
181 * throttling is active or not. */
182 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
183 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
187 printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <linux@brodo.de>\n");
191 /* on P-4s, the TSC runs with constant frequency independent whether
192 * throttling is active or not. */
193 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
195 if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
196 printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
197 "The speedstep-ich or acpi cpufreq modules offer "
198 "voltage scaling in addition of frequency scaling. "
199 "You should use either one instead of p4-clockmod, "
201 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
204 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
209 static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
211 struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
216 policy->cpus = cpu_sibling_map[policy->cpu];
219 /* Errata workaround */
220 cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
226 has_N44_O17_errata[policy->cpu] = 1;
227 dprintk("has errata -- disabling low frequencies\n");
230 /* get max frequency */
231 stock_freq = cpufreq_p4_get_frequency(c);
236 for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
237 if ((i<2) && (has_N44_O17_errata[policy->cpu]))
238 p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
240 p4clockmod_table[i].frequency = (stock_freq * i)/8;
242 cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
244 /* cpuinfo and default policy values */
245 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
246 policy->cpuinfo.transition_latency = 1000000; /* assumed */
247 policy->cur = stock_freq;
249 return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
253 static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
255 cpufreq_frequency_table_put_attr(policy->cpu);
259 static unsigned int cpufreq_p4_get(unsigned int cpu)
261 cpumask_t cpus_allowed;
264 cpus_allowed = current->cpus_allowed;
266 set_cpus_allowed(current, cpumask_of_cpu(cpu));
267 BUG_ON(smp_processor_id() != cpu);
269 rdmsr(MSR_IA32_THERM_CONTROL, l, h);
271 set_cpus_allowed(current, cpus_allowed);
280 return (stock_freq * l / 8);
285 static struct freq_attr* p4clockmod_attr[] = {
286 &cpufreq_freq_attr_scaling_available_freqs,
290 static struct cpufreq_driver p4clockmod_driver = {
291 .verify = cpufreq_p4_verify,
292 .target = cpufreq_p4_target,
293 .init = cpufreq_p4_cpu_init,
294 .exit = cpufreq_p4_cpu_exit,
295 .get = cpufreq_p4_get,
296 .name = "p4-clockmod",
297 .owner = THIS_MODULE,
298 .attr = p4clockmod_attr,
302 static int __init cpufreq_p4_init(void)
304 struct cpuinfo_x86 *c = cpu_data;
308 * THERM_CONTROL is architectural for IA32 now, so
309 * we can rely on the capability checks
311 if (c->x86_vendor != X86_VENDOR_INTEL)
314 if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
315 !test_bit(X86_FEATURE_ACC, c->x86_capability))
318 ret = cpufreq_register_driver(&p4clockmod_driver);
320 printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
326 static void __exit cpufreq_p4_exit(void)
328 cpufreq_unregister_driver(&p4clockmod_driver);
332 MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>");
333 MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
334 MODULE_LICENSE ("GPL");
336 late_initcall(cpufreq_p4_init);
337 module_exit(cpufreq_p4_exit);