2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/bitops.h>
30 #include <asm/mpspec.h>
31 #include <asm/io_apic.h>
33 #include <mach_apic.h>
34 #include <mach_mpparse.h>
35 #include <bios_ebda.h>
37 /* Have we found an MP table */
39 unsigned int __initdata maxcpus = NR_CPUS;
41 #ifdef CONFIG_HOTPLUG_CPU
42 #define CPU_HOTPLUG_ENABLED (1)
44 #define CPU_HOTPLUG_ENABLED (0)
48 * Various Linux-internal data structures created from the
51 int apic_version [MAX_APICS];
52 int mp_bus_id_to_type [MAX_MP_BUSSES];
53 int mp_bus_id_to_node [MAX_MP_BUSSES];
54 int mp_bus_id_to_local [MAX_MP_BUSSES];
55 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
56 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
57 static int mp_current_pci_id;
59 /* I/O APIC entries */
60 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
62 /* # of MP IRQ source entries */
63 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
65 /* MP IRQ source entries */
71 unsigned long mp_lapic_addr;
73 unsigned int def_to_bigsmp = 0;
75 /* Processor that is doing the boot up */
76 unsigned int boot_cpu_physical_apicid = -1U;
77 /* Internal processor count */
78 static unsigned int __devinitdata num_processors;
80 /* Bitmask of physically existing CPUs */
81 physid_mask_t phys_cpu_present_map;
83 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
86 * Intel MP BIOS table parsing routines:
91 * Checksum an MP configuration block.
94 static int __init mpf_checksum(unsigned char *mp, int len)
105 * Have to match translation table entries to main table entries by counter
106 * hence the mpc_record variable .... can't see a less disgusting way of
110 static int mpc_record;
111 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
113 static void __devinit MP_processor_info (struct mpc_config_processor *m)
116 physid_mask_t phys_cpu;
118 if (!(m->mpc_cpuflag & CPU_ENABLED))
121 apicid = mpc_apic_id(m, translation_table[mpc_record]);
123 if (m->mpc_featureflag&(1<<0))
124 Dprintk(" Floating point unit present.\n");
125 if (m->mpc_featureflag&(1<<7))
126 Dprintk(" Machine Exception supported.\n");
127 if (m->mpc_featureflag&(1<<8))
128 Dprintk(" 64 bit compare & exchange supported.\n");
129 if (m->mpc_featureflag&(1<<9))
130 Dprintk(" Internal APIC present.\n");
131 if (m->mpc_featureflag&(1<<11))
132 Dprintk(" SEP present.\n");
133 if (m->mpc_featureflag&(1<<12))
134 Dprintk(" MTRR present.\n");
135 if (m->mpc_featureflag&(1<<13))
136 Dprintk(" PGE present.\n");
137 if (m->mpc_featureflag&(1<<14))
138 Dprintk(" MCA present.\n");
139 if (m->mpc_featureflag&(1<<15))
140 Dprintk(" CMOV present.\n");
141 if (m->mpc_featureflag&(1<<16))
142 Dprintk(" PAT present.\n");
143 if (m->mpc_featureflag&(1<<17))
144 Dprintk(" PSE present.\n");
145 if (m->mpc_featureflag&(1<<18))
146 Dprintk(" PSN present.\n");
147 if (m->mpc_featureflag&(1<<19))
148 Dprintk(" Cache Line Flush Instruction present.\n");
150 if (m->mpc_featureflag&(1<<21))
151 Dprintk(" Debug Trace and EMON Store present.\n");
152 if (m->mpc_featureflag&(1<<22))
153 Dprintk(" ACPI Thermal Throttle Registers present.\n");
154 if (m->mpc_featureflag&(1<<23))
155 Dprintk(" MMX present.\n");
156 if (m->mpc_featureflag&(1<<24))
157 Dprintk(" FXSR present.\n");
158 if (m->mpc_featureflag&(1<<25))
159 Dprintk(" XMM present.\n");
160 if (m->mpc_featureflag&(1<<26))
161 Dprintk(" Willamette New Instructions present.\n");
162 if (m->mpc_featureflag&(1<<27))
163 Dprintk(" Self Snoop present.\n");
164 if (m->mpc_featureflag&(1<<28))
165 Dprintk(" HT present.\n");
166 if (m->mpc_featureflag&(1<<29))
167 Dprintk(" Thermal Monitor present.\n");
168 /* 30, 31 Reserved */
171 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
172 Dprintk(" Bootup CPU\n");
173 boot_cpu_physical_apicid = m->mpc_apicid;
176 ver = m->mpc_apicver;
182 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
183 "fixing up to 0x10. (tell your hw vendor)\n",
187 apic_version[m->mpc_apicid] = ver;
189 phys_cpu = apicid_to_cpu_present(apicid);
190 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
192 if (num_processors >= NR_CPUS) {
193 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
194 " Processor ignored.\n", NR_CPUS);
198 if (num_processors >= maxcpus) {
199 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
200 " Processor ignored.\n", maxcpus);
204 cpu_set(num_processors, cpu_possible_map);
207 if (CPU_HOTPLUG_ENABLED || (num_processors > 8)) {
208 switch (boot_cpu_data.x86_vendor) {
209 case X86_VENDOR_INTEL:
210 if (!APIC_XAPIC(ver)) {
214 /* If P4 and above fall through */
219 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
222 static void __init MP_bus_info (struct mpc_config_bus *m)
226 memcpy(str, m->mpc_bustype, 6);
229 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
231 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
232 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
233 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
234 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
235 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
236 mpc_oem_pci_bus(m, translation_table[mpc_record]);
237 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
238 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
240 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
241 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
242 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
243 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
245 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
249 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
251 if (!(m->mpc_flags & MPC_APIC_USABLE))
254 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
255 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
256 if (nr_ioapics >= MAX_IO_APICS) {
257 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
258 MAX_IO_APICS, nr_ioapics);
259 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
261 if (!m->mpc_apicaddr) {
262 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
263 " found in MP table, skipping!\n");
266 mp_ioapics[nr_ioapics] = *m;
270 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
272 mp_irqs [mp_irq_entries] = *m;
273 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
274 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
275 m->mpc_irqtype, m->mpc_irqflag & 3,
276 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
277 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
278 if (++mp_irq_entries == MAX_IRQ_SOURCES)
279 panic("Max # of irq sources exceeded!!\n");
282 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
284 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
285 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
286 m->mpc_irqtype, m->mpc_irqflag & 3,
287 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
288 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
290 * Well it seems all SMP boards in existence
291 * use ExtINT/LVT1 == LINT0 and
292 * NMI/LVT2 == LINT1 - the following check
293 * will show us if this assumptions is false.
294 * Until then we do not have to add baggage.
296 if ((m->mpc_irqtype == mp_ExtINT) &&
297 (m->mpc_destapiclint != 0))
299 if ((m->mpc_irqtype == mp_NMI) &&
300 (m->mpc_destapiclint != 1))
304 #ifdef CONFIG_X86_NUMAQ
305 static void __init MP_translation_info (struct mpc_config_translation *m)
307 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
309 if (mpc_record >= MAX_MPC_ENTRY)
310 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
312 translation_table[mpc_record] = m; /* stash this for later */
313 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
314 node_set_online(m->trans_quad);
318 * Read/parse the MPC oem tables
321 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
322 unsigned short oemsize)
324 int count = sizeof (*oemtable); /* the header size */
325 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
328 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
329 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
331 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
332 oemtable->oem_signature[0],
333 oemtable->oem_signature[1],
334 oemtable->oem_signature[2],
335 oemtable->oem_signature[3]);
338 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
340 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
343 while (count < oemtable->oem_length) {
347 struct mpc_config_translation *m=
348 (struct mpc_config_translation *)oemptr;
349 MP_translation_info(m);
350 oemptr += sizeof(*m);
357 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
364 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
367 if (strncmp(oem, "IBM NUMA", 8))
368 printk("Warning! May not be a NUMA-Q system!\n");
370 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
373 #endif /* CONFIG_X86_NUMAQ */
379 static int __init smp_read_mpc(struct mp_config_table *mpc)
383 int count=sizeof(*mpc);
384 unsigned char *mpt=((unsigned char *)mpc)+count;
386 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
387 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
388 *(u32 *)mpc->mpc_signature);
391 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
392 printk(KERN_ERR "SMP mptable: checksum error!\n");
395 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
396 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
400 if (!mpc->mpc_lapic) {
401 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
404 memcpy(oem,mpc->mpc_oem,8);
406 printk(KERN_INFO "OEM ID: %s ",oem);
408 memcpy(str,mpc->mpc_productid,12);
410 printk("Product ID: %s ",str);
412 mps_oem_check(mpc, oem, str);
414 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
417 * Save the local APIC address (it might be non-default) -- but only
418 * if we're not using ACPI.
421 mp_lapic_addr = mpc->mpc_lapic;
424 * Now process the configuration blocks.
427 while (count < mpc->mpc_length) {
431 struct mpc_config_processor *m=
432 (struct mpc_config_processor *)mpt;
433 /* ACPI may have already provided this data */
435 MP_processor_info(m);
442 struct mpc_config_bus *m=
443 (struct mpc_config_bus *)mpt;
451 struct mpc_config_ioapic *m=
452 (struct mpc_config_ioapic *)mpt;
460 struct mpc_config_intsrc *m=
461 (struct mpc_config_intsrc *)mpt;
470 struct mpc_config_lintsrc *m=
471 (struct mpc_config_lintsrc *)mpt;
479 count = mpc->mpc_length;
485 clustered_apic_check();
487 printk(KERN_ERR "SMP mptable: no processors registered!\n");
488 return num_processors;
491 static int __init ELCR_trigger(unsigned int irq)
495 port = 0x4d0 + (irq >> 3);
496 return (inb(port) >> (irq & 7)) & 1;
499 static void __init construct_default_ioirq_mptable(int mpc_default_type)
501 struct mpc_config_intsrc intsrc;
503 int ELCR_fallback = 0;
505 intsrc.mpc_type = MP_INTSRC;
506 intsrc.mpc_irqflag = 0; /* conforming */
507 intsrc.mpc_srcbus = 0;
508 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
510 intsrc.mpc_irqtype = mp_INT;
513 * If true, we have an ISA/PCI system with no IRQ entries
514 * in the MP table. To prevent the PCI interrupts from being set up
515 * incorrectly, we try to use the ELCR. The sanity check to see if
516 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
517 * never be level sensitive, so we simply see if the ELCR agrees.
518 * If it does, we assume it's valid.
520 if (mpc_default_type == 5) {
521 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
523 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
524 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
526 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
531 for (i = 0; i < 16; i++) {
532 switch (mpc_default_type) {
534 if (i == 0 || i == 13)
535 continue; /* IRQ0 & IRQ13 not connected */
539 continue; /* IRQ2 is never connected */
544 * If the ELCR indicates a level-sensitive interrupt, we
545 * copy that information over to the MP table in the
546 * irqflag field (level sensitive, active high polarity).
549 intsrc.mpc_irqflag = 13;
551 intsrc.mpc_irqflag = 0;
554 intsrc.mpc_srcbusirq = i;
555 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
556 MP_intsrc_info(&intsrc);
559 intsrc.mpc_irqtype = mp_ExtINT;
560 intsrc.mpc_srcbusirq = 0;
561 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
562 MP_intsrc_info(&intsrc);
565 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
567 struct mpc_config_processor processor;
568 struct mpc_config_bus bus;
569 struct mpc_config_ioapic ioapic;
570 struct mpc_config_lintsrc lintsrc;
571 int linttypes[2] = { mp_ExtINT, mp_NMI };
575 * local APIC has default address
577 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
580 * 2 CPUs, numbered 0 & 1.
582 processor.mpc_type = MP_PROCESSOR;
583 /* Either an integrated APIC or a discrete 82489DX. */
584 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
585 processor.mpc_cpuflag = CPU_ENABLED;
586 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
587 (boot_cpu_data.x86_model << 4) |
588 boot_cpu_data.x86_mask;
589 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
590 processor.mpc_reserved[0] = 0;
591 processor.mpc_reserved[1] = 0;
592 for (i = 0; i < 2; i++) {
593 processor.mpc_apicid = i;
594 MP_processor_info(&processor);
597 bus.mpc_type = MP_BUS;
599 switch (mpc_default_type) {
602 printk(KERN_ERR "Unknown standard configuration %d\n",
607 memcpy(bus.mpc_bustype, "ISA ", 6);
612 memcpy(bus.mpc_bustype, "EISA ", 6);
616 memcpy(bus.mpc_bustype, "MCA ", 6);
619 if (mpc_default_type > 4) {
621 memcpy(bus.mpc_bustype, "PCI ", 6);
625 ioapic.mpc_type = MP_IOAPIC;
626 ioapic.mpc_apicid = 2;
627 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
628 ioapic.mpc_flags = MPC_APIC_USABLE;
629 ioapic.mpc_apicaddr = 0xFEC00000;
630 MP_ioapic_info(&ioapic);
633 * We set up most of the low 16 IO-APIC pins according to MPS rules.
635 construct_default_ioirq_mptable(mpc_default_type);
637 lintsrc.mpc_type = MP_LINTSRC;
638 lintsrc.mpc_irqflag = 0; /* conforming */
639 lintsrc.mpc_srcbusid = 0;
640 lintsrc.mpc_srcbusirq = 0;
641 lintsrc.mpc_destapic = MP_APIC_ALL;
642 for (i = 0; i < 2; i++) {
643 lintsrc.mpc_irqtype = linttypes[i];
644 lintsrc.mpc_destapiclint = i;
645 MP_lintsrc_info(&lintsrc);
649 static struct intel_mp_floating *mpf_found;
652 * Scan the memory blocks for an SMP configuration block.
654 void __init get_smp_config (void)
656 struct intel_mp_floating *mpf = mpf_found;
659 * ACPI supports both logical (e.g. Hyper-Threading) and physical
660 * processors, where MPS only supports physical.
662 if (acpi_lapic && acpi_ioapic) {
663 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
667 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
669 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
670 if (mpf->mpf_feature2 & (1<<7)) {
671 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
674 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
679 * Now see if we need to read further.
681 if (mpf->mpf_feature1 != 0) {
683 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
684 construct_default_ISA_mptable(mpf->mpf_feature1);
686 } else if (mpf->mpf_physptr) {
689 * Read the physical hardware table. Anything here will
690 * override the defaults.
692 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
693 smp_found_config = 0;
694 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
695 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
699 * If there are no explicit MP IRQ entries, then we are
700 * broken. We set up most of the low 16 IO-APIC pins to
701 * ISA defaults and hope it will work.
703 if (!mp_irq_entries) {
704 struct mpc_config_bus bus;
706 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
708 bus.mpc_type = MP_BUS;
710 memcpy(bus.mpc_bustype, "ISA ", 6);
713 construct_default_ioirq_mptable(0);
719 printk(KERN_INFO "Processors: %d\n", num_processors);
721 * Only use the first configuration found.
725 static int __init smp_scan_config (unsigned long base, unsigned long length)
727 unsigned long *bp = phys_to_virt(base);
728 struct intel_mp_floating *mpf;
730 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
731 if (sizeof(*mpf) != 16)
732 printk("Error: MPF size\n");
735 mpf = (struct intel_mp_floating *)bp;
736 if ((*bp == SMP_MAGIC_IDENT) &&
737 (mpf->mpf_length == 1) &&
738 !mpf_checksum((unsigned char *)bp, 16) &&
739 ((mpf->mpf_specification == 1)
740 || (mpf->mpf_specification == 4)) ) {
742 smp_found_config = 1;
743 printk(KERN_INFO "found SMP MP-table at %08lx\n",
745 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
746 if (mpf->mpf_physptr) {
748 * We cannot access to MPC table to compute
749 * table size yet, as only few megabytes from
750 * the bottom is mapped now.
751 * PC-9800's MPC table places on the very last
752 * of physical memory; so that simply reserving
753 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
754 * in reserve_bootmem.
756 unsigned long size = PAGE_SIZE;
757 unsigned long end = max_low_pfn * PAGE_SIZE;
758 if (mpf->mpf_physptr + size > end)
759 size = end - mpf->mpf_physptr;
760 reserve_bootmem(mpf->mpf_physptr, size);
772 void __init find_smp_config (void)
774 unsigned int address;
777 * FIXME: Linux assumes you have 640K of base ram..
778 * this continues the error...
780 * 1) Scan the bottom 1K for a signature
781 * 2) Scan the top 1K of base RAM
782 * 3) Scan the 64K of bios
784 if (smp_scan_config(0x0,0x400) ||
785 smp_scan_config(639*0x400,0x400) ||
786 smp_scan_config(0xF0000,0x10000))
789 * If it is an SMP machine we should know now, unless the
790 * configuration is in an EISA/MCA bus machine with an
791 * extended bios data area.
793 * there is a real-mode segmented pointer pointing to the
794 * 4K EBDA area at 0x40E, calculate and scan it here.
796 * NOTE! There are Linux loaders that will corrupt the EBDA
797 * area, and as such this kind of SMP config may be less
798 * trustworthy, simply because the SMP table may have been
799 * stomped on during early boot. These loaders are buggy and
802 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
805 address = get_bios_ebda();
807 smp_scan_config(address, 0x400);
812 /* --------------------------------------------------------------------------
813 ACPI-based MP Configuration
814 -------------------------------------------------------------------------- */
818 void __init mp_register_lapic_address (
821 mp_lapic_addr = (unsigned long) address;
823 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
825 if (boot_cpu_physical_apicid == -1U)
826 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
828 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
832 void __devinit mp_register_lapic (
836 struct mpc_config_processor processor;
839 if (MAX_APICS - id <= 0) {
840 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
845 if (id == boot_cpu_physical_apicid)
848 processor.mpc_type = MP_PROCESSOR;
849 processor.mpc_apicid = id;
850 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
851 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
852 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
853 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
854 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
855 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
856 processor.mpc_reserved[0] = 0;
857 processor.mpc_reserved[1] = 0;
859 MP_processor_info(&processor);
862 #ifdef CONFIG_X86_IO_APIC
865 #define MP_MAX_IOAPIC_PIN 127
867 static struct mp_ioapic_routing {
871 u32 pin_programmed[4];
872 } mp_ioapic_routing[MAX_IO_APICS];
875 static int mp_find_ioapic (
880 /* Find the IOAPIC that manages this GSI. */
881 for (i = 0; i < nr_ioapics; i++) {
882 if ((gsi >= mp_ioapic_routing[i].gsi_base)
883 && (gsi <= mp_ioapic_routing[i].gsi_end))
887 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
893 void __init mp_register_ioapic (
901 if (nr_ioapics >= MAX_IO_APICS) {
902 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
903 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
904 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
907 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
908 " found in MADT table, skipping!\n");
914 mp_ioapics[idx].mpc_type = MP_IOAPIC;
915 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
916 mp_ioapics[idx].mpc_apicaddr = address;
918 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
919 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
920 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
921 tmpid = io_apic_get_unique_id(idx, id);
928 mp_ioapics[idx].mpc_apicid = tmpid;
929 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
932 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
933 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
935 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
936 mp_ioapic_routing[idx].gsi_base = gsi_base;
937 mp_ioapic_routing[idx].gsi_end = gsi_base +
938 io_apic_get_redir_entries(idx);
940 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
941 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
942 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
943 mp_ioapic_routing[idx].gsi_base,
944 mp_ioapic_routing[idx].gsi_end);
950 void __init mp_override_legacy_irq (
956 struct mpc_config_intsrc intsrc;
961 * Convert 'gsi' to 'ioapic.pin'.
963 ioapic = mp_find_ioapic(gsi);
966 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
969 * TBD: This check is for faulty timer entries, where the override
970 * erroneously sets the trigger to level, resulting in a HUGE
971 * increase of timer interrupts!
973 if ((bus_irq == 0) && (trigger == 3))
976 intsrc.mpc_type = MP_INTSRC;
977 intsrc.mpc_irqtype = mp_INT;
978 intsrc.mpc_irqflag = (trigger << 2) | polarity;
979 intsrc.mpc_srcbus = MP_ISA_BUS;
980 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
981 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
982 intsrc.mpc_dstirq = pin; /* INTIN# */
984 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
985 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
986 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
987 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
989 mp_irqs[mp_irq_entries] = intsrc;
990 if (++mp_irq_entries == MAX_IRQ_SOURCES)
991 panic("Max # of irq sources exceeded!\n");
996 void __init mp_config_acpi_legacy_irqs (void)
998 struct mpc_config_intsrc intsrc;
1003 * Fabricate the legacy ISA bus (bus #31).
1005 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1006 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1009 * Older generations of ES7000 have no legacy identity mappings
1011 if (es7000_plat == 1)
1015 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1017 ioapic = mp_find_ioapic(0);
1021 intsrc.mpc_type = MP_INTSRC;
1022 intsrc.mpc_irqflag = 0; /* Conforming */
1023 intsrc.mpc_srcbus = MP_ISA_BUS;
1024 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1027 * Use the default configuration for the IRQs 0-15. Unless
1028 * overriden by (MADT) interrupt source override entries.
1030 for (i = 0; i < 16; i++) {
1033 for (idx = 0; idx < mp_irq_entries; idx++) {
1034 struct mpc_config_intsrc *irq = mp_irqs + idx;
1036 /* Do we already have a mapping for this ISA IRQ? */
1037 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1040 /* Do we already have a mapping for this IOAPIC pin */
1041 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1042 (irq->mpc_dstirq == i))
1046 if (idx != mp_irq_entries) {
1047 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1048 continue; /* IRQ already used */
1051 intsrc.mpc_irqtype = mp_INT;
1052 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1053 intsrc.mpc_dstirq = i;
1055 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1056 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1057 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1058 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1061 mp_irqs[mp_irq_entries] = intsrc;
1062 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1063 panic("Max # of irq sources exceeded!\n");
1067 #define MAX_GSI_NUM 4096
1069 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1074 static int pci_irq = 16;
1076 * Mapping between Global System Interrups, which
1077 * represent all possible interrupts, and IRQs
1078 * assigned to actual devices.
1080 static int gsi_to_irq[MAX_GSI_NUM];
1082 /* Don't set up the ACPI SCI because it's already set up */
1083 if (acpi_fadt.sci_int == gsi)
1086 ioapic = mp_find_ioapic(gsi);
1088 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1092 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1094 if (ioapic_renumber_irq)
1095 gsi = ioapic_renumber_irq(ioapic, gsi);
1098 * Avoid pin reprogramming. PRTs typically include entries
1099 * with redundant pin->gsi mappings (but unique PCI devices);
1100 * we only program the IOAPIC on the first.
1102 bit = ioapic_pin % 32;
1103 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1105 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1106 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1110 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1111 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1112 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1113 return gsi_to_irq[gsi];
1116 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1118 if (triggering == ACPI_LEVEL_SENSITIVE) {
1120 * For PCI devices assign IRQs in order, avoiding gaps
1121 * due to unused I/O APIC pins.
1124 if (gsi < MAX_GSI_NUM) {
1128 * Don't assign IRQ used by ACPI SCI
1130 if (gsi == acpi_fadt.sci_int)
1132 gsi_to_irq[irq] = gsi;
1134 printk(KERN_ERR "GSI %u is too high\n", gsi);
1139 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1140 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1141 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1145 #endif /* CONFIG_X86_IO_APIC */
1146 #endif /* CONFIG_ACPI */