arch/mips/au1000/common/irq.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1000 interrupt routines.
   4  *
   5  * Copyright 2001 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29 #include <linux/errno.h>
  30 #include <linux/init.h>
  31 #include <linux/irq.h>
  32 #include <linux/kernel_stat.h>
  33 #include <linux/module.h>
  34 #include <linux/signal.h>
  35 #include <linux/sched.h>
  36 #include <linux/types.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/ioport.h>
  39 #include <linux/timex.h>
  40 #include <linux/slab.h>
  41 #include <linux/random.h>
  42 #include <linux/delay.h>
  43 #include <linux/bitops.h>
  44
  45 #include <asm/bootinfo.h>
  46 #include <asm/io.h>
  47 #include <asm/mipsregs.h>
  48 #include <asm/system.h>
  49 #include <asm/mach-au1x00/au1000.h>
  50 #ifdef CONFIG_MIPS_PB1000
  51 #include <asm/mach-pb1x00/pb1000.h>
  52 #endif
  53
  54 #undef DEBUG_IRQ
  55 #ifdef DEBUG_IRQ
  56 /* note: prints function name for you */
  57 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
  58 #else
  59 #define DPRINTK(fmt, args...)
  60 #endif
  61
  62 #define EXT_INTC0_REQ0 2 /* IP 2 */
  63 #define EXT_INTC0_REQ1 3 /* IP 3 */
  64 #define EXT_INTC1_REQ0 4 /* IP 4 */
  65 #define EXT_INTC1_REQ1 5 /* IP 5 */
  66 #define MIPS_TIMER_IP  7 /* IP 7 */
  67
  68 extern void mips_timer_interrupt(void);
  69
  70 void    (*board_init_irq)(void);
  71
  72 static DEFINE_SPINLOCK(irq_lock);
  73
  74
  75 inline void local_enable_irq(unsigned int irq_nr)
  76 {
  77         if (irq_nr > AU1000_LAST_INTC0_INT) {
  78                 au_writel(1<<(irq_nr-32), IC1_MASKSET);
  79                 au_writel(1<<(irq_nr-32), IC1_WAKESET);
  80         }
  81         else {
  82                 au_writel(1<<irq_nr, IC0_MASKSET);
  83                 au_writel(1<<irq_nr, IC0_WAKESET);
  84         }
  85         au_sync();
  86 }
  87
  88
  89 inline void local_disable_irq(unsigned int irq_nr)
  90 {
  91         if (irq_nr > AU1000_LAST_INTC0_INT) {
  92                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
  93                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
  94         }
  95         else {
  96                 au_writel(1<<irq_nr, IC0_MASKCLR);
  97                 au_writel(1<<irq_nr, IC0_WAKECLR);
  98         }
  99         au_sync();
 100 }
 101
 102
 103 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
 104 {
 105         if (irq_nr > AU1000_LAST_INTC0_INT) {
 106                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 107                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 108         }
 109         else {
 110                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 111                 au_writel(1<<irq_nr, IC0_MASKCLR);
 112         }
 113         au_sync();
 114 }
 115
 116
 117 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
 118 {
 119         if (irq_nr > AU1000_LAST_INTC0_INT) {
 120                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 121                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 122         }
 123         else {
 124                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 125                 au_writel(1<<irq_nr, IC0_MASKCLR);
 126         }
 127         au_sync();
 128 }
 129
 130
 131 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
 132 {
 133         /* This may assume that we don't get interrupts from
 134          * both edges at once, or if we do, that we don't care.
 135          */
 136         if (irq_nr > AU1000_LAST_INTC0_INT) {
 137                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 138                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 139                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 140         }
 141         else {
 142                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 143                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 144                 au_writel(1<<irq_nr, IC0_MASKCLR);
 145         }
 146         au_sync();
 147 }
 148
 149
 150 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
 151 {
 152
 153         local_disable_irq(irq_nr);
 154         au_sync();
 155 #if defined(CONFIG_MIPS_PB1000)
 156         if (irq_nr == AU1000_GPIO_15) {
 157                 au_writel(0x8000, PB1000_MDR); /* ack int */
 158                 au_sync();
 159         }
 160 #endif
 161         return;
 162 }
 163
 164
 165 static void end_irq(unsigned int irq_nr)
 166 {
 167         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 168                 local_enable_irq(irq_nr);
 169         }
 170 #if defined(CONFIG_MIPS_PB1000)
 171         if (irq_nr == AU1000_GPIO_15) {
 172                 au_writel(0x4000, PB1000_MDR); /* enable int */
 173                 au_sync();
 174         }
 175 #endif
 176 }
 177
 178 unsigned long save_local_and_disable(int controller)
 179 {
 180         int i;
 181         unsigned long flags, mask;
 182
 183         spin_lock_irqsave(&irq_lock, flags);
 184         if (controller) {
 185                 mask = au_readl(IC1_MASKSET);
 186                 for (i=32; i<64; i++) {
 187                         local_disable_irq(i);
 188                 }
 189         }
 190         else {
 191                 mask = au_readl(IC0_MASKSET);
 192                 for (i=0; i<32; i++) {
 193                         local_disable_irq(i);
 194                 }
 195         }
 196         spin_unlock_irqrestore(&irq_lock, flags);
 197
 198         return mask;
 199 }
 200
 201 void restore_local_and_enable(int controller, unsigned long mask)
 202 {
 203         int i;
 204         unsigned long flags, new_mask;
 205
 206         spin_lock_irqsave(&irq_lock, flags);
 207         for (i=0; i<32; i++) {
 208                 if (mask & (1<<i)) {
 209                         if (controller)
 210                                 local_enable_irq(i+32);
 211                         else
 212                                 local_enable_irq(i);
 213                 }
 214         }
 215         if (controller)
 216                 new_mask = au_readl(IC1_MASKSET);
 217         else
 218                 new_mask = au_readl(IC0_MASKSET);
 219
 220         spin_unlock_irqrestore(&irq_lock, flags);
 221 }
 222
 223
 224 static struct irq_chip rise_edge_irq_type = {
 225         .name = "Au1000 Rise Edge",
 226         .ack = mask_and_ack_rise_edge_irq,
 227         .mask = local_disable_irq,
 228         .mask_ack = mask_and_ack_rise_edge_irq,
 229         .unmask = local_enable_irq,
 230         .end = end_irq,
 231 };
 232
 233 static struct irq_chip fall_edge_irq_type = {
 234         .name = "Au1000 Fall Edge",
 235         .ack = mask_and_ack_fall_edge_irq,
 236         .mask = local_disable_irq,
 237         .mask_ack = mask_and_ack_fall_edge_irq,
 238         .unmask = local_enable_irq,
 239         .end = end_irq,
 240 };
 241
 242 static struct irq_chip either_edge_irq_type = {
 243         .name = "Au1000 Rise or Fall Edge",
 244         .ack = mask_and_ack_either_edge_irq,
 245         .mask = local_disable_irq,
 246         .mask_ack = mask_and_ack_either_edge_irq,
 247         .unmask = local_enable_irq,
 248         .end = end_irq,
 249 };
 250
 251 static struct irq_chip level_irq_type = {
 252         .name = "Au1000 Level",
 253         .ack = mask_and_ack_level_irq,
 254         .mask = local_disable_irq,
 255         .mask_ack = mask_and_ack_level_irq,
 256         .unmask = local_enable_irq,
 257         .end = end_irq,
 258 };
 259
 260 #ifdef CONFIG_PM
 261 void startup_match20_interrupt(irq_handler_t handler)
 262 {
 263         struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
 264
 265         static struct irqaction action;
 266         memset(&action, 0, sizeof(struct irqaction));
 267
 268         /* This is a big problem.... since we didn't use request_irq
 269          * when kernel/irq.c calls probe_irq_xxx this interrupt will
 270          * be probed for usage. This will end up disabling the device :(
 271          * Give it a bogus "action" pointer -- this will keep it from
 272          * getting auto-probed!
 273          *
 274          * By setting the status to match that of request_irq() we
 275          * can avoid it.  --cgray
 276         */
 277         action.dev_id = handler;
 278         action.flags = IRQF_DISABLED;
 279         cpus_clear(action.mask);
 280         action.name = "Au1xxx TOY";
 281         action.handler = handler;
 282         action.next = NULL;
 283
 284         desc->action = &action;
 285         desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
 286
 287         local_enable_irq(AU1000_TOY_MATCH2_INT);
 288 }
 289 #endif
 290
 291 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
 292 {
 293         if (irq_nr > AU1000_MAX_INTR) return;
 294         /* Config2[n], Config1[n], Config0[n] */
 295         if (irq_nr > AU1000_LAST_INTC0_INT) {
 296                 switch (type) {
 297                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 298                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 299                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 300                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 301                                 set_irq_chip(irq_nr, &rise_edge_irq_type);
 302                                 break;
 303                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 304                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 305                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 306                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 307                                 set_irq_chip(irq_nr, &fall_edge_irq_type);
 308                                 break;
 309                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 310                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 311                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 312                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 313                                 set_irq_chip(irq_nr, &either_edge_irq_type);
 314                                 break;
 315                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 316                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 317                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 318                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 319                                 set_irq_chip(irq_nr, &level_irq_type);
 320                                 break;
 321                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 322                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 323                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 324                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 325                                 set_irq_chip(irq_nr, &level_irq_type);
 326                                 break;
 327                         case INTC_INT_DISABLED: /* 0:0:0 */
 328                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 329                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 330                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 331                                 break;
 332                         default: /* disable the interrupt */
 333                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 334                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 335                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 336                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 337                                 return;
 338                 }
 339                 if (int_req) /* assign to interrupt request 1 */
 340                         au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
 341                 else         /* assign to interrupt request 0 */
 342                         au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
 343                 au_writel(1<<(irq_nr-32), IC1_SRCSET);
 344                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 345                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
 346         }
 347         else {
 348                 switch (type) {
 349                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 350                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 351                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 352                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 353                                 set_irq_chip(irq_nr, &rise_edge_irq_type);
 354                                 break;
 355                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 356                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 357                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 358                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 359                                 set_irq_chip(irq_nr, &fall_edge_irq_type);
 360                                 break;
 361                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 362                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 363                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 364                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 365                                 set_irq_chip(irq_nr, &either_edge_irq_type);
 366                                 break;
 367                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 368                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 369                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 370                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 371                                 set_irq_chip(irq_nr, &level_irq_type);
 372                                 break;
 373                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 374                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 375                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 376                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 377                                 set_irq_chip(irq_nr, &level_irq_type);
 378                                 break;
 379                         case INTC_INT_DISABLED: /* 0:0:0 */
 380                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 381                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 382                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 383                                 break;
 384                         default: /* disable the interrupt */
 385                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 386                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 387                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 388                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 389                                 return;
 390                 }
 391                 if (int_req) /* assign to interrupt request 1 */
 392                         au_writel(1<<irq_nr, IC0_ASSIGNCLR);
 393                 else         /* assign to interrupt request 0 */
 394                         au_writel(1<<irq_nr, IC0_ASSIGNSET);
 395                 au_writel(1<<irq_nr, IC0_SRCSET);
 396                 au_writel(1<<irq_nr, IC0_MASKCLR);
 397                 au_writel(1<<irq_nr, IC0_WAKECLR);
 398         }
 399         au_sync();
 400 }
 401
 402
 403 void __init arch_init_irq(void)
 404 {
 405         int i;
 406         unsigned long cp0_status;
 407         au1xxx_irq_map_t *imp;
 408         extern au1xxx_irq_map_t au1xxx_irq_map[];
 409         extern au1xxx_irq_map_t au1xxx_ic0_map[];
 410         extern int au1xxx_nr_irqs;
 411         extern int au1xxx_ic0_nr_irqs;
 412
 413         cp0_status = read_c0_status();
 414
 415         /* Initialize interrupt controllers to a safe state.
 416         */
 417         au_writel(0xffffffff, IC0_CFG0CLR);
 418         au_writel(0xffffffff, IC0_CFG1CLR);
 419         au_writel(0xffffffff, IC0_CFG2CLR);
 420         au_writel(0xffffffff, IC0_MASKCLR);
 421         au_writel(0xffffffff, IC0_ASSIGNSET);
 422         au_writel(0xffffffff, IC0_WAKECLR);
 423         au_writel(0xffffffff, IC0_SRCSET);
 424         au_writel(0xffffffff, IC0_FALLINGCLR);
 425         au_writel(0xffffffff, IC0_RISINGCLR);
 426         au_writel(0x00000000, IC0_TESTBIT);
 427
 428         au_writel(0xffffffff, IC1_CFG0CLR);
 429         au_writel(0xffffffff, IC1_CFG1CLR);
 430         au_writel(0xffffffff, IC1_CFG2CLR);
 431         au_writel(0xffffffff, IC1_MASKCLR);
 432         au_writel(0xffffffff, IC1_ASSIGNSET);
 433         au_writel(0xffffffff, IC1_WAKECLR);
 434         au_writel(0xffffffff, IC1_SRCSET);
 435         au_writel(0xffffffff, IC1_FALLINGCLR);
 436         au_writel(0xffffffff, IC1_RISINGCLR);
 437         au_writel(0x00000000, IC1_TESTBIT);
 438
 439         /* Initialize IC0, which is fixed per processor.
 440         */
 441         imp = au1xxx_ic0_map;
 442         for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
 443                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 444                 imp++;
 445         }
 446
 447         /* Now set up the irq mapping for the board.
 448         */
 449         imp = au1xxx_irq_map;
 450         for (i=0; i<au1xxx_nr_irqs; i++) {
 451                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 452                 imp++;
 453         }
 454
 455         set_c0_status(ALLINTS);
 456
 457         /* Board specific IRQ initialization.
 458         */
 459         if (board_init_irq)
 460                 (*board_init_irq)();
 461 }
 462
 463
 464 /*
 465  * Interrupts are nested. Even if an interrupt handler is registered
 466  * as "fast", we might get another interrupt before we return from
 467  * intcX_reqX_irqdispatch().
 468  */
 469
 470 static void intc0_req0_irqdispatch(void)
 471 {
 472         int irq = 0;
 473         static unsigned long intc0_req0 = 0;
 474
 475         intc0_req0 |= au_readl(IC0_REQ0INT);
 476
 477         if (!intc0_req0)
 478                 return;
 479 #ifdef AU1000_USB_DEV_REQ_INT
 480         /*
 481          * Because of the tight timing of SETUP token to reply
 482          * transactions, the USB devices-side packet complete
 483          * interrupt needs the highest priority.
 484          */
 485         if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
 486                 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
 487                 do_IRQ(AU1000_USB_DEV_REQ_INT);
 488                 return;
 489         }
 490 #endif
 491         irq = au_ffs(intc0_req0) - 1;
 492         intc0_req0 &= ~(1<<irq);
 493         do_IRQ(irq);
 494 }
 495
 496
 497 static void intc0_req1_irqdispatch(void)
 498 {
 499         int irq = 0;
 500         static unsigned long intc0_req1 = 0;
 501
 502         intc0_req1 |= au_readl(IC0_REQ1INT);
 503
 504         if (!intc0_req1)
 505                 return;
 506
 507         irq = au_ffs(intc0_req1) - 1;
 508         intc0_req1 &= ~(1<<irq);
 509         do_IRQ(irq);
 510 }
 511
 512
 513 /*
 514  * Interrupt Controller 1:
 515  * interrupts 32 - 63
 516  */
 517 static void intc1_req0_irqdispatch(void)
 518 {
 519         int irq = 0;
 520         static unsigned long intc1_req0 = 0;
 521
 522         intc1_req0 |= au_readl(IC1_REQ0INT);
 523
 524         if (!intc1_req0)
 525                 return;
 526
 527         irq = au_ffs(intc1_req0) - 1;
 528         intc1_req0 &= ~(1<<irq);
 529         irq += 32;
 530         do_IRQ(irq);
 531 }
 532
 533
 534 static void intc1_req1_irqdispatch(void)
 535 {
 536         int irq = 0;
 537         static unsigned long intc1_req1 = 0;
 538
 539         intc1_req1 |= au_readl(IC1_REQ1INT);
 540
 541         if (!intc1_req1)
 542                 return;
 543
 544         irq = au_ffs(intc1_req1) - 1;
 545         intc1_req1 &= ~(1<<irq);
 546         irq += 32;
 547         do_IRQ(irq);
 548 }
 549
 550 #ifdef CONFIG_PM
 551
 552 /* Save/restore the interrupt controller state.
 553  * Called from the save/restore core registers as part of the
 554  * au_sleep function in power.c.....maybe I should just pm_register()
 555  * them instead?
 556  */
 557 static unsigned int     sleep_intctl_config0[2];
 558 static unsigned int     sleep_intctl_config1[2];
 559 static unsigned int     sleep_intctl_config2[2];
 560 static unsigned int     sleep_intctl_src[2];
 561 static unsigned int     sleep_intctl_assign[2];
 562 static unsigned int     sleep_intctl_wake[2];
 563 static unsigned int     sleep_intctl_mask[2];
 564
 565 void
 566 save_au1xxx_intctl(void)
 567 {
 568         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 569         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
 570         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
 571         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
 572         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
 573         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
 574         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
 575
 576         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
 577         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
 578         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
 579         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
 580         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
 581         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
 582         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 583 }
 584
 585 /* For most restore operations, we clear the entire register and
 586  * then set the bits we found during the save.
 587  */
 588 void
 589 restore_au1xxx_intctl(void)
 590 {
 591         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 592
 593         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
 594         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
 595         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
 596         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
 597         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
 598         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
 599         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
 600         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
 601         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
 602         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
 603         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
 604         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
 605         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
 606         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
 607         au_writel(0x00000000, IC0_TESTBIT); au_sync();
 608
 609         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
 610
 611         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
 612         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
 613         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
 614         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
 615         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
 616         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
 617         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
 618         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
 619         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
 620         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
 621         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
 622         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
 623         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
 624         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
 625         au_writel(0x00000000, IC1_TESTBIT); au_sync();
 626
 627         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
 628
 629         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
 630 }
 631 #endif /* CONFIG_PM */
 632
 633 asmlinkage void plat_irq_dispatch(void)
 634 {
 635         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 636
 637         if (pending & CAUSEF_IP7)
 638                 mips_timer_interrupt();
 639         else if (pending & CAUSEF_IP2)
 640                 intc0_req0_irqdispatch();
 641         else if (pending & CAUSEF_IP3)
 642                 intc0_req1_irqdispatch();
 643         else if (pending & CAUSEF_IP4)
 644                 intc1_req0_irqdispatch();
 645         else if (pending  & CAUSEF_IP5)
 646                 intc1_req1_irqdispatch();
 647         else
 648                 spurious_interrupt();
 649 }