2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * arch/mips/ddb5xxx/ddb5477/irq.c
6 * The irq setup and misc routines for DDB5476.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/types.h>
17 #include <linux/ptrace.h>
19 #include <asm/i8259.h>
20 #include <asm/system.h>
21 #include <asm/mipsregs.h>
22 #include <asm/debug.h>
23 #include <asm/addrspace.h>
24 #include <asm/bootinfo.h>
26 #include <asm/ddb5xxx/ddb5xxx.h>
32 * 0-7: 8 CPU interrupts
33 * 0 - software interrupt 0
34 * 1 - software interrupt 1
35 * 2 - most Vrc5477 interrupts are routed to this pin
36 * 3 - (optional) some other interrupts routed to this pin for debugg
40 * 7 - cpu timer (used by default)
42 * 8-39: 32 Vrc5477 interrupt sources
43 * (refer to the Vrc5477 manual)
46 #define PCI0 DDB_INTPPES0
47 #define PCI1 DDB_INTPPES1
53 #define EDGE_TRIGGER 0
62 set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
67 reg_value = ddb_in32(pci);
68 reg_bitmask = 0x3 << (intn * 2);
70 reg_value &= ~reg_bitmask;
71 reg_value |= (active | trigger) << (intn * 2);
72 ddb_out32(pci, reg_value);
75 extern void vrc5477_irq_init(u32 base);
76 extern void mips_cpu_irq_init(u32 base);
77 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
78 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
80 void __init arch_init_irq(void)
82 /* by default, we disable all interrupts and route all vrc5477
83 * interrupts to pin 0 (irq 2) */
84 ddb_out32(DDB_INTCTRL0, 0);
85 ddb_out32(DDB_INTCTRL1, 0);
86 ddb_out32(DDB_INTCTRL2, 0);
87 ddb_out32(DDB_INTCTRL3, 0);
89 clear_c0_status(0xff00);
90 set_c0_status(0x0400);
92 /* setup PCI interrupt attributes */
93 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
94 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
95 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
96 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
98 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
99 set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
100 set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
102 set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
103 set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
104 set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
105 set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
106 set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
109 * for debugging purpose, we enable several error interrupts
110 * and route them to pin 1. (IP3)
112 /* cpu parity check - 0 */
113 ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
114 /* cpu no-target decode - 1 */
115 ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
116 /* local bus read time-out - 7 */
117 ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
119 ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
120 /* PCI internal error - 15 */
121 ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
122 /* IOPCI SERR# - 30 */
123 ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
124 /* IOPCI internal error - 31 */
125 ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
127 /* init all controllers */
129 mips_cpu_irq_init(CPU_IRQ_BASE);
130 vrc5477_irq_init(VRC5477_IRQ_BASE);
133 /* setup cascade interrupts */
134 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
135 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
138 u8 i8259_interrupt_ack(void)
143 /* Set window 0 for interrupt acknowledge */
144 reg = ddb_in32(DDB_PCIINIT10);
146 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
147 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
148 ddb_out32(DDB_PCIINIT10, reg);
150 /* i8259.c set the base vector to be 0x0 */
151 return irq + I8259_IRQ_BASE;
154 * the first level int-handler will jump here if it is a vrc5477 irq
156 #define NUM_5477_IRQS 32
158 vrc5477_irq_dispatch(struct pt_regs *regs)
164 db_assert(ddb_in32(DDB_INT2STAT) == 0);
165 db_assert(ddb_in32(DDB_INT3STAT) == 0);
166 db_assert(ddb_in32(DDB_INT4STAT) == 0);
167 db_assert(ddb_in32(DDB_NMISTAT) == 0);
169 if (ddb_in32(DDB_INT1STAT) != 0) {
170 #if defined(CONFIG_RUNTIME_DEBUG)
171 vrc5477_show_int_regs();
173 panic("error interrupt has happened.");
176 intStatus = ddb_in32(DDB_INT0STAT);
178 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
179 /* check for i8259 interrupts */
180 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
181 int i8259_irq = i8259_interrupt_ack();
182 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
187 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
188 /* do we need to "and" with the int mask? */
189 if (intStatus & bitmask) {
190 do_IRQ(VRC5477_IRQ_BASE + i, regs);
196 #define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
198 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
200 unsigned int pending = read_c0_cause() & read_c0_status();
202 if (pending & STATUSF_IP7)
203 do_IRQ(CPU_IRQ_BASE + 7, regs);
204 else if (pending & VR5477INTS)
205 vrc5477_irq_dispatch(regs);
206 else if (pending & STATUSF_IP0)
207 do_IRQ(CPU_IRQ_BASE, regs);
208 else if (pending & STATUSF_IP1)
209 do_IRQ(CPU_IRQ_BASE + 1, regs);
211 spurious_interrupt(regs);