]> pilppa.org Git - linux-2.6-omap-h63xx.git/blob - arch/mips/include/asm/mipsregs.h
Merge branches 'irq/genirq', 'irq/sparseirq' and 'irq/urgent' into irq/core
[linux-2.6-omap-h63xx.git] / arch / mips / include / asm / mipsregs.h
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7  * Copyright (C) 2000 Silicon Graphics, Inc.
8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
12  */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18 #include <asm/war.h>
19
20 /*
21  * The following macros are especially useful for __asm__
22  * inline assembler.
23  */
24 #ifndef __STR
25 #define __STR(x) #x
26 #endif
27 #ifndef STR
28 #define STR(x) __STR(x)
29 #endif
30
31 /*
32  *  Configure language
33  */
34 #ifdef __ASSEMBLY__
35 #define _ULCAST_
36 #else
37 #define _ULCAST_ (unsigned long)
38 #endif
39
40 /*
41  * Coprocessor 0 register names
42  */
43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6
51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13
58 #define CP0_EPC $14
59 #define CP0_PRID $15
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76
77 /*
78  * R4640/R4650 cp0 register names.  These registers are listed
79  * here only for completeness; without MMU these CPUs are not useable
80  * by Linux.  A future ELKS port might take make Linux run on them
81  * though ...
82  */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90
91 /*
92  * Coprocessor 0 Set 1 register names
93  */
94 #define CP0_S1_DERRADDR0  $26
95 #define CP0_S1_DERRADDR1  $27
96 #define CP0_S1_INTCONTROL $20
97
98 /*
99  * Coprocessor 0 Set 2 register names
100  */
101 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
102
103 /*
104  * Coprocessor 0 Set 3 register names
105  */
106 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
107
108 /*
109  *  TX39 Series
110  */
111 #define CP0_TX39_CACHE  $7
112
113 /*
114  * Coprocessor 1 (FPU) register names
115  */
116 #define CP1_REVISION   $0
117 #define CP1_STATUS     $31
118
119 /*
120  * FPU Status Register Values
121  */
122 /*
123  * Status Register Values
124  */
125
126 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
127 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
128 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
129 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
130 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
131 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
132 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
133 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
134 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
135 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
136
137 /*
138  * X the exception cause indicator
139  * E the exception enable
140  * S the sticky/flag bit
141 */
142 #define FPU_CSR_ALL_X   0x0003f000
143 #define FPU_CSR_UNI_X   0x00020000
144 #define FPU_CSR_INV_X   0x00010000
145 #define FPU_CSR_DIV_X   0x00008000
146 #define FPU_CSR_OVF_X   0x00004000
147 #define FPU_CSR_UDF_X   0x00002000
148 #define FPU_CSR_INE_X   0x00001000
149
150 #define FPU_CSR_ALL_E   0x00000f80
151 #define FPU_CSR_INV_E   0x00000800
152 #define FPU_CSR_DIV_E   0x00000400
153 #define FPU_CSR_OVF_E   0x00000200
154 #define FPU_CSR_UDF_E   0x00000100
155 #define FPU_CSR_INE_E   0x00000080
156
157 #define FPU_CSR_ALL_S   0x0000007c
158 #define FPU_CSR_INV_S   0x00000040
159 #define FPU_CSR_DIV_S   0x00000020
160 #define FPU_CSR_OVF_S   0x00000010
161 #define FPU_CSR_UDF_S   0x00000008
162 #define FPU_CSR_INE_S   0x00000004
163
164 /* rounding mode */
165 #define FPU_CSR_RN      0x0     /* nearest */
166 #define FPU_CSR_RZ      0x1     /* towards zero */
167 #define FPU_CSR_RU      0x2     /* towards +Infinity */
168 #define FPU_CSR_RD      0x3     /* towards -Infinity */
169
170
171 /*
172  * Values for PageMask register
173  */
174 #ifdef CONFIG_CPU_VR41XX
175
176 /* Why doesn't stupidity hurt ... */
177
178 #define PM_1K           0x00000000
179 #define PM_4K           0x00001800
180 #define PM_16K          0x00007800
181 #define PM_64K          0x0001f800
182 #define PM_256K         0x0007f800
183
184 #else
185
186 #define PM_4K           0x00000000
187 #define PM_16K          0x00006000
188 #define PM_64K          0x0001e000
189 #define PM_256K         0x0007e000
190 #define PM_1M           0x001fe000
191 #define PM_4M           0x007fe000
192 #define PM_16M          0x01ffe000
193 #define PM_64M          0x07ffe000
194 #define PM_256M         0x1fffe000
195 #define PM_1G           0x7fffe000
196
197 #endif
198
199 /*
200  * Default page size for a given kernel configuration
201  */
202 #ifdef CONFIG_PAGE_SIZE_4KB
203 #define PM_DEFAULT_MASK PM_4K
204 #elif defined(CONFIG_PAGE_SIZE_16KB)
205 #define PM_DEFAULT_MASK PM_16K
206 #elif defined(CONFIG_PAGE_SIZE_64KB)
207 #define PM_DEFAULT_MASK PM_64K
208 #else
209 #error Bad page size configuration!
210 #endif
211
212
213 /*
214  * Values used for computation of new tlb entries
215  */
216 #define PL_4K           12
217 #define PL_16K          14
218 #define PL_64K          16
219 #define PL_256K         18
220 #define PL_1M           20
221 #define PL_4M           22
222 #define PL_16M          24
223 #define PL_64M          26
224 #define PL_256M         28
225
226 /*
227  * R4x00 interrupt enable / cause bits
228  */
229 #define IE_SW0          (_ULCAST_(1) <<  8)
230 #define IE_SW1          (_ULCAST_(1) <<  9)
231 #define IE_IRQ0         (_ULCAST_(1) << 10)
232 #define IE_IRQ1         (_ULCAST_(1) << 11)
233 #define IE_IRQ2         (_ULCAST_(1) << 12)
234 #define IE_IRQ3         (_ULCAST_(1) << 13)
235 #define IE_IRQ4         (_ULCAST_(1) << 14)
236 #define IE_IRQ5         (_ULCAST_(1) << 15)
237
238 /*
239  * R4x00 interrupt cause bits
240  */
241 #define C_SW0           (_ULCAST_(1) <<  8)
242 #define C_SW1           (_ULCAST_(1) <<  9)
243 #define C_IRQ0          (_ULCAST_(1) << 10)
244 #define C_IRQ1          (_ULCAST_(1) << 11)
245 #define C_IRQ2          (_ULCAST_(1) << 12)
246 #define C_IRQ3          (_ULCAST_(1) << 13)
247 #define C_IRQ4          (_ULCAST_(1) << 14)
248 #define C_IRQ5          (_ULCAST_(1) << 15)
249
250 /*
251  * Bitfields in the R4xx0 cp0 status register
252  */
253 #define ST0_IE                  0x00000001
254 #define ST0_EXL                 0x00000002
255 #define ST0_ERL                 0x00000004
256 #define ST0_KSU                 0x00000018
257 #  define KSU_USER              0x00000010
258 #  define KSU_SUPERVISOR        0x00000008
259 #  define KSU_KERNEL            0x00000000
260 #define ST0_UX                  0x00000020
261 #define ST0_SX                  0x00000040
262 #define ST0_KX                  0x00000080
263 #define ST0_DE                  0x00010000
264 #define ST0_CE                  0x00020000
265
266 /*
267  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
268  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
269  * processors.
270  */
271 #define ST0_CO                  0x08000000
272
273 /*
274  * Bitfields in the R[23]000 cp0 status register.
275  */
276 #define ST0_IEC                 0x00000001
277 #define ST0_KUC                 0x00000002
278 #define ST0_IEP                 0x00000004
279 #define ST0_KUP                 0x00000008
280 #define ST0_IEO                 0x00000010
281 #define ST0_KUO                 0x00000020
282 /* bits 6 & 7 are reserved on R[23]000 */
283 #define ST0_ISC                 0x00010000
284 #define ST0_SWC                 0x00020000
285 #define ST0_CM                  0x00080000
286
287 /*
288  * Bits specific to the R4640/R4650
289  */
290 #define ST0_UM                  (_ULCAST_(1) <<  4)
291 #define ST0_IL                  (_ULCAST_(1) << 23)
292 #define ST0_DL                  (_ULCAST_(1) << 24)
293
294 /*
295  * Enable the MIPS MDMX and DSP ASEs
296  */
297 #define ST0_MX                  0x01000000
298
299 /*
300  * Bitfields in the TX39 family CP0 Configuration Register 3
301  */
302 #define TX39_CONF_ICS_SHIFT     19
303 #define TX39_CONF_ICS_MASK      0x00380000
304 #define TX39_CONF_ICS_1KB       0x00000000
305 #define TX39_CONF_ICS_2KB       0x00080000
306 #define TX39_CONF_ICS_4KB       0x00100000
307 #define TX39_CONF_ICS_8KB       0x00180000
308 #define TX39_CONF_ICS_16KB      0x00200000
309
310 #define TX39_CONF_DCS_SHIFT     16
311 #define TX39_CONF_DCS_MASK      0x00070000
312 #define TX39_CONF_DCS_1KB       0x00000000
313 #define TX39_CONF_DCS_2KB       0x00010000
314 #define TX39_CONF_DCS_4KB       0x00020000
315 #define TX39_CONF_DCS_8KB       0x00030000
316 #define TX39_CONF_DCS_16KB      0x00040000
317
318 #define TX39_CONF_CWFON         0x00004000
319 #define TX39_CONF_WBON          0x00002000
320 #define TX39_CONF_RF_SHIFT      10
321 #define TX39_CONF_RF_MASK       0x00000c00
322 #define TX39_CONF_DOZE          0x00000200
323 #define TX39_CONF_HALT          0x00000100
324 #define TX39_CONF_LOCK          0x00000080
325 #define TX39_CONF_ICE           0x00000020
326 #define TX39_CONF_DCE           0x00000010
327 #define TX39_CONF_IRSIZE_SHIFT  2
328 #define TX39_CONF_IRSIZE_MASK   0x0000000c
329 #define TX39_CONF_DRSIZE_SHIFT  0
330 #define TX39_CONF_DRSIZE_MASK   0x00000003
331
332 /*
333  * Status register bits available in all MIPS CPUs.
334  */
335 #define ST0_IM                  0x0000ff00
336 #define  STATUSB_IP0            8
337 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
338 #define  STATUSB_IP1            9
339 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
340 #define  STATUSB_IP2            10
341 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
342 #define  STATUSB_IP3            11
343 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
344 #define  STATUSB_IP4            12
345 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
346 #define  STATUSB_IP5            13
347 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
348 #define  STATUSB_IP6            14
349 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
350 #define  STATUSB_IP7            15
351 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
352 #define  STATUSB_IP8            0
353 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
354 #define  STATUSB_IP9            1
355 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
356 #define  STATUSB_IP10           2
357 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
358 #define  STATUSB_IP11           3
359 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
360 #define  STATUSB_IP12           4
361 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
362 #define  STATUSB_IP13           5
363 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
364 #define  STATUSB_IP14           6
365 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
366 #define  STATUSB_IP15           7
367 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
368 #define ST0_CH                  0x00040000
369 #define ST0_SR                  0x00100000
370 #define ST0_TS                  0x00200000
371 #define ST0_BEV                 0x00400000
372 #define ST0_RE                  0x02000000
373 #define ST0_FR                  0x04000000
374 #define ST0_CU                  0xf0000000
375 #define ST0_CU0                 0x10000000
376 #define ST0_CU1                 0x20000000
377 #define ST0_CU2                 0x40000000
378 #define ST0_CU3                 0x80000000
379 #define ST0_XX                  0x80000000      /* MIPS IV naming */
380
381 /*
382  * Bitfields and bit numbers in the coprocessor 0 cause register.
383  *
384  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
385  */
386 #define  CAUSEB_EXCCODE         2
387 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
388 #define  CAUSEB_IP              8
389 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
390 #define  CAUSEB_IP0             8
391 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
392 #define  CAUSEB_IP1             9
393 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
394 #define  CAUSEB_IP2             10
395 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
396 #define  CAUSEB_IP3             11
397 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
398 #define  CAUSEB_IP4             12
399 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
400 #define  CAUSEB_IP5             13
401 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
402 #define  CAUSEB_IP6             14
403 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
404 #define  CAUSEB_IP7             15
405 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
406 #define  CAUSEB_IV              23
407 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
408 #define  CAUSEB_CE              28
409 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
410 #define  CAUSEB_BD              31
411 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
412
413 /*
414  * Bits in the coprocessor 0 config register.
415  */
416 /* Generic bits.  */
417 #define CONF_CM_CACHABLE_NO_WA          0
418 #define CONF_CM_CACHABLE_WA             1
419 #define CONF_CM_UNCACHED                2
420 #define CONF_CM_CACHABLE_NONCOHERENT    3
421 #define CONF_CM_CACHABLE_CE             4
422 #define CONF_CM_CACHABLE_COW            5
423 #define CONF_CM_CACHABLE_CUW            6
424 #define CONF_CM_CACHABLE_ACCELERATED    7
425 #define CONF_CM_CMASK                   7
426 #define CONF_BE                 (_ULCAST_(1) << 15)
427
428 /* Bits common to various processors.  */
429 #define CONF_CU                 (_ULCAST_(1) <<  3)
430 #define CONF_DB                 (_ULCAST_(1) <<  4)
431 #define CONF_IB                 (_ULCAST_(1) <<  5)
432 #define CONF_DC                 (_ULCAST_(7) <<  6)
433 #define CONF_IC                 (_ULCAST_(7) <<  9)
434 #define CONF_EB                 (_ULCAST_(1) << 13)
435 #define CONF_EM                 (_ULCAST_(1) << 14)
436 #define CONF_SM                 (_ULCAST_(1) << 16)
437 #define CONF_SC                 (_ULCAST_(1) << 17)
438 #define CONF_EW                 (_ULCAST_(3) << 18)
439 #define CONF_EP                 (_ULCAST_(15)<< 24)
440 #define CONF_EC                 (_ULCAST_(7) << 28)
441 #define CONF_CM                 (_ULCAST_(1) << 31)
442
443 /* Bits specific to the R4xx0.  */
444 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
445 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
446 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
447
448 /* Bits specific to the R5000.  */
449 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
450 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
451
452 /* Bits specific to the RM7000.  */
453 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
454 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
455 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
456 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
457 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
458 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
459
460 /* Bits specific to the R10000.  */
461 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
462 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
463 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
464 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
465 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
466 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
467 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
468 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
469 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
470 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
471 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
472
473 /* Bits specific to the VR41xx.  */
474 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
475 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
476 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
477 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
478 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
479
480 /* Bits specific to the R30xx.  */
481 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
482 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
483 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
484 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
485 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
486 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
487 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
488 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
489 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
490
491 /* Bits specific to the TX49.  */
492 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
493 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
494 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
495 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
496
497 /* Bits specific to the MIPS32/64 PRA.  */
498 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
499 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
500 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
501 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
502
503 /*
504  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
505  */
506 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
507 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
508 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
509 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
510 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
511 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
512 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
513 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
514 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
515 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
516 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
517 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
518 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
519 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
520
521 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
522 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
523 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
524 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
525 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
526 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
527 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
528 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
529
530 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
531 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
532 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
533 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
534 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
535 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
536 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
537 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
538 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
539
540 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
541
542 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
543
544
545 /*
546  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
547  */
548 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
549 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
550 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
551 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
552 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
553 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
554 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
555
556 #ifndef __ASSEMBLY__
557
558 /*
559  * Functions to access the R10000 performance counters.  These are basically
560  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
561  * performance counter number encoded into bits 1 ... 5 of the instruction.
562  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
563  * disassembler these will look like an access to sel 0 or 1.
564  */
565 #define read_r10k_perf_cntr(counter)                            \
566 ({                                                              \
567         unsigned int __res;                                     \
568         __asm__ __volatile__(                                   \
569         "mfpc\t%0, %1"                                          \
570         : "=r" (__res)                                          \
571         : "i" (counter));                                       \
572                                                                 \
573         __res;                                                  \
574 })
575
576 #define write_r10k_perf_cntr(counter,val)                       \
577 do {                                                            \
578         __asm__ __volatile__(                                   \
579         "mtpc\t%0, %1"                                          \
580         :                                                       \
581         : "r" (val), "i" (counter));                            \
582 } while (0)
583
584 #define read_r10k_perf_event(counter)                           \
585 ({                                                              \
586         unsigned int __res;                                     \
587         __asm__ __volatile__(                                   \
588         "mfps\t%0, %1"                                          \
589         : "=r" (__res)                                          \
590         : "i" (counter));                                       \
591                                                                 \
592         __res;                                                  \
593 })
594
595 #define write_r10k_perf_cntl(counter,val)                       \
596 do {                                                            \
597         __asm__ __volatile__(                                   \
598         "mtps\t%0, %1"                                          \
599         :                                                       \
600         : "r" (val), "i" (counter));                            \
601 } while (0)
602
603
604 /*
605  * Macros to access the system control coprocessor
606  */
607
608 #define __read_32bit_c0_register(source, sel)                           \
609 ({ int __res;                                                           \
610         if (sel == 0)                                                   \
611                 __asm__ __volatile__(                                   \
612                         "mfc0\t%0, " #source "\n\t"                     \
613                         : "=r" (__res));                                \
614         else                                                            \
615                 __asm__ __volatile__(                                   \
616                         ".set\tmips32\n\t"                              \
617                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
618                         ".set\tmips0\n\t"                               \
619                         : "=r" (__res));                                \
620         __res;                                                          \
621 })
622
623 #define __read_64bit_c0_register(source, sel)                           \
624 ({ unsigned long long __res;                                            \
625         if (sizeof(unsigned long) == 4)                                 \
626                 __res = __read_64bit_c0_split(source, sel);             \
627         else if (sel == 0)                                              \
628                 __asm__ __volatile__(                                   \
629                         ".set\tmips3\n\t"                               \
630                         "dmfc0\t%0, " #source "\n\t"                    \
631                         ".set\tmips0"                                   \
632                         : "=r" (__res));                                \
633         else                                                            \
634                 __asm__ __volatile__(                                   \
635                         ".set\tmips64\n\t"                              \
636                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
637                         ".set\tmips0"                                   \
638                         : "=r" (__res));                                \
639         __res;                                                          \
640 })
641
642 #define __write_32bit_c0_register(register, sel, value)                 \
643 do {                                                                    \
644         if (sel == 0)                                                   \
645                 __asm__ __volatile__(                                   \
646                         "mtc0\t%z0, " #register "\n\t"                  \
647                         : : "Jr" ((unsigned int)(value)));              \
648         else                                                            \
649                 __asm__ __volatile__(                                   \
650                         ".set\tmips32\n\t"                              \
651                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
652                         ".set\tmips0"                                   \
653                         : : "Jr" ((unsigned int)(value)));              \
654 } while (0)
655
656 #define __write_64bit_c0_register(register, sel, value)                 \
657 do {                                                                    \
658         if (sizeof(unsigned long) == 4)                                 \
659                 __write_64bit_c0_split(register, sel, value);           \
660         else if (sel == 0)                                              \
661                 __asm__ __volatile__(                                   \
662                         ".set\tmips3\n\t"                               \
663                         "dmtc0\t%z0, " #register "\n\t"                 \
664                         ".set\tmips0"                                   \
665                         : : "Jr" (value));                              \
666         else                                                            \
667                 __asm__ __volatile__(                                   \
668                         ".set\tmips64\n\t"                              \
669                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
670                         ".set\tmips0"                                   \
671                         : : "Jr" (value));                              \
672 } while (0)
673
674 #define __read_ulong_c0_register(reg, sel)                              \
675         ((sizeof(unsigned long) == 4) ?                                 \
676         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
677         (unsigned long) __read_64bit_c0_register(reg, sel))
678
679 #define __write_ulong_c0_register(reg, sel, val)                        \
680 do {                                                                    \
681         if (sizeof(unsigned long) == 4)                                 \
682                 __write_32bit_c0_register(reg, sel, val);               \
683         else                                                            \
684                 __write_64bit_c0_register(reg, sel, val);               \
685 } while (0)
686
687 /*
688  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
689  */
690 #define __read_32bit_c0_ctrl_register(source)                           \
691 ({ int __res;                                                           \
692         __asm__ __volatile__(                                           \
693                 "cfc0\t%0, " #source "\n\t"                             \
694                 : "=r" (__res));                                        \
695         __res;                                                          \
696 })
697
698 #define __write_32bit_c0_ctrl_register(register, value)                 \
699 do {                                                                    \
700         __asm__ __volatile__(                                           \
701                 "ctc0\t%z0, " #register "\n\t"                          \
702                 : : "Jr" ((unsigned int)(value)));                      \
703 } while (0)
704
705 /*
706  * These versions are only needed for systems with more than 38 bits of
707  * physical address space running the 32-bit kernel.  That's none atm :-)
708  */
709 #define __read_64bit_c0_split(source, sel)                              \
710 ({                                                                      \
711         unsigned long long __val;                                       \
712         unsigned long __flags;                                          \
713                                                                         \
714         local_irq_save(__flags);                                        \
715         if (sel == 0)                                                   \
716                 __asm__ __volatile__(                                   \
717                         ".set\tmips64\n\t"                              \
718                         "dmfc0\t%M0, " #source "\n\t"                   \
719                         "dsll\t%L0, %M0, 32\n\t"                        \
720                         "dsrl\t%M0, %M0, 32\n\t"                        \
721                         "dsrl\t%L0, %L0, 32\n\t"                        \
722                         ".set\tmips0"                                   \
723                         : "=r" (__val));                                \
724         else                                                            \
725                 __asm__ __volatile__(                                   \
726                         ".set\tmips64\n\t"                              \
727                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
728                         "dsll\t%L0, %M0, 32\n\t"                        \
729                         "dsrl\t%M0, %M0, 32\n\t"                        \
730                         "dsrl\t%L0, %L0, 32\n\t"                        \
731                         ".set\tmips0"                                   \
732                         : "=r" (__val));                                \
733         local_irq_restore(__flags);                                     \
734                                                                         \
735         __val;                                                          \
736 })
737
738 #define __write_64bit_c0_split(source, sel, val)                        \
739 do {                                                                    \
740         unsigned long __flags;                                          \
741                                                                         \
742         local_irq_save(__flags);                                        \
743         if (sel == 0)                                                   \
744                 __asm__ __volatile__(                                   \
745                         ".set\tmips64\n\t"                              \
746                         "dsll\t%L0, %L0, 32\n\t"                        \
747                         "dsrl\t%L0, %L0, 32\n\t"                        \
748                         "dsll\t%M0, %M0, 32\n\t"                        \
749                         "or\t%L0, %L0, %M0\n\t"                         \
750                         "dmtc0\t%L0, " #source "\n\t"                   \
751                         ".set\tmips0"                                   \
752                         : : "r" (val));                                 \
753         else                                                            \
754                 __asm__ __volatile__(                                   \
755                         ".set\tmips64\n\t"                              \
756                         "dsll\t%L0, %L0, 32\n\t"                        \
757                         "dsrl\t%L0, %L0, 32\n\t"                        \
758                         "dsll\t%M0, %M0, 32\n\t"                        \
759                         "or\t%L0, %L0, %M0\n\t"                         \
760                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
761                         ".set\tmips0"                                   \
762                         : : "r" (val));                                 \
763         local_irq_restore(__flags);                                     \
764 } while (0)
765
766 #define read_c0_index()         __read_32bit_c0_register($0, 0)
767 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
768
769 #define read_c0_random()        __read_32bit_c0_register($1, 0)
770 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
771
772 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
773 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
774
775 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
776 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
777
778 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
779 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
780
781 #define read_c0_context()       __read_ulong_c0_register($4, 0)
782 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
783
784 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
785 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
786
787 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
788 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
789
790 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
791 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
792
793 #define read_c0_info()          __read_32bit_c0_register($7, 0)
794
795 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
796 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
797
798 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
799 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
800
801 #define read_c0_count()         __read_32bit_c0_register($9, 0)
802 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
803
804 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
805 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
806
807 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
808 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
809
810 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
811 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
812
813 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
814 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
815
816 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
817 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
818
819 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
820 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
821
822 #define read_c0_status()        __read_32bit_c0_register($12, 0)
823 #ifdef CONFIG_MIPS_MT_SMTC
824 #define write_c0_status(val)                                            \
825 do {                                                                    \
826         __write_32bit_c0_register($12, 0, val);                         \
827         __ehb();                                                        \
828 } while (0)
829 #else
830 /*
831  * Legacy non-SMTC code, which may be hazardous
832  * but which might not support EHB
833  */
834 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
835 #endif /* CONFIG_MIPS_MT_SMTC */
836
837 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
838 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
839
840 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
841 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
842
843 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
844
845 #define read_c0_config()        __read_32bit_c0_register($16, 0)
846 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
847 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
848 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
849 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
850 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
851 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
852 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
853 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
854 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
855 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
856 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
857 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
858 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
859 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
860 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
861
862 /*
863  * The WatchLo register.  There may be upto 8 of them.
864  */
865 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
866 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
867 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
868 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
869 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
870 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
871 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
872 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
873 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
874 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
875 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
876 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
877 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
878 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
879 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
880 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
881
882 /*
883  * The WatchHi register.  There may be upto 8 of them.
884  */
885 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
886 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
887 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
888 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
889 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
890 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
891 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
892 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
893
894 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
895 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
896 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
897 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
898 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
899 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
900 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
901 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
902
903 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
904 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
905
906 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
907 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
908
909 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
910 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
911
912 /* RM9000 PerfControl performance counter control register */
913 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
914 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
915
916 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
917 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
918
919 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
920 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
921
922 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
923 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
924
925 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
926 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
927
928 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
929 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
930
931 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
932 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
933
934 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
935 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
936
937 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
938 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
939
940 /*
941  * MIPS32 / MIPS64 performance counters
942  */
943 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
944 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
945 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
946 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
947 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
948 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
949 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
950 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
951 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
952 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
953 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
954 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
955 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
956 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
957 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
958 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
959
960 /* RM9000 PerfCount performance counter register */
961 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
962 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
963
964 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
965 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
966
967 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
968 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
969
970 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
971
972 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
973 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
974
975 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
976 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
977
978 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
979 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
980
981 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
982 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
983
984 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
985 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
986
987 /* MIPSR2 */
988 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
989 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
990
991 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
992 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
993
994 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
995 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
996
997 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
998 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
999
1000 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1001 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1002
1003
1004 /* Cavium OCTEON (cnMIPS) */
1005 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1006 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1007
1008 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1009 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1010
1011 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1012 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1013 /*
1014  * The cacheerr registers are not standardized.  On OCTEON, they are
1015  * 64 bits wide.
1016  */
1017 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1018 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1019
1020 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1021 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1022
1023 /*
1024  * Macros to access the floating point coprocessor control registers
1025  */
1026 #define read_32bit_cp1_register(source)                         \
1027 ({ int __res;                                                   \
1028         __asm__ __volatile__(                                   \
1029         ".set\tpush\n\t"                                        \
1030         ".set\treorder\n\t"                                     \
1031         /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1032         ".set\tmips1\n\t"                                       \
1033         "cfc1\t%0,"STR(source)"\n\t"                            \
1034         ".set\tpop"                                             \
1035         : "=r" (__res));                                        \
1036         __res;})
1037
1038 #define rddsp(mask)                                                     \
1039 ({                                                                      \
1040         unsigned int __res;                                             \
1041                                                                         \
1042         __asm__ __volatile__(                                           \
1043         "       .set    push                            \n"             \
1044         "       .set    noat                            \n"             \
1045         "       # rddsp $1, %x1                         \n"             \
1046         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1047         "       move    %0, $1                          \n"             \
1048         "       .set    pop                             \n"             \
1049         : "=r" (__res)                                                  \
1050         : "i" (mask));                                                  \
1051         __res;                                                          \
1052 })
1053
1054 #define wrdsp(val, mask)                                                \
1055 do {                                                                    \
1056         __asm__ __volatile__(                                           \
1057         "       .set    push                                    \n"     \
1058         "       .set    noat                                    \n"     \
1059         "       move    $1, %0                                  \n"     \
1060         "       # wrdsp $1, %x1                                 \n"     \
1061         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1062         "       .set    pop                                     \n"     \
1063         :                                                               \
1064         : "r" (val), "i" (mask));                                       \
1065 } while (0)
1066
1067 #if 0   /* Need DSP ASE capable assembler ... */
1068 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1069 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1070 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1071 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1072
1073 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1074 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1075 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1076 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1077
1078 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1079 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1080 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1081 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1082
1083 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1084 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1085 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1086 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1087
1088 #else
1089
1090 #define mfhi0()                                                         \
1091 ({                                                                      \
1092         unsigned long __treg;                                           \
1093                                                                         \
1094         __asm__ __volatile__(                                           \
1095         "       .set    push                    \n"                     \
1096         "       .set    noat                    \n"                     \
1097         "       # mfhi  %0, $ac0                \n"                     \
1098         "       .word   0x00000810              \n"                     \
1099         "       move    %0, $1                  \n"                     \
1100         "       .set    pop                     \n"                     \
1101         : "=r" (__treg));                                               \
1102         __treg;                                                         \
1103 })
1104
1105 #define mfhi1()                                                         \
1106 ({                                                                      \
1107         unsigned long __treg;                                           \
1108                                                                         \
1109         __asm__ __volatile__(                                           \
1110         "       .set    push                    \n"                     \
1111         "       .set    noat                    \n"                     \
1112         "       # mfhi  %0, $ac1                \n"                     \
1113         "       .word   0x00200810              \n"                     \
1114         "       move    %0, $1                  \n"                     \
1115         "       .set    pop                     \n"                     \
1116         : "=r" (__treg));                                               \
1117         __treg;                                                         \
1118 })
1119
1120 #define mfhi2()                                                         \
1121 ({                                                                      \
1122         unsigned long __treg;                                           \
1123                                                                         \
1124         __asm__ __volatile__(                                           \
1125         "       .set    push                    \n"                     \
1126         "       .set    noat                    \n"                     \
1127         "       # mfhi  %0, $ac2                \n"                     \
1128         "       .word   0x00400810              \n"                     \
1129         "       move    %0, $1                  \n"                     \
1130         "       .set    pop                     \n"                     \
1131         : "=r" (__treg));                                               \
1132         __treg;                                                         \
1133 })
1134
1135 #define mfhi3()                                                         \
1136 ({                                                                      \
1137         unsigned long __treg;                                           \
1138                                                                         \
1139         __asm__ __volatile__(                                           \
1140         "       .set    push                    \n"                     \
1141         "       .set    noat                    \n"                     \
1142         "       # mfhi  %0, $ac3                \n"                     \
1143         "       .word   0x00600810              \n"                     \
1144         "       move    %0, $1                  \n"                     \
1145         "       .set    pop                     \n"                     \
1146         : "=r" (__treg));                                               \
1147         __treg;                                                         \
1148 })
1149
1150 #define mflo0()                                                         \
1151 ({                                                                      \
1152         unsigned long __treg;                                           \
1153                                                                         \
1154         __asm__ __volatile__(                                           \
1155         "       .set    push                    \n"                     \
1156         "       .set    noat                    \n"                     \
1157         "       # mflo  %0, $ac0                \n"                     \
1158         "       .word   0x00000812              \n"                     \
1159         "       move    %0, $1                  \n"                     \
1160         "       .set    pop                     \n"                     \
1161         : "=r" (__treg));                                               \
1162         __treg;                                                         \
1163 })
1164
1165 #define mflo1()                                                         \
1166 ({                                                                      \
1167         unsigned long __treg;                                           \
1168                                                                         \
1169         __asm__ __volatile__(                                           \
1170         "       .set    push                    \n"                     \
1171         "       .set    noat                    \n"                     \
1172         "       # mflo  %0, $ac1                \n"                     \
1173         "       .word   0x00200812              \n"                     \
1174         "       move    %0, $1                  \n"                     \
1175         "       .set    pop                     \n"                     \
1176         : "=r" (__treg));                                               \
1177         __treg;                                                         \
1178 })
1179
1180 #define mflo2()                                                         \
1181 ({                                                                      \
1182         unsigned long __treg;                                           \
1183                                                                         \
1184         __asm__ __volatile__(                                           \
1185         "       .set    push                    \n"                     \
1186         "       .set    noat                    \n"                     \
1187         "       # mflo  %0, $ac2                \n"                     \
1188         "       .word   0x00400812              \n"                     \
1189         "       move    %0, $1                  \n"                     \
1190         "       .set    pop                     \n"                     \
1191         : "=r" (__treg));                                               \
1192         __treg;                                                         \
1193 })
1194
1195 #define mflo3()                                                         \
1196 ({                                                                      \
1197         unsigned long __treg;                                           \
1198                                                                         \
1199         __asm__ __volatile__(                                           \
1200         "       .set    push                    \n"                     \
1201         "       .set    noat                    \n"                     \
1202         "       # mflo  %0, $ac3                \n"                     \
1203         "       .word   0x00600812              \n"                     \
1204         "       move    %0, $1                  \n"                     \
1205         "       .set    pop                     \n"                     \
1206         : "=r" (__treg));                                               \
1207         __treg;                                                         \
1208 })
1209
1210 #define mthi0(x)                                                        \
1211 do {                                                                    \
1212         __asm__ __volatile__(                                           \
1213         "       .set    push                                    \n"     \
1214         "       .set    noat                                    \n"     \
1215         "       move    $1, %0                                  \n"     \
1216         "       # mthi  $1, $ac0                                \n"     \
1217         "       .word   0x00200011                              \n"     \
1218         "       .set    pop                                     \n"     \
1219         :                                                               \
1220         : "r" (x));                                                     \
1221 } while (0)
1222
1223 #define mthi1(x)                                                        \
1224 do {                                                                    \
1225         __asm__ __volatile__(                                           \
1226         "       .set    push                                    \n"     \
1227         "       .set    noat                                    \n"     \
1228         "       move    $1, %0                                  \n"     \
1229         "       # mthi  $1, $ac1                                \n"     \
1230         "       .word   0x00200811                              \n"     \
1231         "       .set    pop                                     \n"     \
1232         :                                                               \
1233         : "r" (x));                                                     \
1234 } while (0)
1235
1236 #define mthi2(x)                                                        \
1237 do {                                                                    \
1238         __asm__ __volatile__(                                           \
1239         "       .set    push                                    \n"     \
1240         "       .set    noat                                    \n"     \
1241         "       move    $1, %0                                  \n"     \
1242         "       # mthi  $1, $ac2                                \n"     \
1243         "       .word   0x00201011                              \n"     \
1244         "       .set    pop                                     \n"     \
1245         :                                                               \
1246         : "r" (x));                                                     \
1247 } while (0)
1248
1249 #define mthi3(x)                                                        \
1250 do {                                                                    \
1251         __asm__ __volatile__(                                           \
1252         "       .set    push                                    \n"     \
1253         "       .set    noat                                    \n"     \
1254         "       move    $1, %0                                  \n"     \
1255         "       # mthi  $1, $ac3                                \n"     \
1256         "       .word   0x00201811                              \n"     \
1257         "       .set    pop                                     \n"     \
1258         :                                                               \
1259         : "r" (x));                                                     \
1260 } while (0)
1261
1262 #define mtlo0(x)                                                        \
1263 do {                                                                    \
1264         __asm__ __volatile__(                                           \
1265         "       .set    push                                    \n"     \
1266         "       .set    noat                                    \n"     \
1267         "       move    $1, %0                                  \n"     \
1268         "       # mtlo  $1, $ac0                                \n"     \
1269         "       .word   0x00200013                              \n"     \
1270         "       .set    pop                                     \n"     \
1271         :                                                               \
1272         : "r" (x));                                                     \
1273 } while (0)
1274
1275 #define mtlo1(x)                                                        \
1276 do {                                                                    \
1277         __asm__ __volatile__(                                           \
1278         "       .set    push                                    \n"     \
1279         "       .set    noat                                    \n"     \
1280         "       move    $1, %0                                  \n"     \
1281         "       # mtlo  $1, $ac1                                \n"     \
1282         "       .word   0x00200813                              \n"     \
1283         "       .set    pop                                     \n"     \
1284         :                                                               \
1285         : "r" (x));                                                     \
1286 } while (0)
1287
1288 #define mtlo2(x)                                                        \
1289 do {                                                                    \
1290         __asm__ __volatile__(                                           \
1291         "       .set    push                                    \n"     \
1292         "       .set    noat                                    \n"     \
1293         "       move    $1, %0                                  \n"     \
1294         "       # mtlo  $1, $ac2                                \n"     \
1295         "       .word   0x00201013                              \n"     \
1296         "       .set    pop                                     \n"     \
1297         :                                                               \
1298         : "r" (x));                                                     \
1299 } while (0)
1300
1301 #define mtlo3(x)                                                        \
1302 do {                                                                    \
1303         __asm__ __volatile__(                                           \
1304         "       .set    push                                    \n"     \
1305         "       .set    noat                                    \n"     \
1306         "       move    $1, %0                                  \n"     \
1307         "       # mtlo  $1, $ac3                                \n"     \
1308         "       .word   0x00201813                              \n"     \
1309         "       .set    pop                                     \n"     \
1310         :                                                               \
1311         : "r" (x));                                                     \
1312 } while (0)
1313
1314 #endif
1315
1316 /*
1317  * TLB operations.
1318  *
1319  * It is responsibility of the caller to take care of any TLB hazards.
1320  */
1321 static inline void tlb_probe(void)
1322 {
1323         __asm__ __volatile__(
1324                 ".set noreorder\n\t"
1325                 "tlbp\n\t"
1326                 ".set reorder");
1327 }
1328
1329 static inline void tlb_read(void)
1330 {
1331 #if MIPS34K_MISSED_ITLB_WAR
1332         int res = 0;
1333
1334         __asm__ __volatile__(
1335         "       .set    push                                    \n"
1336         "       .set    noreorder                               \n"
1337         "       .set    noat                                    \n"
1338         "       .set    mips32r2                                \n"
1339         "       .word   0x41610001              # dvpe $1       \n"
1340         "       move    %0, $1                                  \n"
1341         "       ehb                                             \n"
1342         "       .set    pop                                     \n"
1343         : "=r" (res));
1344
1345         instruction_hazard();
1346 #endif
1347
1348         __asm__ __volatile__(
1349                 ".set noreorder\n\t"
1350                 "tlbr\n\t"
1351                 ".set reorder");
1352
1353 #if MIPS34K_MISSED_ITLB_WAR
1354         if ((res & _ULCAST_(1)))
1355                 __asm__ __volatile__(
1356                 "       .set    push                            \n"
1357                 "       .set    noreorder                       \n"
1358                 "       .set    noat                            \n"
1359                 "       .set    mips32r2                        \n"
1360                 "       .word   0x41600021      # evpe          \n"
1361                 "       ehb                                     \n"
1362                 "       .set    pop                             \n");
1363 #endif
1364 }
1365
1366 static inline void tlb_write_indexed(void)
1367 {
1368         __asm__ __volatile__(
1369                 ".set noreorder\n\t"
1370                 "tlbwi\n\t"
1371                 ".set reorder");
1372 }
1373
1374 static inline void tlb_write_random(void)
1375 {
1376         __asm__ __volatile__(
1377                 ".set noreorder\n\t"
1378                 "tlbwr\n\t"
1379                 ".set reorder");
1380 }
1381
1382 /*
1383  * Manipulate bits in a c0 register.
1384  */
1385 #ifndef CONFIG_MIPS_MT_SMTC
1386 /*
1387  * SMTC Linux requires shutting-down microthread scheduling
1388  * during CP0 register read-modify-write sequences.
1389  */
1390 #define __BUILD_SET_C0(name)                                    \
1391 static inline unsigned int                                      \
1392 set_c0_##name(unsigned int set)                                 \
1393 {                                                               \
1394         unsigned int res;                                       \
1395                                                                 \
1396         res = read_c0_##name();                                 \
1397         res |= set;                                             \
1398         write_c0_##name(res);                                   \
1399                                                                 \
1400         return res;                                             \
1401 }                                                               \
1402                                                                 \
1403 static inline unsigned int                                      \
1404 clear_c0_##name(unsigned int clear)                             \
1405 {                                                               \
1406         unsigned int res;                                       \
1407                                                                 \
1408         res = read_c0_##name();                                 \
1409         res &= ~clear;                                          \
1410         write_c0_##name(res);                                   \
1411                                                                 \
1412         return res;                                             \
1413 }                                                               \
1414                                                                 \
1415 static inline unsigned int                                      \
1416 change_c0_##name(unsigned int change, unsigned int new)         \
1417 {                                                               \
1418         unsigned int res;                                       \
1419                                                                 \
1420         res = read_c0_##name();                                 \
1421         res &= ~change;                                         \
1422         res |= (new & change);                                  \
1423         write_c0_##name(res);                                   \
1424                                                                 \
1425         return res;                                             \
1426 }
1427
1428 #else /* SMTC versions that manage MT scheduling */
1429
1430 #include <linux/irqflags.h>
1431
1432 /*
1433  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1434  * header file recursion.
1435  */
1436 static inline unsigned int __dmt(void)
1437 {
1438         int res;
1439
1440         __asm__ __volatile__(
1441         "       .set    push                                            \n"
1442         "       .set    mips32r2                                        \n"
1443         "       .set    noat                                            \n"
1444         "       .word   0x41610BC1                      # dmt $1        \n"
1445         "       ehb                                                     \n"
1446         "       move    %0, $1                                          \n"
1447         "       .set    pop                                             \n"
1448         : "=r" (res));
1449
1450         instruction_hazard();
1451
1452         return res;
1453 }
1454
1455 #define __VPECONTROL_TE_SHIFT   15
1456 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1457
1458 #define __EMT_ENABLE            __VPECONTROL_TE
1459
1460 static inline void __emt(unsigned int previous)
1461 {
1462         if ((previous & __EMT_ENABLE))
1463                 __asm__ __volatile__(
1464                 "       .set    mips32r2                                \n"
1465                 "       .word   0x41600be1              # emt           \n"
1466                 "       ehb                                             \n"
1467                 "       .set    mips0                                   \n");
1468 }
1469
1470 static inline void __ehb(void)
1471 {
1472         __asm__ __volatile__(
1473         "       .set    mips32r2                                        \n"
1474         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1475 }
1476
1477 /*
1478  * Note that local_irq_save/restore affect TC-specific IXMT state,
1479  * not Status.IE as in non-SMTC kernel.
1480  */
1481
1482 #define __BUILD_SET_C0(name)                                    \
1483 static inline unsigned int                                      \
1484 set_c0_##name(unsigned int set)                                 \
1485 {                                                               \
1486         unsigned int res;                                       \
1487         unsigned int omt;                                       \
1488         unsigned long flags;                                    \
1489                                                                 \
1490         local_irq_save(flags);                                  \
1491         omt = __dmt();                                          \
1492         res = read_c0_##name();                                 \
1493         res |= set;                                             \
1494         write_c0_##name(res);                                   \
1495         __emt(omt);                                             \
1496         local_irq_restore(flags);                               \
1497                                                                 \
1498         return res;                                             \
1499 }                                                               \
1500                                                                 \
1501 static inline unsigned int                                      \
1502 clear_c0_##name(unsigned int clear)                             \
1503 {                                                               \
1504         unsigned int res;                                       \
1505         unsigned int omt;                                       \
1506         unsigned long flags;                                    \
1507                                                                 \
1508         local_irq_save(flags);                                  \
1509         omt = __dmt();                                          \
1510         res = read_c0_##name();                                 \
1511         res &= ~clear;                                          \
1512         write_c0_##name(res);                                   \
1513         __emt(omt);                                             \
1514         local_irq_restore(flags);                               \
1515                                                                 \
1516         return res;                                             \
1517 }                                                               \
1518                                                                 \
1519 static inline unsigned int                                      \
1520 change_c0_##name(unsigned int change, unsigned int new)         \
1521 {                                                               \
1522         unsigned int res;                                       \
1523         unsigned int omt;                                       \
1524         unsigned long flags;                                    \
1525                                                                 \
1526         local_irq_save(flags);                                  \
1527                                                                 \
1528         omt = __dmt();                                          \
1529         res = read_c0_##name();                                 \
1530         res &= ~change;                                         \
1531         res |= (new & change);                                  \
1532         write_c0_##name(res);                                   \
1533         __emt(omt);                                             \
1534         local_irq_restore(flags);                               \
1535                                                                 \
1536         return res;                                             \
1537 }
1538 #endif
1539
1540 __BUILD_SET_C0(status)
1541 __BUILD_SET_C0(cause)
1542 __BUILD_SET_C0(config)
1543 __BUILD_SET_C0(intcontrol)
1544 __BUILD_SET_C0(intctl)
1545 __BUILD_SET_C0(srsmap)
1546
1547 #endif /* !__ASSEMBLY__ */
1548
1549 #endif /* _ASM_MIPSREGS_H */