arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 2003  Maciej W. Rozycki
   6  * Copyright (C) 1994 - 2003 Ralf Baechle
   7  * Copyright (C) 2001 MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/bugs.h>
  21 #include <asm/cpu.h>
  22 #include <asm/fpu.h>
  23 #include <asm/mipsregs.h>
  24 #include <asm/system.h>
  25
  26 /*
  27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  28  * the implementation of the "wait" feature differs between CPU families. This
  29  * points to the function that implements CPU specific wait.
  30  * The wait instruction stops the pipeline and reduces the power consumption of
  31  * the CPU very much.
  32  */
  33 void (*cpu_wait)(void) = NULL;
  34
  35 static void r3081_wait(void)
  36 {
  37         unsigned long cfg = read_c0_conf();
  38         write_c0_conf(cfg | R30XX_CONF_HALT);
  39 }
  40
  41 static void r39xx_wait(void)
  42 {
  43         unsigned long cfg = read_c0_conf();
  44         write_c0_conf(cfg | TX39_CONF_HALT);
  45 }
  46
  47 static void r4k_wait(void)
  48 {
  49         __asm__(".set\tmips3\n\t"
  50                 "wait\n\t"
  51                 ".set\tmips0");
  52 }
  53
  54 /* The Au1xxx wait is available only if using 32khz counter or
  55  * external timer source, but specifically not CP0 Counter. */
  56 int allow_au1k_wait;
  57 static void au1k_wait(void)
  58 {
  59         unsigned long addr = 0;
  60         /* using the wait instruction makes CP0 counter unusable */
  61         __asm__("la %0,au1k_wait\n\t"
  62                 ".set mips3\n\t"
  63                 "cache 0x14,0(%0)\n\t"
  64                 "cache 0x14,32(%0)\n\t"
  65                 "sync\n\t"
  66                 "nop\n\t"
  67                 "wait\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 "nop\n\t"
  71                 "nop\n\t"
  72                 ".set mips0\n\t"
  73                 : : "r" (addr));
  74 }
  75
  76 static inline void check_wait(void)
  77 {
  78         struct cpuinfo_mips *c = &current_cpu_data;
  79
  80         printk("Checking for 'wait' instruction... ");
  81         switch (c->cputype) {
  82         case CPU_R3081:
  83         case CPU_R3081E:
  84                 cpu_wait = r3081_wait;
  85                 printk(" available.\n");
  86                 break;
  87         case CPU_TX3927:
  88                 cpu_wait = r39xx_wait;
  89                 printk(" available.\n");
  90                 break;
  91         case CPU_R4200:
  92 /*      case CPU_R4300: */
  93         case CPU_R4600:
  94         case CPU_R4640:
  95         case CPU_R4650:
  96         case CPU_R4700:
  97         case CPU_R5000:
  98         case CPU_NEVADA:
  99         case CPU_RM7000:
 100         case CPU_RM9000:
 101         case CPU_TX49XX:
 102         case CPU_4KC:
 103         case CPU_4KEC:
 104         case CPU_4KSC:
 105         case CPU_5KC:
 106 /*      case CPU_20KC:*/
 107         case CPU_24K:
 108         case CPU_25KF:
 109                 cpu_wait = r4k_wait;
 110                 printk(" available.\n");
 111                 break;
 112         case CPU_AU1000:
 113         case CPU_AU1100:
 114         case CPU_AU1500:
 115         case CPU_AU1550:
 116         case CPU_AU1200:
 117                 if (allow_au1k_wait) {
 118                         cpu_wait = au1k_wait;
 119                         printk(" available.\n");
 120                 } else
 121                         printk(" unavailable.\n");
 122                 break;
 123         default:
 124                 printk(" unavailable.\n");
 125                 break;
 126         }
 127 }
 128
 129 void __init check_bugs32(void)
 130 {
 131         check_wait();
 132 }
 133
 134 /*
 135  * Probe whether cpu has config register by trying to play with
 136  * alternate cache bit and see whether it matters.
 137  * It's used by cpu_probe to distinguish between R3000A and R3081.
 138  */
 139 static inline int cpu_has_confreg(void)
 140 {
 141 #ifdef CONFIG_CPU_R3000
 142         extern unsigned long r3k_cache_size(unsigned long);
 143         unsigned long size1, size2;
 144         unsigned long cfg = read_c0_conf();
 145
 146         size1 = r3k_cache_size(ST0_ISC);
 147         write_c0_conf(cfg ^ R30XX_CONF_AC);
 148         size2 = r3k_cache_size(ST0_ISC);
 149         write_c0_conf(cfg);
 150         return size1 != size2;
 151 #else
 152         return 0;
 153 #endif
 154 }
 155
 156 /*
 157  * Get the FPU Implementation/Revision.
 158  */
 159 static inline unsigned long cpu_get_fpu_id(void)
 160 {
 161         unsigned long tmp, fpu_id;
 162
 163         tmp = read_c0_status();
 164         __enable_fpu();
 165         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 166         write_c0_status(tmp);
 167         return fpu_id;
 168 }
 169
 170 /*
 171  * Check the CPU has an FPU the official way.
 172  */
 173 static inline int __cpu_has_fpu(void)
 174 {
 175         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 176 }
 177
 178 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 179                 | MIPS_CPU_COUNTER)
 180
 181 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 182 {
 183         switch (c->processor_id & 0xff00) {
 184         case PRID_IMP_R2000:
 185                 c->cputype = CPU_R2000;
 186                 c->isa_level = MIPS_CPU_ISA_I;
 187                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 188                 if (__cpu_has_fpu())
 189                         c->options |= MIPS_CPU_FPU;
 190                 c->tlbsize = 64;
 191                 break;
 192         case PRID_IMP_R3000:
 193                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 194                         if (cpu_has_confreg())
 195                                 c->cputype = CPU_R3081E;
 196                         else
 197                                 c->cputype = CPU_R3000A;
 198                 else
 199                         c->cputype = CPU_R3000;
 200                 c->isa_level = MIPS_CPU_ISA_I;
 201                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 202                 if (__cpu_has_fpu())
 203                         c->options |= MIPS_CPU_FPU;
 204                 c->tlbsize = 64;
 205                 break;
 206         case PRID_IMP_R4000:
 207                 if (read_c0_config() & CONF_SC) {
 208                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 209                                 c->cputype = CPU_R4400PC;
 210                         else
 211                                 c->cputype = CPU_R4000PC;
 212                 } else {
 213                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 214                                 c->cputype = CPU_R4400SC;
 215                         else
 216                                 c->cputype = CPU_R4000SC;
 217                 }
 218
 219                 c->isa_level = MIPS_CPU_ISA_III;
 220                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 221                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 222                              MIPS_CPU_LLSC;
 223                 c->tlbsize = 48;
 224                 break;
 225         case PRID_IMP_VR41XX:
 226                 switch (c->processor_id & 0xf0) {
 227                 case PRID_REV_VR4111:
 228                         c->cputype = CPU_VR4111;
 229                         break;
 230                 case PRID_REV_VR4121:
 231                         c->cputype = CPU_VR4121;
 232                         break;
 233                 case PRID_REV_VR4122:
 234                         if ((c->processor_id & 0xf) < 0x3)
 235                                 c->cputype = CPU_VR4122;
 236                         else
 237                                 c->cputype = CPU_VR4181A;
 238                         break;
 239                 case PRID_REV_VR4130:
 240                         if ((c->processor_id & 0xf) < 0x4)
 241                                 c->cputype = CPU_VR4131;
 242                         else
 243                                 c->cputype = CPU_VR4133;
 244                         break;
 245                 default:
 246                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 247                         c->cputype = CPU_VR41XX;
 248                         break;
 249                 }
 250                 c->isa_level = MIPS_CPU_ISA_III;
 251                 c->options = R4K_OPTS;
 252                 c->tlbsize = 32;
 253                 break;
 254         case PRID_IMP_R4300:
 255                 c->cputype = CPU_R4300;
 256                 c->isa_level = MIPS_CPU_ISA_III;
 257                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 258                              MIPS_CPU_LLSC;
 259                 c->tlbsize = 32;
 260                 break;
 261         case PRID_IMP_R4600:
 262                 c->cputype = CPU_R4600;
 263                 c->isa_level = MIPS_CPU_ISA_III;
 264                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 265                 c->tlbsize = 48;
 266                 break;
 267         #if 0
 268         case PRID_IMP_R4650:
 269                 /*
 270                  * This processor doesn't have an MMU, so it's not
 271                  * "real easy" to run Linux on it. It is left purely
 272                  * for documentation.  Commented out because it shares
 273                  * it's c0_prid id number with the TX3900.
 274                  */
 275                 c->cputype = CPU_R4650;
 276                 c->isa_level = MIPS_CPU_ISA_III;
 277                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 278                 c->tlbsize = 48;
 279                 break;
 280         #endif
 281         case PRID_IMP_TX39:
 282                 c->isa_level = MIPS_CPU_ISA_I;
 283                 c->options = MIPS_CPU_TLB;
 284
 285                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 286                         c->cputype = CPU_TX3927;
 287                         c->tlbsize = 64;
 288                 } else {
 289                         switch (c->processor_id & 0xff) {
 290                         case PRID_REV_TX3912:
 291                                 c->cputype = CPU_TX3912;
 292                                 c->tlbsize = 32;
 293                                 break;
 294                         case PRID_REV_TX3922:
 295                                 c->cputype = CPU_TX3922;
 296                                 c->tlbsize = 64;
 297                                 break;
 298                         default:
 299                                 c->cputype = CPU_UNKNOWN;
 300                                 break;
 301                         }
 302                 }
 303                 break;
 304         case PRID_IMP_R4700:
 305                 c->cputype = CPU_R4700;
 306                 c->isa_level = MIPS_CPU_ISA_III;
 307                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 308                              MIPS_CPU_LLSC;
 309                 c->tlbsize = 48;
 310                 break;
 311         case PRID_IMP_TX49:
 312                 c->cputype = CPU_TX49XX;
 313                 c->isa_level = MIPS_CPU_ISA_III;
 314                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 315                 if (!(c->processor_id & 0x08))
 316                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 317                 c->tlbsize = 48;
 318                 break;
 319         case PRID_IMP_R5000:
 320                 c->cputype = CPU_R5000;
 321                 c->isa_level = MIPS_CPU_ISA_IV;
 322                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 323                              MIPS_CPU_LLSC;
 324                 c->tlbsize = 48;
 325                 break;
 326         case PRID_IMP_R5432:
 327                 c->cputype = CPU_R5432;
 328                 c->isa_level = MIPS_CPU_ISA_IV;
 329                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 330                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 331                 c->tlbsize = 48;
 332                 break;
 333         case PRID_IMP_R5500:
 334                 c->cputype = CPU_R5500;
 335                 c->isa_level = MIPS_CPU_ISA_IV;
 336                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 337                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 338                 c->tlbsize = 48;
 339                 break;
 340         case PRID_IMP_NEVADA:
 341                 c->cputype = CPU_NEVADA;
 342                 c->isa_level = MIPS_CPU_ISA_IV;
 343                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 344                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 345                 c->tlbsize = 48;
 346                 break;
 347         case PRID_IMP_R6000:
 348                 c->cputype = CPU_R6000;
 349                 c->isa_level = MIPS_CPU_ISA_II;
 350                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 351                              MIPS_CPU_LLSC;
 352                 c->tlbsize = 32;
 353                 break;
 354         case PRID_IMP_R6000A:
 355                 c->cputype = CPU_R6000A;
 356                 c->isa_level = MIPS_CPU_ISA_II;
 357                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 358                              MIPS_CPU_LLSC;
 359                 c->tlbsize = 32;
 360                 break;
 361         case PRID_IMP_RM7000:
 362                 c->cputype = CPU_RM7000;
 363                 c->isa_level = MIPS_CPU_ISA_IV;
 364                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 365                              MIPS_CPU_LLSC;
 366                 /*
 367                  * Undocumented RM7000:  Bit 29 in the info register of
 368                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 369                  * entries.
 370                  *
 371                  * 29      1 =>    64 entry JTLB
 372                  *         0 =>    48 entry JTLB
 373                  */
 374                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 375                 break;
 376         case PRID_IMP_RM9000:
 377                 c->cputype = CPU_RM9000;
 378                 c->isa_level = MIPS_CPU_ISA_IV;
 379                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 380                              MIPS_CPU_LLSC;
 381                 /*
 382                  * Bit 29 in the info register of the RM9000
 383                  * indicates if the TLB has 48 or 64 entries.
 384                  *
 385                  * 29      1 =>    64 entry JTLB
 386                  *         0 =>    48 entry JTLB
 387                  */
 388                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 389                 break;
 390         case PRID_IMP_R8000:
 391                 c->cputype = CPU_R8000;
 392                 c->isa_level = MIPS_CPU_ISA_IV;
 393                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 394                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 395                              MIPS_CPU_LLSC;
 396                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 397                 break;
 398         case PRID_IMP_R10000:
 399                 c->cputype = CPU_R10000;
 400                 c->isa_level = MIPS_CPU_ISA_IV;
 401                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 402                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 403                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 404                              MIPS_CPU_LLSC;
 405                 c->tlbsize = 64;
 406                 break;
 407         case PRID_IMP_R12000:
 408                 c->cputype = CPU_R12000;
 409                 c->isa_level = MIPS_CPU_ISA_IV;
 410                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 411                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 412                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 413                              MIPS_CPU_LLSC;
 414                 c->tlbsize = 64;
 415                 break;
 416         }
 417 }
 418
 419 static inline void decode_config1(struct cpuinfo_mips *c)
 420 {
 421         unsigned long config0 = read_c0_config();
 422         unsigned long config1;
 423
 424         if ((config0 & (1 << 31)) == 0)
 425                 return;                 /* actually wort a panic() */
 426
 427         /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
 428         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 429                 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 430                 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 431         config1 = read_c0_config1();
 432         if (config1 & (1 << 3))
 433                 c->options |= MIPS_CPU_WATCH;
 434         if (config1 & (1 << 2))
 435                 c->options |= MIPS_CPU_MIPS16;
 436         if (config1 & (1 << 1))
 437                 c->options |= MIPS_CPU_EJTAG;
 438         if (config1 & 1) {
 439                 c->options |= MIPS_CPU_FPU;
 440                 c->options |= MIPS_CPU_32FPR;
 441         }
 442         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 443
 444         c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
 445 }
 446
 447 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 448 {
 449         decode_config1(c);
 450         switch (c->processor_id & 0xff00) {
 451         case PRID_IMP_4KC:
 452                 c->cputype = CPU_4KC;
 453                 c->isa_level = MIPS_CPU_ISA_M32;
 454                 break;
 455         case PRID_IMP_4KEC:
 456                 c->cputype = CPU_4KEC;
 457                 c->isa_level = MIPS_CPU_ISA_M32;
 458                 break;
 459         case PRID_IMP_4KECR2:
 460                 c->cputype = CPU_4KEC;
 461                 c->isa_level = MIPS_CPU_ISA_M32;
 462                 break;
 463         case PRID_IMP_4KSC:
 464                 c->cputype = CPU_4KSC;
 465                 c->isa_level = MIPS_CPU_ISA_M32;
 466                 break;
 467         case PRID_IMP_5KC:
 468                 c->cputype = CPU_5KC;
 469                 c->isa_level = MIPS_CPU_ISA_M64;
 470                 break;
 471         case PRID_IMP_20KC:
 472                 c->cputype = CPU_20KC;
 473                 c->isa_level = MIPS_CPU_ISA_M64;
 474                 break;
 475         case PRID_IMP_24K:
 476                 c->cputype = CPU_24K;
 477                 c->isa_level = MIPS_CPU_ISA_M32;
 478                 break;
 479         case PRID_IMP_25KF:
 480                 c->cputype = CPU_25KF;
 481                 c->isa_level = MIPS_CPU_ISA_M64;
 482                 /* Probe for L2 cache */
 483                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 484                 break;
 485         }
 486 }
 487
 488 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 489 {
 490         decode_config1(c);
 491         switch (c->processor_id & 0xff00) {
 492         case PRID_IMP_AU1_REV1:
 493         case PRID_IMP_AU1_REV2:
 494                 switch ((c->processor_id >> 24) & 0xff) {
 495                 case 0:
 496                         c->cputype = CPU_AU1000;
 497                         break;
 498                 case 1:
 499                         c->cputype = CPU_AU1500;
 500                         break;
 501                 case 2:
 502                         c->cputype = CPU_AU1100;
 503                         break;
 504                 case 3:
 505                         c->cputype = CPU_AU1550;
 506                         break;
 507                 case 4:
 508                         c->cputype = CPU_AU1200;
 509                         break;
 510                 default:
 511                         panic("Unknown Au Core!");
 512                         break;
 513                 }
 514                 c->isa_level = MIPS_CPU_ISA_M32;
 515                 break;
 516         }
 517 }
 518
 519 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 520 {
 521         decode_config1(c);
 522         switch (c->processor_id & 0xff00) {
 523         case PRID_IMP_SB1:
 524                 c->cputype = CPU_SB1;
 525                 c->isa_level = MIPS_CPU_ISA_M64;
 526                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 527                              MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 528                              MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
 529                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 530 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
 531                 /* FPU in pass1 is known to have issues. */
 532                 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 533 #endif
 534                 break;
 535         }
 536 }
 537
 538 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 539 {
 540         decode_config1(c);
 541         switch (c->processor_id & 0xff00) {
 542         case PRID_IMP_SR71000:
 543                 c->cputype = CPU_SR71000;
 544                 c->isa_level = MIPS_CPU_ISA_M64;
 545                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 546                              MIPS_CPU_4KTLB | MIPS_CPU_FPU |
 547                              MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
 548                 c->scache.ways = 8;
 549                 c->tlbsize = 64;
 550                 break;
 551         }
 552 }
 553
 554 __init void cpu_probe(void)
 555 {
 556         struct cpuinfo_mips *c = &current_cpu_data;
 557
 558         c->processor_id = PRID_IMP_UNKNOWN;
 559         c->fpu_id       = FPIR_IMP_NONE;
 560         c->cputype      = CPU_UNKNOWN;
 561
 562         c->processor_id = read_c0_prid();
 563         switch (c->processor_id & 0xff0000) {
 564         case PRID_COMP_LEGACY:
 565                 cpu_probe_legacy(c);
 566                 break;
 567         case PRID_COMP_MIPS:
 568                 cpu_probe_mips(c);
 569                 break;
 570         case PRID_COMP_ALCHEMY:
 571                 cpu_probe_alchemy(c);
 572                 break;
 573         case PRID_COMP_SIBYTE:
 574                 cpu_probe_sibyte(c);
 575                 break;
 576
 577         case PRID_COMP_SANDCRAFT:
 578                 cpu_probe_sandcraft(c);
 579                 break;
 580         default:
 581                 c->cputype = CPU_UNKNOWN;
 582         }
 583         if (c->options & MIPS_CPU_FPU)
 584                 c->fpu_id = cpu_get_fpu_id();
 585 }
 586
 587 __init void cpu_report(void)
 588 {
 589         struct cpuinfo_mips *c = &current_cpu_data;
 590
 591         printk("CPU revision is: %08x\n", c->processor_id);
 592         if (c->options & MIPS_CPU_FPU)
 593                 printk("FPU revision is: %08x\n", c->fpu_id);
 594 }