2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait)(void) = NULL;
34 static void r3081_wait(void)
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
40 static void r39xx_wait(void)
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
48 extern void r4k_wait(void);
51 * This variant is preferable as it allows testing need_resched and going to
52 * sleep depending on the outcome atomically. Unfortunately the "It is
53 * implementation-dependent whether the pipeline restarts when a non-enabled
54 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
55 * using this version a gamble.
57 static void r4k_wait_irqoff(void)
61 __asm__(" .set mips3 \n"
68 * The RM7000 variant has to handle erratum 38. The workaround is to not
69 * have any pending stores when the WAIT instruction is executed.
71 static void rm7k_wait_irqoff(void)
81 " mtc0 $1, $12 # stalls until W stage \n"
83 " mtc0 $1, $12 # stalls until W stage \n"
88 /* The Au1xxx wait is available only if using 32khz counter or
89 * external timer source, but specifically not CP0 Counter. */
92 static void au1k_wait(void)
94 /* using the wait instruction makes CP0 counter unusable */
95 __asm__(" .set mips3 \n"
96 " cache 0x14, 0(%0) \n"
97 " cache 0x14, 32(%0) \n"
106 : : "r" (au1k_wait));
109 static int __initdata nowait = 0;
111 static int __init wait_disable(char *s)
118 __setup("nowait", wait_disable);
120 void __init check_wait(void)
122 struct cpuinfo_mips *c = ¤t_cpu_data;
125 printk("Wait instruction disabled.\n");
129 switch (c->cputype) {
132 cpu_wait = r3081_wait;
135 cpu_wait = r39xx_wait;
138 /* case CPU_R4300: */
156 cpu_wait = rm7k_wait_irqoff;
163 if (read_c0_config7() & MIPS_CONF7_WII)
164 cpu_wait = r4k_wait_irqoff;
169 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
170 cpu_wait = r4k_wait_irqoff;
174 cpu_wait = r4k_wait_irqoff;
184 cpu_wait = au1k_wait;
188 * WAIT on Rev1.0 has E1, E2, E3 and E16.
189 * WAIT on Rev2.0 and Rev3.0 has E16.
190 * Rev3.1 WAIT is nop, why bother
192 if ((c->processor_id & 0xff) <= 0x64)
196 * Another rev is incremeting c0_count at a reduced clock
197 * rate while in WAIT mode. So we basically have the choice
198 * between using the cp0 timer as clocksource or avoiding
199 * the WAIT instruction. Until more details are known,
200 * disable the use of WAIT for 20Kc entirely.
205 if ((c->processor_id & 0x00ff) >= 0x40)
213 static inline void check_errata(void)
215 struct cpuinfo_mips *c = ¤t_cpu_data;
217 switch (c->cputype) {
220 * Erratum "RPS May Cause Incorrect Instruction Execution"
221 * This code only handles VPE0, any SMP/SMTC/RTOS code
222 * making use of VPE1 will be responsable for that VPE.
224 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
225 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
232 void __init check_bugs32(void)
238 * Probe whether cpu has config register by trying to play with
239 * alternate cache bit and see whether it matters.
240 * It's used by cpu_probe to distinguish between R3000A and R3081.
242 static inline int cpu_has_confreg(void)
244 #ifdef CONFIG_CPU_R3000
245 extern unsigned long r3k_cache_size(unsigned long);
246 unsigned long size1, size2;
247 unsigned long cfg = read_c0_conf();
249 size1 = r3k_cache_size(ST0_ISC);
250 write_c0_conf(cfg ^ R30XX_CONF_AC);
251 size2 = r3k_cache_size(ST0_ISC);
253 return size1 != size2;
260 * Get the FPU Implementation/Revision.
262 static inline unsigned long cpu_get_fpu_id(void)
264 unsigned long tmp, fpu_id;
266 tmp = read_c0_status();
268 fpu_id = read_32bit_cp1_register(CP1_REVISION);
269 write_c0_status(tmp);
274 * Check the CPU has an FPU the official way.
276 static inline int __cpu_has_fpu(void)
278 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
281 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
284 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
286 switch (c->processor_id & 0xff00) {
288 c->cputype = CPU_R2000;
289 c->isa_level = MIPS_CPU_ISA_I;
290 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
293 c->options |= MIPS_CPU_FPU;
297 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
298 if (cpu_has_confreg())
299 c->cputype = CPU_R3081E;
301 c->cputype = CPU_R3000A;
303 c->cputype = CPU_R3000;
304 c->isa_level = MIPS_CPU_ISA_I;
305 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
308 c->options |= MIPS_CPU_FPU;
312 if (read_c0_config() & CONF_SC) {
313 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
314 c->cputype = CPU_R4400PC;
316 c->cputype = CPU_R4000PC;
318 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
319 c->cputype = CPU_R4400SC;
321 c->cputype = CPU_R4000SC;
324 c->isa_level = MIPS_CPU_ISA_III;
325 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
326 MIPS_CPU_WATCH | MIPS_CPU_VCE |
330 case PRID_IMP_VR41XX:
331 switch (c->processor_id & 0xf0) {
332 case PRID_REV_VR4111:
333 c->cputype = CPU_VR4111;
335 case PRID_REV_VR4121:
336 c->cputype = CPU_VR4121;
338 case PRID_REV_VR4122:
339 if ((c->processor_id & 0xf) < 0x3)
340 c->cputype = CPU_VR4122;
342 c->cputype = CPU_VR4181A;
344 case PRID_REV_VR4130:
345 if ((c->processor_id & 0xf) < 0x4)
346 c->cputype = CPU_VR4131;
348 c->cputype = CPU_VR4133;
351 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
352 c->cputype = CPU_VR41XX;
355 c->isa_level = MIPS_CPU_ISA_III;
356 c->options = R4K_OPTS;
360 c->cputype = CPU_R4300;
361 c->isa_level = MIPS_CPU_ISA_III;
362 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
367 c->cputype = CPU_R4600;
368 c->isa_level = MIPS_CPU_ISA_III;
369 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
376 * This processor doesn't have an MMU, so it's not
377 * "real easy" to run Linux on it. It is left purely
378 * for documentation. Commented out because it shares
379 * it's c0_prid id number with the TX3900.
381 c->cputype = CPU_R4650;
382 c->isa_level = MIPS_CPU_ISA_III;
383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
388 c->isa_level = MIPS_CPU_ISA_I;
389 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
391 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
392 c->cputype = CPU_TX3927;
395 switch (c->processor_id & 0xff) {
396 case PRID_REV_TX3912:
397 c->cputype = CPU_TX3912;
400 case PRID_REV_TX3922:
401 c->cputype = CPU_TX3922;
405 c->cputype = CPU_UNKNOWN;
411 c->cputype = CPU_R4700;
412 c->isa_level = MIPS_CPU_ISA_III;
413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
418 c->cputype = CPU_TX49XX;
419 c->isa_level = MIPS_CPU_ISA_III;
420 c->options = R4K_OPTS | MIPS_CPU_LLSC;
421 if (!(c->processor_id & 0x08))
422 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
426 c->cputype = CPU_R5000;
427 c->isa_level = MIPS_CPU_ISA_IV;
428 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
433 c->cputype = CPU_R5432;
434 c->isa_level = MIPS_CPU_ISA_IV;
435 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
436 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
440 c->cputype = CPU_R5500;
441 c->isa_level = MIPS_CPU_ISA_IV;
442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
446 case PRID_IMP_NEVADA:
447 c->cputype = CPU_NEVADA;
448 c->isa_level = MIPS_CPU_ISA_IV;
449 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
450 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
454 c->cputype = CPU_R6000;
455 c->isa_level = MIPS_CPU_ISA_II;
456 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
460 case PRID_IMP_R6000A:
461 c->cputype = CPU_R6000A;
462 c->isa_level = MIPS_CPU_ISA_II;
463 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
467 case PRID_IMP_RM7000:
468 c->cputype = CPU_RM7000;
469 c->isa_level = MIPS_CPU_ISA_IV;
470 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
473 * Undocumented RM7000: Bit 29 in the info register of
474 * the RM7000 v2.0 indicates if the TLB has 48 or 64
477 * 29 1 => 64 entry JTLB
480 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
482 case PRID_IMP_RM9000:
483 c->cputype = CPU_RM9000;
484 c->isa_level = MIPS_CPU_ISA_IV;
485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
488 * Bit 29 in the info register of the RM9000
489 * indicates if the TLB has 48 or 64 entries.
491 * 29 1 => 64 entry JTLB
494 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
497 c->cputype = CPU_R8000;
498 c->isa_level = MIPS_CPU_ISA_IV;
499 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
500 MIPS_CPU_FPU | MIPS_CPU_32FPR |
502 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
504 case PRID_IMP_R10000:
505 c->cputype = CPU_R10000;
506 c->isa_level = MIPS_CPU_ISA_IV;
507 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
508 MIPS_CPU_FPU | MIPS_CPU_32FPR |
509 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
513 case PRID_IMP_R12000:
514 c->cputype = CPU_R12000;
515 c->isa_level = MIPS_CPU_ISA_IV;
516 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
517 MIPS_CPU_FPU | MIPS_CPU_32FPR |
518 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
522 case PRID_IMP_R14000:
523 c->cputype = CPU_R14000;
524 c->isa_level = MIPS_CPU_ISA_IV;
525 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
526 MIPS_CPU_FPU | MIPS_CPU_32FPR |
527 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
531 case PRID_IMP_LOONGSON2:
532 c->cputype = CPU_LOONGSON2;
533 c->isa_level = MIPS_CPU_ISA_III;
534 c->options = R4K_OPTS |
535 MIPS_CPU_FPU | MIPS_CPU_LLSC |
542 static char unknown_isa[] __cpuinitdata = KERN_ERR \
543 "Unsupported ISA type, c0.config0: %d.";
545 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
547 unsigned int config0;
550 config0 = read_c0_config();
552 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
553 c->options |= MIPS_CPU_TLB;
554 isa = (config0 & MIPS_CONF_AT) >> 13;
557 switch ((config0 & MIPS_CONF_AR) >> 10) {
559 c->isa_level = MIPS_CPU_ISA_M32R1;
562 c->isa_level = MIPS_CPU_ISA_M32R2;
569 switch ((config0 & MIPS_CONF_AR) >> 10) {
571 c->isa_level = MIPS_CPU_ISA_M64R1;
574 c->isa_level = MIPS_CPU_ISA_M64R2;
584 return config0 & MIPS_CONF_M;
587 panic(unknown_isa, config0);
590 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
592 unsigned int config1;
594 config1 = read_c0_config1();
596 if (config1 & MIPS_CONF1_MD)
597 c->ases |= MIPS_ASE_MDMX;
598 if (config1 & MIPS_CONF1_WR)
599 c->options |= MIPS_CPU_WATCH;
600 if (config1 & MIPS_CONF1_CA)
601 c->ases |= MIPS_ASE_MIPS16;
602 if (config1 & MIPS_CONF1_EP)
603 c->options |= MIPS_CPU_EJTAG;
604 if (config1 & MIPS_CONF1_FP) {
605 c->options |= MIPS_CPU_FPU;
606 c->options |= MIPS_CPU_32FPR;
609 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
611 return config1 & MIPS_CONF_M;
614 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
616 unsigned int config2;
618 config2 = read_c0_config2();
620 if (config2 & MIPS_CONF2_SL)
621 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
623 return config2 & MIPS_CONF_M;
626 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
628 unsigned int config3;
630 config3 = read_c0_config3();
632 if (config3 & MIPS_CONF3_SM)
633 c->ases |= MIPS_ASE_SMARTMIPS;
634 if (config3 & MIPS_CONF3_DSP)
635 c->ases |= MIPS_ASE_DSP;
636 if (config3 & MIPS_CONF3_VINT)
637 c->options |= MIPS_CPU_VINT;
638 if (config3 & MIPS_CONF3_VEIC)
639 c->options |= MIPS_CPU_VEIC;
640 if (config3 & MIPS_CONF3_MT)
641 c->ases |= MIPS_ASE_MIPSMT;
642 if (config3 & MIPS_CONF3_ULRI)
643 c->options |= MIPS_CPU_ULRI;
645 return config3 & MIPS_CONF_M;
648 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
650 /* MIPS32 or MIPS64 compliant CPU. */
651 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
654 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
656 /* Read Config registers. */
657 if (!decode_config0(c))
658 return; /* actually worth a panic() */
659 if (!decode_config1(c))
661 if (!decode_config2(c))
663 if (!decode_config3(c))
667 #ifdef CONFIG_CPU_MIPSR2
668 extern void spram_config(void);
670 static inline void spram_config(void) {}
673 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
676 switch (c->processor_id & 0xff00) {
678 c->cputype = CPU_4KC;
681 c->cputype = CPU_4KEC;
683 case PRID_IMP_4KECR2:
684 c->cputype = CPU_4KEC;
688 c->cputype = CPU_4KSC;
691 c->cputype = CPU_5KC;
694 c->cputype = CPU_20KC;
698 c->cputype = CPU_24K;
701 c->cputype = CPU_25KF;
704 c->cputype = CPU_34K;
707 c->cputype = CPU_74K;
710 c->cputype = CPU_1004K;
717 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
720 switch (c->processor_id & 0xff00) {
721 case PRID_IMP_AU1_REV1:
722 case PRID_IMP_AU1_REV2:
723 switch ((c->processor_id >> 24) & 0xff) {
725 c->cputype = CPU_AU1000;
728 c->cputype = CPU_AU1500;
731 c->cputype = CPU_AU1100;
734 c->cputype = CPU_AU1550;
737 c->cputype = CPU_AU1200;
738 if (2 == (c->processor_id & 0xff))
739 c->cputype = CPU_AU1250;
742 c->cputype = CPU_AU1210;
745 panic("Unknown Au Core!");
752 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
756 switch (c->processor_id & 0xff00) {
758 c->cputype = CPU_SB1;
759 /* FPU in pass1 is known to have issues. */
760 if ((c->processor_id & 0xff) < 0x02)
761 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
764 c->cputype = CPU_SB1A;
769 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
772 switch (c->processor_id & 0xff00) {
773 case PRID_IMP_SR71000:
774 c->cputype = CPU_SR71000;
781 static inline void cpu_probe_nxp(struct cpuinfo_mips *c)
784 switch (c->processor_id & 0xff00) {
785 case PRID_IMP_PR4450:
786 c->cputype = CPU_PR4450;
787 c->isa_level = MIPS_CPU_ISA_M32R1;
790 panic("Unknown NXP Core!"); /* REVISIT: die? */
796 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
799 switch (c->processor_id & 0xff00) {
800 case PRID_IMP_BCM3302:
801 c->cputype = CPU_BCM3302;
803 case PRID_IMP_BCM4710:
804 c->cputype = CPU_BCM4710;
807 c->cputype = CPU_UNKNOWN;
812 const char *__cpu_name[NR_CPUS];
817 static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
819 const char *name = NULL;
821 switch (c->cputype) {
822 case CPU_UNKNOWN: name = "unknown"; break;
823 case CPU_R2000: name = "R2000"; break;
824 case CPU_R3000: name = "R3000"; break;
825 case CPU_R3000A: name = "R3000A"; break;
826 case CPU_R3041: name = "R3041"; break;
827 case CPU_R3051: name = "R3051"; break;
828 case CPU_R3052: name = "R3052"; break;
829 case CPU_R3081: name = "R3081"; break;
830 case CPU_R3081E: name = "R3081E"; break;
831 case CPU_R4000PC: name = "R4000PC"; break;
832 case CPU_R4000SC: name = "R4000SC"; break;
833 case CPU_R4000MC: name = "R4000MC"; break;
834 case CPU_R4200: name = "R4200"; break;
835 case CPU_R4400PC: name = "R4400PC"; break;
836 case CPU_R4400SC: name = "R4400SC"; break;
837 case CPU_R4400MC: name = "R4400MC"; break;
838 case CPU_R4600: name = "R4600"; break;
839 case CPU_R6000: name = "R6000"; break;
840 case CPU_R6000A: name = "R6000A"; break;
841 case CPU_R8000: name = "R8000"; break;
842 case CPU_R10000: name = "R10000"; break;
843 case CPU_R12000: name = "R12000"; break;
844 case CPU_R14000: name = "R14000"; break;
845 case CPU_R4300: name = "R4300"; break;
846 case CPU_R4650: name = "R4650"; break;
847 case CPU_R4700: name = "R4700"; break;
848 case CPU_R5000: name = "R5000"; break;
849 case CPU_R5000A: name = "R5000A"; break;
850 case CPU_R4640: name = "R4640"; break;
851 case CPU_NEVADA: name = "Nevada"; break;
852 case CPU_RM7000: name = "RM7000"; break;
853 case CPU_RM9000: name = "RM9000"; break;
854 case CPU_R5432: name = "R5432"; break;
855 case CPU_4KC: name = "MIPS 4Kc"; break;
856 case CPU_5KC: name = "MIPS 5Kc"; break;
857 case CPU_R4310: name = "R4310"; break;
858 case CPU_SB1: name = "SiByte SB1"; break;
859 case CPU_SB1A: name = "SiByte SB1A"; break;
860 case CPU_TX3912: name = "TX3912"; break;
861 case CPU_TX3922: name = "TX3922"; break;
862 case CPU_TX3927: name = "TX3927"; break;
863 case CPU_AU1000: name = "Au1000"; break;
864 case CPU_AU1500: name = "Au1500"; break;
865 case CPU_AU1100: name = "Au1100"; break;
866 case CPU_AU1550: name = "Au1550"; break;
867 case CPU_AU1200: name = "Au1200"; break;
868 case CPU_AU1210: name = "Au1210"; break;
869 case CPU_AU1250: name = "Au1250"; break;
870 case CPU_4KEC: name = "MIPS 4KEc"; break;
871 case CPU_4KSC: name = "MIPS 4KSc"; break;
872 case CPU_VR41XX: name = "NEC Vr41xx"; break;
873 case CPU_R5500: name = "R5500"; break;
874 case CPU_TX49XX: name = "TX49xx"; break;
875 case CPU_20KC: name = "MIPS 20Kc"; break;
876 case CPU_24K: name = "MIPS 24K"; break;
877 case CPU_25KF: name = "MIPS 25Kf"; break;
878 case CPU_34K: name = "MIPS 34K"; break;
879 case CPU_1004K: name = "MIPS 1004K"; break;
880 case CPU_74K: name = "MIPS 74K"; break;
881 case CPU_VR4111: name = "NEC VR4111"; break;
882 case CPU_VR4121: name = "NEC VR4121"; break;
883 case CPU_VR4122: name = "NEC VR4122"; break;
884 case CPU_VR4131: name = "NEC VR4131"; break;
885 case CPU_VR4133: name = "NEC VR4133"; break;
886 case CPU_VR4181: name = "NEC VR4181"; break;
887 case CPU_VR4181A: name = "NEC VR4181A"; break;
888 case CPU_SR71000: name = "Sandcraft SR71000"; break;
889 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
890 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
891 case CPU_PR4450: name = "Philips PR4450"; break;
892 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
900 __cpuinit void cpu_probe(void)
902 struct cpuinfo_mips *c = ¤t_cpu_data;
903 unsigned int cpu = smp_processor_id();
905 c->processor_id = PRID_IMP_UNKNOWN;
906 c->fpu_id = FPIR_IMP_NONE;
907 c->cputype = CPU_UNKNOWN;
909 c->processor_id = read_c0_prid();
910 switch (c->processor_id & 0xff0000) {
911 case PRID_COMP_LEGACY:
917 case PRID_COMP_ALCHEMY:
918 cpu_probe_alchemy(c);
920 case PRID_COMP_SIBYTE:
923 case PRID_COMP_BROADCOM:
924 cpu_probe_broadcom(c);
926 case PRID_COMP_SANDCRAFT:
927 cpu_probe_sandcraft(c);
933 c->cputype = CPU_UNKNOWN;
937 * Platform code can force the cpu type to optimize code
938 * generation. In that case be sure the cpu type is correctly
939 * manually setup otherwise it could trigger some nasty bugs.
941 BUG_ON(current_cpu_type() != c->cputype);
943 if (c->options & MIPS_CPU_FPU) {
944 c->fpu_id = cpu_get_fpu_id();
946 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
947 c->isa_level == MIPS_CPU_ISA_M32R2 ||
948 c->isa_level == MIPS_CPU_ISA_M64R1 ||
949 c->isa_level == MIPS_CPU_ISA_M64R2) {
950 if (c->fpu_id & MIPS_FPIR_3D)
951 c->ases |= MIPS_ASE_MIPS3D;
955 __cpu_name[cpu] = cpu_to_name(c);
958 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
963 __cpuinit void cpu_report(void)
965 struct cpuinfo_mips *c = ¤t_cpu_data;
967 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
968 c->processor_id, cpu_name_string());
969 if (c->options & MIPS_CPU_FPU)
970 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);