2 * linux/arch/mips/kernel/irq_txx9.c
4 * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
5 * linux/arch/mips/tx4927/common/tx4927_irq.c,
6 * linux/arch/mips/tx4938/common/irq.c
8 * Copyright 2001, 2003-2005 MontaVista Software Inc.
9 * Author: MontaVista Software, Inc.
10 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/types.h>
21 #include <asm/txx9irq.h>
38 /* IRCER : Int. Control Enable */
39 #define TXx9_IRCER_ICE 0x00000001
41 /* IRCR : Int. Control */
42 #define TXx9_IRCR_LOW 0x00000000
43 #define TXx9_IRCR_HIGH 0x00000001
44 #define TXx9_IRCR_DOWN 0x00000002
45 #define TXx9_IRCR_UP 0x00000003
46 #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
48 /* IRSCR : Int. Status Control */
49 #define TXx9_IRSCR_EIClrE 0x00000100
50 #define TXx9_IRSCR_EIClr_MASK 0x0000000f
52 /* IRCSR : Int. Current Status */
53 #define TXx9_IRCSR_IF 0x00010000
54 #define TXx9_IRCSR_ILV_MASK 0x00000700
55 #define TXx9_IRCSR_IVL_MASK 0x0000001f
60 static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
65 } txx9irq[TXx9_MAX_IR] __read_mostly;
67 static void txx9_irq_unmask(unsigned int irq)
69 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
70 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
71 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
73 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
74 | (txx9irq[irq_nr].level << ofs),
76 #ifdef CONFIG_CPU_TX39XX
78 __raw_writel(0, &txx9_ircptr->imr);
79 __raw_writel(irc_elevel, &txx9_ircptr->imr);
83 static inline void txx9_irq_mask(unsigned int irq)
85 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
86 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
87 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
89 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
90 | (irc_dlevel << ofs),
92 #ifdef CONFIG_CPU_TX39XX
94 __raw_writel(0, &txx9_ircptr->imr);
95 __raw_writel(irc_elevel, &txx9_ircptr->imr);
96 /* flush write buffer */
97 __raw_readl(&txx9_ircptr->ssr);
103 static void txx9_irq_mask_ack(unsigned int irq)
105 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
108 if (TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)) {
109 /* clear edge detection */
110 u32 cr = __raw_readl(&txx9_ircptr->cr[irq_nr / 8]);
111 cr = (cr >> ((irq_nr & (8 - 1)) * 2)) & 3;
112 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr,
117 static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
119 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
125 if (flow_type & IRQF_TRIGGER_PROBE)
127 switch (flow_type & IRQF_TRIGGER_MASK) {
128 case IRQF_TRIGGER_RISING: mode = TXx9_IRCR_UP; break;
129 case IRQF_TRIGGER_FALLING: mode = TXx9_IRCR_DOWN; break;
130 case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH; break;
131 case IRQF_TRIGGER_LOW: mode = TXx9_IRCR_LOW; break;
135 crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
136 cr = __raw_readl(crp);
137 ofs = (irq_nr & (8 - 1)) * 2;
139 cr |= (mode & 0x3) << ofs;
140 __raw_writel(cr, crp);
141 txx9irq[irq_nr].mode = mode;
145 static struct irq_chip txx9_irq_chip = {
147 .ack = txx9_irq_mask_ack,
148 .mask = txx9_irq_mask,
149 .mask_ack = txx9_irq_mask_ack,
150 .unmask = txx9_irq_unmask,
151 .set_type = txx9_irq_set_type,
154 void __init txx9_irq_init(unsigned long baseaddr)
158 txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
159 for (i = 0; i < TXx9_MAX_IR; i++) {
160 txx9irq[i].level = 4; /* middle level */
161 txx9irq[i].mode = TXx9_IRCR_LOW;
162 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
163 &txx9_irq_chip, handle_level_irq);
166 /* mask all IRC interrupts */
167 __raw_writel(0, &txx9_ircptr->imr);
168 for (i = 0; i < 8; i++)
169 __raw_writel(0, &txx9_ircptr->ilr[i]);
170 /* setup IRC interrupt mode (Low Active) */
171 for (i = 0; i < 2; i++)
172 __raw_writel(0, &txx9_ircptr->cr[i]);
173 /* enable interrupt control */
174 __raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
175 __raw_writel(irc_elevel, &txx9_ircptr->imr);
178 int __init txx9_irq_set_pri(int irc_irq, int new_pri)
182 if ((unsigned int)irc_irq >= TXx9_MAX_IR)
184 old_pri = txx9irq[irc_irq].level;
185 txx9irq[irc_irq].level = new_pri;
191 u32 csr = __raw_readl(&txx9_ircptr->csr);
193 if (likely(!(csr & TXx9_IRCSR_IF)))
194 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));