2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
30 #include <asm/module.h>
31 #include <asm/pgtable.h>
32 #include <asm/ptrace.h>
33 #include <asm/sections.h>
34 #include <asm/system.h>
35 #include <asm/tlbdebug.h>
36 #include <asm/traps.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/watch.h>
40 #include <asm/types.h>
42 extern asmlinkage void handle_tlbm(void);
43 extern asmlinkage void handle_tlbl(void);
44 extern asmlinkage void handle_tlbs(void);
45 extern asmlinkage void handle_adel(void);
46 extern asmlinkage void handle_ades(void);
47 extern asmlinkage void handle_ibe(void);
48 extern asmlinkage void handle_dbe(void);
49 extern asmlinkage void handle_sys(void);
50 extern asmlinkage void handle_bp(void);
51 extern asmlinkage void handle_ri(void);
52 extern asmlinkage void handle_cpu(void);
53 extern asmlinkage void handle_ov(void);
54 extern asmlinkage void handle_tr(void);
55 extern asmlinkage void handle_fpe(void);
56 extern asmlinkage void handle_mdmx(void);
57 extern asmlinkage void handle_watch(void);
58 extern asmlinkage void handle_dsp(void);
59 extern asmlinkage void handle_mcheck(void);
60 extern asmlinkage void handle_reserved(void);
62 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
63 struct mips_fpu_soft_struct *ctx);
65 void (*board_be_init)(void);
66 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
69 * These constant is for searching for possible module text segments.
70 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
72 #define MODULE_RANGE (8*1024*1024)
75 * This routine abuses get_user()/put_user() to reference pointers
76 * with at least a bit of error checking ...
78 void show_stack(struct task_struct *task, unsigned long *sp)
80 const int field = 2 * sizeof(unsigned long);
85 if (task && task != current)
86 sp = (unsigned long *) task->thread.reg29;
88 sp = (unsigned long *) &sp;
93 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
94 if (i && ((i % (64 / field)) == 0))
101 if (__get_user(stackdata, sp++)) {
102 printk(" (Bad stack address)");
106 printk(" %0*lx", field, stackdata);
112 void show_trace(struct task_struct *task, unsigned long *stack)
114 const int field = 2 * sizeof(unsigned long);
118 if (task && task != current)
119 stack = (unsigned long *) task->thread.reg29;
121 stack = (unsigned long *) &stack;
124 printk("Call Trace:");
125 #ifdef CONFIG_KALLSYMS
128 while (!kstack_end(stack)) {
130 if (__kernel_text_address(addr)) {
131 printk(" [<%0*lx>] ", field, addr);
132 print_symbol("%s\n", addr);
139 * The architecture-independent dump_stack generator
141 void dump_stack(void)
145 show_trace(current, &stack);
148 EXPORT_SYMBOL(dump_stack);
150 void show_code(unsigned int *pc)
156 for(i = -3 ; i < 6 ; i++) {
158 if (__get_user(insn, pc + i)) {
159 printk(" (Bad address in epc)\n");
162 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
166 void show_regs(struct pt_regs *regs)
168 const int field = 2 * sizeof(unsigned long);
169 unsigned int cause = regs->cp0_cause;
172 printk("Cpu %d\n", smp_processor_id());
175 * Saved main processor registers
177 for (i = 0; i < 32; ) {
181 printk(" %0*lx", field, 0UL);
182 else if (i == 26 || i == 27)
183 printk(" %*s", field, "");
185 printk(" %0*lx", field, regs->regs[i]);
192 printk("Hi : %0*lx\n", field, regs->hi);
193 printk("Lo : %0*lx\n", field, regs->lo);
196 * Saved cp0 registers
198 printk("epc : %0*lx ", field, regs->cp0_epc);
199 print_symbol("%s ", regs->cp0_epc);
200 printk(" %s\n", print_tainted());
201 printk("ra : %0*lx ", field, regs->regs[31]);
202 print_symbol("%s\n", regs->regs[31]);
204 printk("Status: %08x ", (uint32_t) regs->cp0_status);
206 if (regs->cp0_status & ST0_KX)
208 if (regs->cp0_status & ST0_SX)
210 if (regs->cp0_status & ST0_UX)
212 switch (regs->cp0_status & ST0_KSU) {
217 printk("SUPERVISOR ");
226 if (regs->cp0_status & ST0_ERL)
228 if (regs->cp0_status & ST0_EXL)
230 if (regs->cp0_status & ST0_IE)
234 printk("Cause : %08x\n", cause);
236 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
237 if (1 <= cause && cause <= 5)
238 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
240 printk("PrId : %08x\n", read_c0_prid());
243 void show_registers(struct pt_regs *regs)
247 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
248 current->comm, current->pid, current_thread_info(), current);
249 show_stack(current, (long *) regs->regs[29]);
250 show_trace(current, (long *) regs->regs[29]);
251 show_code((unsigned int *) regs->cp0_epc);
255 static DEFINE_SPINLOCK(die_lock);
257 NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs,
258 const char * file, const char * func,
261 static int die_counter;
264 spin_lock_irq(&die_lock);
267 printk(" in %s:%s, line %ld", file, func, line);
268 printk("[#%d]:\n", ++die_counter);
269 show_registers(regs);
270 spin_unlock_irq(&die_lock);
274 void __die_if_kernel(const char * str, struct pt_regs * regs,
275 const char * file, const char * func, unsigned long line)
277 if (!user_mode(regs))
278 __die(str, regs, file, func, line);
281 extern const struct exception_table_entry __start___dbe_table[];
282 extern const struct exception_table_entry __stop___dbe_table[];
284 void __declare_dbe_table(void)
286 __asm__ __volatile__(
287 ".section\t__dbe_table,\"a\"\n\t"
292 /* Given an address, look for it in the exception tables. */
293 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
295 const struct exception_table_entry *e;
297 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
299 e = search_module_dbetables(addr);
303 asmlinkage void do_be(struct pt_regs *regs)
305 const int field = 2 * sizeof(unsigned long);
306 const struct exception_table_entry *fixup = NULL;
307 int data = regs->cp0_cause & 4;
308 int action = MIPS_BE_FATAL;
310 /* XXX For now. Fixme, this searches the wrong table ... */
311 if (data && !user_mode(regs))
312 fixup = search_dbe_tables(exception_epc(regs));
315 action = MIPS_BE_FIXUP;
317 if (board_be_handler)
318 action = board_be_handler(regs, fixup != 0);
321 case MIPS_BE_DISCARD:
325 regs->cp0_epc = fixup->nextinsn;
334 * Assume it would be too dangerous to continue ...
336 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
337 data ? "Data" : "Instruction",
338 field, regs->cp0_epc, field, regs->regs[31]);
339 die_if_kernel("Oops", regs);
340 force_sig(SIGBUS, current);
343 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
345 unsigned int __user *epc;
347 epc = (unsigned int __user *) regs->cp0_epc +
348 ((regs->cp0_cause & CAUSEF_BD) != 0);
349 if (!get_user(*opcode, epc))
352 force_sig(SIGSEGV, current);
360 #define OPCODE 0xfc000000
361 #define BASE 0x03e00000
362 #define RT 0x001f0000
363 #define OFFSET 0x0000ffff
364 #define LL 0xc0000000
365 #define SC 0xe0000000
366 #define SPEC3 0x7c000000
367 #define RD 0x0000f800
368 #define FUNC 0x0000003f
369 #define RDHWR 0x0000003b
372 * The ll_bit is cleared by r*_switch.S
375 unsigned long ll_bit;
377 static struct task_struct *ll_task = NULL;
379 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
381 unsigned long value, __user *vaddr;
386 * analyse the ll instruction that just caused a ri exception
387 * and put the referenced address to addr.
390 /* sign extend offset */
391 offset = opcode & OFFSET;
395 vaddr = (unsigned long __user *)
396 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
398 if ((unsigned long)vaddr & 3) {
402 if (get_user(value, vaddr)) {
409 if (ll_task == NULL || ll_task == current) {
418 compute_return_epc(regs);
420 regs->regs[(opcode & RT) >> 16] = value;
425 force_sig(signal, current);
428 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
430 unsigned long __user *vaddr;
436 * analyse the sc instruction that just caused a ri exception
437 * and put the referenced address to addr.
440 /* sign extend offset */
441 offset = opcode & OFFSET;
445 vaddr = (unsigned long __user *)
446 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
447 reg = (opcode & RT) >> 16;
449 if ((unsigned long)vaddr & 3) {
456 if (ll_bit == 0 || ll_task != current) {
457 compute_return_epc(regs);
465 if (put_user(regs->regs[reg], vaddr)) {
470 compute_return_epc(regs);
476 force_sig(signal, current);
480 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
481 * opcodes are supposed to result in coprocessor unusable exceptions if
482 * executed on ll/sc-less processors. That's the theory. In practice a
483 * few processors such as NEC's VR4100 throw reserved instruction exceptions
484 * instead, so we're doing the emulation thing in both exception handlers.
486 static inline int simulate_llsc(struct pt_regs *regs)
490 if (unlikely(get_insn_opcode(regs, &opcode)))
493 if ((opcode & OPCODE) == LL) {
494 simulate_ll(regs, opcode);
497 if ((opcode & OPCODE) == SC) {
498 simulate_sc(regs, opcode);
502 return -EFAULT; /* Strange things going on ... */
506 * Simulate trapping 'rdhwr' instructions to provide user accessible
507 * registers not implemented in hardware. The only current use of this
508 * is the thread area pointer.
510 static inline int simulate_rdhwr(struct pt_regs *regs)
512 struct thread_info *ti = current->thread_info;
515 if (unlikely(get_insn_opcode(regs, &opcode)))
518 if (unlikely(compute_return_epc(regs)))
521 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
522 int rd = (opcode & RD) >> 11;
523 int rt = (opcode & RT) >> 16;
526 regs->regs[rt] = ti->tp_value;
536 asmlinkage void do_ov(struct pt_regs *regs)
540 info.si_code = FPE_INTOVF;
541 info.si_signo = SIGFPE;
543 info.si_addr = (void __user *) regs->cp0_epc;
544 force_sig_info(SIGFPE, &info, current);
548 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
550 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
552 if (fcr31 & FPU_CSR_UNI_X) {
557 #ifdef CONFIG_PREEMPT
558 if (!is_fpu_owner()) {
559 /* We might lose fpu before disabling preempt... */
561 BUG_ON(!used_math());
566 * Unimplemented operation exception. If we've got the full
567 * software emulator on-board, let's use it...
569 * Force FPU to dump state into task/thread context. We're
570 * moving a lot of data here for what is probably a single
571 * instruction, but the alternative is to pre-decode the FP
572 * register operands before invoking the emulator, which seems
573 * a bit extreme for what should be an infrequent event.
576 /* Ensure 'resume' not overwrite saved fp context again. */
581 /* Run the emulator */
582 sig = fpu_emulator_cop1Handler (0, regs,
583 ¤t->thread.fpu.soft);
587 own_fpu(); /* Using the FPU again. */
589 * We can't allow the emulated instruction to leave any of
590 * the cause bit set in $fcr31.
592 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
594 /* Restore the hardware register state */
599 /* If something went wrong, signal */
601 force_sig(sig, current);
606 force_sig(SIGFPE, current);
609 asmlinkage void do_bp(struct pt_regs *regs)
611 unsigned int opcode, bcode;
614 die_if_kernel("Break instruction in kernel code", regs);
616 if (get_insn_opcode(regs, &opcode))
620 * There is the ancient bug in the MIPS assemblers that the break
621 * code starts left to bit 16 instead to bit 6 in the opcode.
622 * Gas is bug-compatible, but not always, grrr...
623 * We handle both cases with a simple heuristics. --macro
625 bcode = ((opcode >> 6) & ((1 << 20) - 1));
626 if (bcode < (1 << 10))
630 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
631 * insns, even for break codes that indicate arithmetic failures.
633 * But should we continue the brokenness??? --macro
636 case BRK_OVERFLOW << 10:
637 case BRK_DIVZERO << 10:
638 if (bcode == (BRK_DIVZERO << 10))
639 info.si_code = FPE_INTDIV;
641 info.si_code = FPE_INTOVF;
642 info.si_signo = SIGFPE;
644 info.si_addr = (void __user *) regs->cp0_epc;
645 force_sig_info(SIGFPE, &info, current);
648 force_sig(SIGTRAP, current);
652 asmlinkage void do_tr(struct pt_regs *regs)
654 unsigned int opcode, tcode = 0;
657 die_if_kernel("Trap instruction in kernel code", regs);
659 if (get_insn_opcode(regs, &opcode))
662 /* Immediate versions don't provide a code. */
663 if (!(opcode & OPCODE))
664 tcode = ((opcode >> 6) & ((1 << 10) - 1));
667 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
668 * insns, even for trap codes that indicate arithmetic failures.
670 * But should we continue the brokenness??? --macro
675 if (tcode == BRK_DIVZERO)
676 info.si_code = FPE_INTDIV;
678 info.si_code = FPE_INTOVF;
679 info.si_signo = SIGFPE;
681 info.si_addr = (void __user *) regs->cp0_epc;
682 force_sig_info(SIGFPE, &info, current);
685 force_sig(SIGTRAP, current);
689 asmlinkage void do_ri(struct pt_regs *regs)
691 die_if_kernel("Reserved instruction in kernel code", regs);
694 if (!simulate_llsc(regs))
697 if (!simulate_rdhwr(regs))
700 force_sig(SIGILL, current);
703 asmlinkage void do_cpu(struct pt_regs *regs)
707 die_if_kernel("do_cpu invoked from kernel context!", regs);
709 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
714 if (!simulate_llsc(regs))
717 if (!simulate_rdhwr(regs))
726 if (used_math()) { /* Using the FPU again. */
728 } else { /* First time FPU user. */
736 int sig = fpu_emulator_cop1Handler(0, regs,
737 ¤t->thread.fpu.soft);
739 force_sig(sig, current);
749 force_sig(SIGILL, current);
752 asmlinkage void do_mdmx(struct pt_regs *regs)
754 force_sig(SIGILL, current);
757 asmlinkage void do_watch(struct pt_regs *regs)
760 * We use the watch exception where available to detect stack
765 panic("Caught WATCH exception - probably caused by stack overflow.");
768 asmlinkage void do_mcheck(struct pt_regs *regs)
773 * Some chips may have other causes of machine check (e.g. SB1
776 panic("Caught Machine Check exception - %scaused by multiple "
777 "matching entries in the TLB.",
778 (regs->cp0_status & ST0_TS) ? "" : "not ");
781 asmlinkage void do_dsp(struct pt_regs *regs)
784 panic("Unexpected DSP exception\n");
786 force_sig(SIGILL, current);
789 asmlinkage void do_reserved(struct pt_regs *regs)
792 * Game over - no way to handle this if it ever occurs. Most probably
793 * caused by a new unknown cpu type or after another deadly
794 * hard/software error.
797 panic("Caught reserved exception %ld - should not happen.",
798 (regs->cp0_cause & 0x7f) >> 2);
802 * Some MIPS CPUs can enable/disable for cache parity detection, but do
805 static inline void parity_protection_init(void)
807 switch (current_cpu_data.cputype) {
810 write_c0_ecc(0x80000000);
811 back_to_back_c0_hazard();
812 /* Set the PE bit (bit 31) in the c0_errctl register. */
813 printk(KERN_INFO "Cache parity protection %sabled\n",
814 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
818 /* Clear the DE bit (bit 16) in the c0_status register. */
819 printk(KERN_INFO "Enable cache parity protection for "
820 "MIPS 20KC/25KF CPUs.\n");
821 clear_c0_status(ST0_DE);
828 asmlinkage void cache_parity_error(void)
830 const int field = 2 * sizeof(unsigned long);
831 unsigned int reg_val;
833 /* For the moment, report the problem and hang. */
834 printk("Cache error exception:\n");
835 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
836 reg_val = read_c0_cacheerr();
837 printk("c0_cacheerr == %08x\n", reg_val);
839 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
840 reg_val & (1<<30) ? "secondary" : "primary",
841 reg_val & (1<<31) ? "data" : "insn");
842 printk("Error bits: %s%s%s%s%s%s%s\n",
843 reg_val & (1<<29) ? "ED " : "",
844 reg_val & (1<<28) ? "ET " : "",
845 reg_val & (1<<26) ? "EE " : "",
846 reg_val & (1<<25) ? "EB " : "",
847 reg_val & (1<<24) ? "EI " : "",
848 reg_val & (1<<23) ? "E1 " : "",
849 reg_val & (1<<22) ? "E0 " : "");
850 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
852 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
853 if (reg_val & (1<<22))
854 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
856 if (reg_val & (1<<23))
857 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
860 panic("Can't handle the cache error!");
864 * SDBBP EJTAG debug exception handler.
865 * We skip the instruction and return to the next instruction.
867 void ejtag_exception_handler(struct pt_regs *regs)
869 const int field = 2 * sizeof(unsigned long);
870 unsigned long depc, old_epc;
873 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
874 depc = read_c0_depc();
875 debug = read_c0_debug();
876 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
877 if (debug & 0x80000000) {
879 * In branch delay slot.
880 * We cheat a little bit here and use EPC to calculate the
881 * debug return address (DEPC). EPC is restored after the
884 old_epc = regs->cp0_epc;
885 regs->cp0_epc = depc;
886 __compute_return_epc(regs);
887 depc = regs->cp0_epc;
888 regs->cp0_epc = old_epc;
894 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
895 write_c0_debug(debug | 0x100);
900 * NMI exception handler.
902 void nmi_exception_handler(struct pt_regs *regs)
904 printk("NMI taken!!!!\n");
909 unsigned long exception_handlers[32];
912 * As a side effect of the way this is implemented we're limited
913 * to interrupt handlers in the address range from
914 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
916 void *set_except_vector(int n, void *addr)
918 unsigned long handler = (unsigned long) addr;
919 unsigned long old_handler = exception_handlers[n];
921 exception_handlers[n] = handler;
922 if (n == 0 && cpu_has_divec) {
923 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
924 (0x03ffffff & (handler >> 2));
925 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
927 return (void *)old_handler;
931 * This is used by native signal handling
933 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
934 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
936 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
937 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
939 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
940 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
942 static inline void signal_init(void)
945 save_fp_context = _save_fp_context;
946 restore_fp_context = _restore_fp_context;
948 save_fp_context = fpu_emulator_save_context;
949 restore_fp_context = fpu_emulator_restore_context;
953 #ifdef CONFIG_MIPS32_COMPAT
956 * This is used by 32-bit signal stuff on the 64-bit kernel
958 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
959 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
961 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
962 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
964 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
965 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
967 static inline void signal32_init(void)
970 save_fp_context32 = _save_fp_context32;
971 restore_fp_context32 = _restore_fp_context32;
973 save_fp_context32 = fpu_emulator_save_context32;
974 restore_fp_context32 = fpu_emulator_restore_context32;
979 extern void cpu_cache_init(void);
980 extern void tlb_init(void);
982 void __init per_cpu_trap_init(void)
984 unsigned int cpu = smp_processor_id();
985 unsigned int status_set = ST0_CU0;
988 * Disable coprocessors and select 32-bit or 64-bit addressing
989 * and the 16/32 or 32/32 FPR register model. Reset the BEV
990 * flag that some firmware may have left set and the TS bit (for
991 * IP27). Set XX for ISA IV code to work.
994 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
996 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
997 status_set |= ST0_XX;
998 change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1002 set_c0_status(ST0_MX);
1005 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1006 * interrupt processing overhead. Use it where available.
1009 set_c0_cause(CAUSEF_IV);
1011 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1012 TLBMISS_HANDLER_SETUP();
1014 atomic_inc(&init_mm.mm_count);
1015 current->active_mm = &init_mm;
1016 BUG_ON(current->mm);
1017 enter_lazy_tlb(&init_mm, current);
1023 void __init trap_init(void)
1025 extern char except_vec3_generic, except_vec3_r4000;
1026 extern char except_vec_ejtag_debug;
1027 extern char except_vec4;
1030 per_cpu_trap_init();
1033 * Copy the generic exception handlers to their final destination.
1034 * This will be overriden later as suitable for a particular
1037 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1040 * Setup default vectors
1042 for (i = 0; i <= 31; i++)
1043 set_except_vector(i, handle_reserved);
1046 * Copy the EJTAG debug exception vector handler code to it's final
1050 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
1053 * Only some CPUs have the watch exceptions.
1056 set_except_vector(23, handle_watch);
1059 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1060 * interrupt processing overhead. Use it where available.
1063 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
1066 * Some CPUs can enable/disable for cache parity detection, but does
1067 * it different ways.
1069 parity_protection_init();
1072 * The Data Bus Errors / Instruction Bus Errors are signaled
1073 * by external hardware. Therefore these two exceptions
1074 * may have board specific handlers.
1079 set_except_vector(1, handle_tlbm);
1080 set_except_vector(2, handle_tlbl);
1081 set_except_vector(3, handle_tlbs);
1083 set_except_vector(4, handle_adel);
1084 set_except_vector(5, handle_ades);
1086 set_except_vector(6, handle_ibe);
1087 set_except_vector(7, handle_dbe);
1089 set_except_vector(8, handle_sys);
1090 set_except_vector(9, handle_bp);
1091 set_except_vector(10, handle_ri);
1092 set_except_vector(11, handle_cpu);
1093 set_except_vector(12, handle_ov);
1094 set_except_vector(13, handle_tr);
1096 if (current_cpu_data.cputype == CPU_R6000 ||
1097 current_cpu_data.cputype == CPU_R6000A) {
1099 * The R6000 is the only R-series CPU that features a machine
1100 * check exception (similar to the R4000 cache error) and
1101 * unaligned ldc1/sdc1 exception. The handlers have not been
1102 * written yet. Well, anyway there is no R6000 machine on the
1103 * current list of targets for Linux/MIPS.
1104 * (Duh, crap, there is someone with a triple R6k machine)
1106 //set_except_vector(14, handle_mc);
1107 //set_except_vector(15, handle_ndc);
1110 if (cpu_has_fpu && !cpu_has_nofpuex)
1111 set_except_vector(15, handle_fpe);
1113 set_except_vector(22, handle_mdmx);
1116 set_except_vector(24, handle_mcheck);
1119 set_except_vector(26, handle_dsp);
1122 /* Special exception: R4[04]00 uses also the divec space. */
1123 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1124 else if (cpu_has_4kex)
1125 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1127 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1130 #ifdef CONFIG_MIPS32_COMPAT
1134 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);