2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
45 extern asmlinkage void handle_tlbm(void);
46 extern asmlinkage void handle_tlbl(void);
47 extern asmlinkage void handle_tlbs(void);
48 extern asmlinkage void handle_adel(void);
49 extern asmlinkage void handle_ades(void);
50 extern asmlinkage void handle_ibe(void);
51 extern asmlinkage void handle_dbe(void);
52 extern asmlinkage void handle_sys(void);
53 extern asmlinkage void handle_bp(void);
54 extern asmlinkage void handle_ri(void);
55 extern asmlinkage void handle_cpu(void);
56 extern asmlinkage void handle_ov(void);
57 extern asmlinkage void handle_tr(void);
58 extern asmlinkage void handle_fpe(void);
59 extern asmlinkage void handle_mdmx(void);
60 extern asmlinkage void handle_watch(void);
61 extern asmlinkage void handle_mt(void);
62 extern asmlinkage void handle_dsp(void);
63 extern asmlinkage void handle_mcheck(void);
64 extern asmlinkage void handle_reserved(void);
66 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
67 struct mips_fpu_soft_struct *ctx);
69 void (*board_be_init)(void);
70 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
71 void (*board_nmi_handler_setup)(void);
72 void (*board_ejtag_handler_setup)(void);
73 void (*board_bind_eic_interrupt)(int irq, int regset);
76 * These constant is for searching for possible module text segments.
77 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
79 #define MODULE_RANGE (8*1024*1024)
82 * This routine abuses get_user()/put_user() to reference pointers
83 * with at least a bit of error checking ...
85 void show_stack(struct task_struct *task, unsigned long *sp)
87 const int field = 2 * sizeof(unsigned long);
92 if (task && task != current)
93 sp = (unsigned long *) task->thread.reg29;
95 sp = (unsigned long *) &sp;
100 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
101 if (i && ((i % (64 / field)) == 0))
108 if (__get_user(stackdata, sp++)) {
109 printk(" (Bad stack address)");
113 printk(" %0*lx", field, stackdata);
119 void show_trace(struct task_struct *task, unsigned long *stack)
121 const int field = 2 * sizeof(unsigned long);
125 if (task && task != current)
126 stack = (unsigned long *) task->thread.reg29;
128 stack = (unsigned long *) &stack;
131 printk("Call Trace:");
132 #ifdef CONFIG_KALLSYMS
135 while (!kstack_end(stack)) {
137 if (__kernel_text_address(addr)) {
138 printk(" [<%0*lx>] ", field, addr);
139 print_symbol("%s\n", addr);
146 * The architecture-independent dump_stack generator
148 void dump_stack(void)
152 show_trace(current, &stack);
155 EXPORT_SYMBOL(dump_stack);
157 void show_code(unsigned int *pc)
163 for(i = -3 ; i < 6 ; i++) {
165 if (__get_user(insn, pc + i)) {
166 printk(" (Bad address in epc)\n");
169 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
173 void show_regs(struct pt_regs *regs)
175 const int field = 2 * sizeof(unsigned long);
176 unsigned int cause = regs->cp0_cause;
179 printk("Cpu %d\n", smp_processor_id());
182 * Saved main processor registers
184 for (i = 0; i < 32; ) {
188 printk(" %0*lx", field, 0UL);
189 else if (i == 26 || i == 27)
190 printk(" %*s", field, "");
192 printk(" %0*lx", field, regs->regs[i]);
199 printk("Hi : %0*lx\n", field, regs->hi);
200 printk("Lo : %0*lx\n", field, regs->lo);
203 * Saved cp0 registers
205 printk("epc : %0*lx ", field, regs->cp0_epc);
206 print_symbol("%s ", regs->cp0_epc);
207 printk(" %s\n", print_tainted());
208 printk("ra : %0*lx ", field, regs->regs[31]);
209 print_symbol("%s\n", regs->regs[31]);
211 printk("Status: %08x ", (uint32_t) regs->cp0_status);
213 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
214 if (regs->cp0_status & ST0_KUO)
216 if (regs->cp0_status & ST0_IEO)
218 if (regs->cp0_status & ST0_KUP)
220 if (regs->cp0_status & ST0_IEP)
222 if (regs->cp0_status & ST0_KUC)
224 if (regs->cp0_status & ST0_IEC)
227 if (regs->cp0_status & ST0_KX)
229 if (regs->cp0_status & ST0_SX)
231 if (regs->cp0_status & ST0_UX)
233 switch (regs->cp0_status & ST0_KSU) {
238 printk("SUPERVISOR ");
247 if (regs->cp0_status & ST0_ERL)
249 if (regs->cp0_status & ST0_EXL)
251 if (regs->cp0_status & ST0_IE)
256 printk("Cause : %08x\n", cause);
258 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
259 if (1 <= cause && cause <= 5)
260 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
262 printk("PrId : %08x\n", read_c0_prid());
265 void show_registers(struct pt_regs *regs)
269 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
270 current->comm, current->pid, current_thread_info(), current);
271 show_stack(current, (long *) regs->regs[29]);
272 show_trace(current, (long *) regs->regs[29]);
273 show_code((unsigned int *) regs->cp0_epc);
277 static DEFINE_SPINLOCK(die_lock);
279 NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs,
280 const char * file, const char * func,
283 static int die_counter;
286 spin_lock_irq(&die_lock);
289 printk(" in %s:%s, line %ld", file, func, line);
290 printk("[#%d]:\n", ++die_counter);
291 show_registers(regs);
292 spin_unlock_irq(&die_lock);
296 void __die_if_kernel(const char * str, struct pt_regs * regs,
297 const char * file, const char * func, unsigned long line)
299 if (!user_mode(regs))
300 __die(str, regs, file, func, line);
303 extern const struct exception_table_entry __start___dbe_table[];
304 extern const struct exception_table_entry __stop___dbe_table[];
306 void __declare_dbe_table(void)
308 __asm__ __volatile__(
309 ".section\t__dbe_table,\"a\"\n\t"
314 /* Given an address, look for it in the exception tables. */
315 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
317 const struct exception_table_entry *e;
319 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
321 e = search_module_dbetables(addr);
325 asmlinkage void do_be(struct pt_regs *regs)
327 const int field = 2 * sizeof(unsigned long);
328 const struct exception_table_entry *fixup = NULL;
329 int data = regs->cp0_cause & 4;
330 int action = MIPS_BE_FATAL;
332 /* XXX For now. Fixme, this searches the wrong table ... */
333 if (data && !user_mode(regs))
334 fixup = search_dbe_tables(exception_epc(regs));
337 action = MIPS_BE_FIXUP;
339 if (board_be_handler)
340 action = board_be_handler(regs, fixup != 0);
343 case MIPS_BE_DISCARD:
347 regs->cp0_epc = fixup->nextinsn;
356 * Assume it would be too dangerous to continue ...
358 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
359 data ? "Data" : "Instruction",
360 field, regs->cp0_epc, field, regs->regs[31]);
361 die_if_kernel("Oops", regs);
362 force_sig(SIGBUS, current);
365 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
367 unsigned int __user *epc;
369 epc = (unsigned int __user *) regs->cp0_epc +
370 ((regs->cp0_cause & CAUSEF_BD) != 0);
371 if (!get_user(*opcode, epc))
374 force_sig(SIGSEGV, current);
382 #define OPCODE 0xfc000000
383 #define BASE 0x03e00000
384 #define RT 0x001f0000
385 #define OFFSET 0x0000ffff
386 #define LL 0xc0000000
387 #define SC 0xe0000000
388 #define SPEC3 0x7c000000
389 #define RD 0x0000f800
390 #define FUNC 0x0000003f
391 #define RDHWR 0x0000003b
394 * The ll_bit is cleared by r*_switch.S
397 unsigned long ll_bit;
399 static struct task_struct *ll_task = NULL;
401 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
403 unsigned long value, __user *vaddr;
408 * analyse the ll instruction that just caused a ri exception
409 * and put the referenced address to addr.
412 /* sign extend offset */
413 offset = opcode & OFFSET;
417 vaddr = (unsigned long __user *)
418 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
420 if ((unsigned long)vaddr & 3) {
424 if (get_user(value, vaddr)) {
431 if (ll_task == NULL || ll_task == current) {
440 compute_return_epc(regs);
442 regs->regs[(opcode & RT) >> 16] = value;
447 force_sig(signal, current);
450 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
452 unsigned long __user *vaddr;
458 * analyse the sc instruction that just caused a ri exception
459 * and put the referenced address to addr.
462 /* sign extend offset */
463 offset = opcode & OFFSET;
467 vaddr = (unsigned long __user *)
468 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
469 reg = (opcode & RT) >> 16;
471 if ((unsigned long)vaddr & 3) {
478 if (ll_bit == 0 || ll_task != current) {
479 compute_return_epc(regs);
487 if (put_user(regs->regs[reg], vaddr)) {
492 compute_return_epc(regs);
498 force_sig(signal, current);
502 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
503 * opcodes are supposed to result in coprocessor unusable exceptions if
504 * executed on ll/sc-less processors. That's the theory. In practice a
505 * few processors such as NEC's VR4100 throw reserved instruction exceptions
506 * instead, so we're doing the emulation thing in both exception handlers.
508 static inline int simulate_llsc(struct pt_regs *regs)
512 if (unlikely(get_insn_opcode(regs, &opcode)))
515 if ((opcode & OPCODE) == LL) {
516 simulate_ll(regs, opcode);
519 if ((opcode & OPCODE) == SC) {
520 simulate_sc(regs, opcode);
524 return -EFAULT; /* Strange things going on ... */
528 * Simulate trapping 'rdhwr' instructions to provide user accessible
529 * registers not implemented in hardware. The only current use of this
530 * is the thread area pointer.
532 static inline int simulate_rdhwr(struct pt_regs *regs)
534 struct thread_info *ti = current->thread_info;
537 if (unlikely(get_insn_opcode(regs, &opcode)))
540 if (unlikely(compute_return_epc(regs)))
543 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
544 int rd = (opcode & RD) >> 11;
545 int rt = (opcode & RT) >> 16;
548 regs->regs[rt] = ti->tp_value;
558 asmlinkage void do_ov(struct pt_regs *regs)
562 info.si_code = FPE_INTOVF;
563 info.si_signo = SIGFPE;
565 info.si_addr = (void __user *) regs->cp0_epc;
566 force_sig_info(SIGFPE, &info, current);
570 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
572 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
574 if (fcr31 & FPU_CSR_UNI_X) {
579 #ifdef CONFIG_PREEMPT
580 if (!is_fpu_owner()) {
581 /* We might lose fpu before disabling preempt... */
583 BUG_ON(!used_math());
588 * Unimplemented operation exception. If we've got the full
589 * software emulator on-board, let's use it...
591 * Force FPU to dump state into task/thread context. We're
592 * moving a lot of data here for what is probably a single
593 * instruction, but the alternative is to pre-decode the FP
594 * register operands before invoking the emulator, which seems
595 * a bit extreme for what should be an infrequent event.
598 /* Ensure 'resume' not overwrite saved fp context again. */
603 /* Run the emulator */
604 sig = fpu_emulator_cop1Handler (0, regs,
605 ¤t->thread.fpu.soft);
609 own_fpu(); /* Using the FPU again. */
611 * We can't allow the emulated instruction to leave any of
612 * the cause bit set in $fcr31.
614 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
616 /* Restore the hardware register state */
621 /* If something went wrong, signal */
623 force_sig(sig, current);
628 force_sig(SIGFPE, current);
631 asmlinkage void do_bp(struct pt_regs *regs)
633 unsigned int opcode, bcode;
636 die_if_kernel("Break instruction in kernel code", regs);
638 if (get_insn_opcode(regs, &opcode))
642 * There is the ancient bug in the MIPS assemblers that the break
643 * code starts left to bit 16 instead to bit 6 in the opcode.
644 * Gas is bug-compatible, but not always, grrr...
645 * We handle both cases with a simple heuristics. --macro
647 bcode = ((opcode >> 6) & ((1 << 20) - 1));
648 if (bcode < (1 << 10))
652 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
653 * insns, even for break codes that indicate arithmetic failures.
655 * But should we continue the brokenness??? --macro
658 case BRK_OVERFLOW << 10:
659 case BRK_DIVZERO << 10:
660 if (bcode == (BRK_DIVZERO << 10))
661 info.si_code = FPE_INTDIV;
663 info.si_code = FPE_INTOVF;
664 info.si_signo = SIGFPE;
666 info.si_addr = (void __user *) regs->cp0_epc;
667 force_sig_info(SIGFPE, &info, current);
670 force_sig(SIGTRAP, current);
674 asmlinkage void do_tr(struct pt_regs *regs)
676 unsigned int opcode, tcode = 0;
679 die_if_kernel("Trap instruction in kernel code", regs);
681 if (get_insn_opcode(regs, &opcode))
684 /* Immediate versions don't provide a code. */
685 if (!(opcode & OPCODE))
686 tcode = ((opcode >> 6) & ((1 << 10) - 1));
689 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
690 * insns, even for trap codes that indicate arithmetic failures.
692 * But should we continue the brokenness??? --macro
697 if (tcode == BRK_DIVZERO)
698 info.si_code = FPE_INTDIV;
700 info.si_code = FPE_INTOVF;
701 info.si_signo = SIGFPE;
703 info.si_addr = (void __user *) regs->cp0_epc;
704 force_sig_info(SIGFPE, &info, current);
707 force_sig(SIGTRAP, current);
711 asmlinkage void do_ri(struct pt_regs *regs)
713 die_if_kernel("Reserved instruction in kernel code", regs);
716 if (!simulate_llsc(regs))
719 if (!simulate_rdhwr(regs))
722 force_sig(SIGILL, current);
725 asmlinkage void do_cpu(struct pt_regs *regs)
729 die_if_kernel("do_cpu invoked from kernel context!", regs);
731 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
736 if (!simulate_llsc(regs))
739 if (!simulate_rdhwr(regs))
748 if (used_math()) { /* Using the FPU again. */
750 } else { /* First time FPU user. */
758 int sig = fpu_emulator_cop1Handler(0, regs,
759 ¤t->thread.fpu.soft);
761 force_sig(sig, current);
771 force_sig(SIGILL, current);
774 asmlinkage void do_mdmx(struct pt_regs *regs)
776 force_sig(SIGILL, current);
779 asmlinkage void do_watch(struct pt_regs *regs)
782 * We use the watch exception where available to detect stack
787 panic("Caught WATCH exception - probably caused by stack overflow.");
790 asmlinkage void do_mcheck(struct pt_regs *regs)
795 * Some chips may have other causes of machine check (e.g. SB1
798 panic("Caught Machine Check exception - %scaused by multiple "
799 "matching entries in the TLB.",
800 (regs->cp0_status & ST0_TS) ? "" : "not ");
803 asmlinkage void do_mt(struct pt_regs *regs)
805 die_if_kernel("MIPS MT Thread exception in kernel", regs);
807 force_sig(SIGILL, current);
811 asmlinkage void do_dsp(struct pt_regs *regs)
814 panic("Unexpected DSP exception\n");
816 force_sig(SIGILL, current);
819 asmlinkage void do_reserved(struct pt_regs *regs)
822 * Game over - no way to handle this if it ever occurs. Most probably
823 * caused by a new unknown cpu type or after another deadly
824 * hard/software error.
827 panic("Caught reserved exception %ld - should not happen.",
828 (regs->cp0_cause & 0x7f) >> 2);
831 asmlinkage void do_default_vi(struct pt_regs *regs)
834 panic("Caught unexpected vectored interrupt.");
838 * Some MIPS CPUs can enable/disable for cache parity detection, but do
841 static inline void parity_protection_init(void)
843 switch (current_cpu_data.cputype) {
846 write_c0_ecc(0x80000000);
847 back_to_back_c0_hazard();
848 /* Set the PE bit (bit 31) in the c0_errctl register. */
849 printk(KERN_INFO "Cache parity protection %sabled\n",
850 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
854 /* Clear the DE bit (bit 16) in the c0_status register. */
855 printk(KERN_INFO "Enable cache parity protection for "
856 "MIPS 20KC/25KF CPUs.\n");
857 clear_c0_status(ST0_DE);
864 asmlinkage void cache_parity_error(void)
866 const int field = 2 * sizeof(unsigned long);
867 unsigned int reg_val;
869 /* For the moment, report the problem and hang. */
870 printk("Cache error exception:\n");
871 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
872 reg_val = read_c0_cacheerr();
873 printk("c0_cacheerr == %08x\n", reg_val);
875 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
876 reg_val & (1<<30) ? "secondary" : "primary",
877 reg_val & (1<<31) ? "data" : "insn");
878 printk("Error bits: %s%s%s%s%s%s%s\n",
879 reg_val & (1<<29) ? "ED " : "",
880 reg_val & (1<<28) ? "ET " : "",
881 reg_val & (1<<26) ? "EE " : "",
882 reg_val & (1<<25) ? "EB " : "",
883 reg_val & (1<<24) ? "EI " : "",
884 reg_val & (1<<23) ? "E1 " : "",
885 reg_val & (1<<22) ? "E0 " : "");
886 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
888 #if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
889 if (reg_val & (1<<22))
890 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
892 if (reg_val & (1<<23))
893 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
896 panic("Can't handle the cache error!");
900 * SDBBP EJTAG debug exception handler.
901 * We skip the instruction and return to the next instruction.
903 void ejtag_exception_handler(struct pt_regs *regs)
905 const int field = 2 * sizeof(unsigned long);
906 unsigned long depc, old_epc;
909 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
910 depc = read_c0_depc();
911 debug = read_c0_debug();
912 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
913 if (debug & 0x80000000) {
915 * In branch delay slot.
916 * We cheat a little bit here and use EPC to calculate the
917 * debug return address (DEPC). EPC is restored after the
920 old_epc = regs->cp0_epc;
921 regs->cp0_epc = depc;
922 __compute_return_epc(regs);
923 depc = regs->cp0_epc;
924 regs->cp0_epc = old_epc;
930 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
931 write_c0_debug(debug | 0x100);
936 * NMI exception handler.
938 void nmi_exception_handler(struct pt_regs *regs)
940 printk("NMI taken!!!!\n");
945 #define VECTORSPACING 0x100 /* for EI/VI mode */
948 unsigned long exception_handlers[32];
949 unsigned long vi_handlers[64];
952 * As a side effect of the way this is implemented we're limited
953 * to interrupt handlers in the address range from
954 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
956 void *set_except_vector(int n, void *addr)
958 unsigned long handler = (unsigned long) addr;
959 unsigned long old_handler = exception_handlers[n];
961 exception_handlers[n] = handler;
962 if (n == 0 && cpu_has_divec) {
963 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
964 (0x03ffffff & (handler >> 2));
965 flush_icache_range(ebase + 0x200, ebase + 0x204);
967 return (void *)old_handler;
970 #ifdef CONFIG_CPU_MIPSR2
972 * Shadow register allocation
976 /* MIPSR2 shadow register sets */
977 struct shadow_registers {
978 spinlock_t sr_lock; /* */
979 int sr_supported; /* Number of shadow register sets supported */
980 int sr_allocated; /* Bitmap of allocated shadow registers */
983 void mips_srs_init(void)
985 #ifdef CONFIG_CPU_MIPSR2_SRS
986 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
987 printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported);
989 shadow_registers.sr_supported = 1;
991 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
992 spin_lock_init(&shadow_registers.sr_lock);
995 int mips_srs_max(void)
997 return shadow_registers.sr_supported;
1000 int mips_srs_alloc (void)
1002 struct shadow_registers *sr = &shadow_registers;
1003 unsigned long flags;
1006 spin_lock_irqsave(&sr->sr_lock, flags);
1008 for (set = 0; set < sr->sr_supported; set++) {
1009 if ((sr->sr_allocated & (1 << set)) == 0) {
1010 sr->sr_allocated |= 1 << set;
1011 spin_unlock_irqrestore(&sr->sr_lock, flags);
1016 /* None available */
1017 spin_unlock_irqrestore(&sr->sr_lock, flags);
1021 void mips_srs_free (int set)
1023 struct shadow_registers *sr = &shadow_registers;
1024 unsigned long flags;
1026 spin_lock_irqsave(&sr->sr_lock, flags);
1027 sr->sr_allocated &= ~(1 << set);
1028 spin_unlock_irqrestore(&sr->sr_lock, flags);
1031 void *set_vi_srs_handler (int n, void *addr, int srs)
1033 unsigned long handler;
1034 unsigned long old_handler = vi_handlers[n];
1038 if (!cpu_has_veic && !cpu_has_vint)
1042 handler = (unsigned long) do_default_vi;
1046 handler = (unsigned long) addr;
1047 vi_handlers[n] = (unsigned long) addr;
1049 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1051 if (srs >= mips_srs_max())
1052 panic("Shadow register set %d not supported", srs);
1055 if (board_bind_eic_interrupt)
1056 board_bind_eic_interrupt (n, srs);
1058 else if (cpu_has_vint) {
1059 /* SRSMap is only defined if shadow sets are implemented */
1060 if (mips_srs_max() > 1)
1061 change_c0_srsmap (0xf << n*4, srs << n*4);
1066 * If no shadow set is selected then use the default handler
1067 * that does normal register saving and a standard interrupt exit
1070 extern char except_vec_vi, except_vec_vi_lui;
1071 extern char except_vec_vi_ori, except_vec_vi_end;
1072 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1073 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1074 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1076 if (handler_len > VECTORSPACING) {
1078 * Sigh... panicing won't help as the console
1079 * is probably not configured :(
1081 panic ("VECTORSPACING too small");
1084 memcpy (b, &except_vec_vi, handler_len);
1085 w = (u32 *)(b + lui_offset);
1086 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1087 w = (u32 *)(b + ori_offset);
1088 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1089 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1093 * In other cases jump directly to the interrupt handler
1095 * It is the handlers responsibility to save registers if required
1096 * (eg hi/lo) and return from the exception using "eret"
1099 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1101 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1104 return (void *)old_handler;
1107 void *set_vi_handler (int n, void *addr)
1109 return set_vi_srs_handler (n, addr, 0);
1114 * This is used by native signal handling
1116 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1117 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1119 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1120 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1122 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1123 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1125 static inline void signal_init(void)
1128 save_fp_context = _save_fp_context;
1129 restore_fp_context = _restore_fp_context;
1131 save_fp_context = fpu_emulator_save_context;
1132 restore_fp_context = fpu_emulator_restore_context;
1136 #ifdef CONFIG_MIPS32_COMPAT
1139 * This is used by 32-bit signal stuff on the 64-bit kernel
1141 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1142 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1144 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1145 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1147 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1148 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1150 static inline void signal32_init(void)
1153 save_fp_context32 = _save_fp_context32;
1154 restore_fp_context32 = _restore_fp_context32;
1156 save_fp_context32 = fpu_emulator_save_context32;
1157 restore_fp_context32 = fpu_emulator_restore_context32;
1162 extern void cpu_cache_init(void);
1163 extern void tlb_init(void);
1164 extern void flush_tlb_handlers(void);
1166 void __init per_cpu_trap_init(void)
1168 unsigned int cpu = smp_processor_id();
1169 unsigned int status_set = ST0_CU0;
1172 * Disable coprocessors and select 32-bit or 64-bit addressing
1173 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1174 * flag that some firmware may have left set and the TS bit (for
1175 * IP27). Set XX for ISA IV code to work.
1178 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1180 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1181 status_set |= ST0_XX;
1182 change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1186 set_c0_status(ST0_MX);
1188 #ifdef CONFIG_CPU_MIPSR2
1189 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1193 * Interrupt handling.
1195 if (cpu_has_veic || cpu_has_vint) {
1196 write_c0_ebase (ebase);
1197 /* Setting vector spacing enables EI/VI mode */
1198 change_c0_intctl (0x3e0, VECTORSPACING);
1200 if (cpu_has_divec) {
1201 if (cpu_has_mipsmt) {
1202 unsigned int vpflags = dvpe();
1203 set_c0_cause(CAUSEF_IV);
1206 set_c0_cause(CAUSEF_IV);
1209 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1210 TLBMISS_HANDLER_SETUP();
1212 atomic_inc(&init_mm.mm_count);
1213 current->active_mm = &init_mm;
1214 BUG_ON(current->mm);
1215 enter_lazy_tlb(&init_mm, current);
1221 /* Install CPU exception handler */
1222 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1224 memcpy((void *)(ebase + offset), addr, size);
1225 flush_icache_range(ebase + offset, ebase + offset + size);
1228 /* Install uncached CPU exception handler */
1229 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1232 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1235 unsigned long uncached_ebase = TO_UNCAC(ebase);
1238 memcpy((void *)(uncached_ebase + offset), addr, size);
1241 void __init trap_init(void)
1243 extern char except_vec3_generic, except_vec3_r4000;
1244 extern char except_vec4;
1247 if (cpu_has_veic || cpu_has_vint)
1248 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1252 #ifdef CONFIG_CPU_MIPSR2
1256 per_cpu_trap_init();
1259 * Copy the generic exception handlers to their final destination.
1260 * This will be overriden later as suitable for a particular
1263 set_handler(0x180, &except_vec3_generic, 0x80);
1266 * Setup default vectors
1268 for (i = 0; i <= 31; i++)
1269 set_except_vector(i, handle_reserved);
1272 * Copy the EJTAG debug exception vector handler code to it's final
1275 if (cpu_has_ejtag && board_ejtag_handler_setup)
1276 board_ejtag_handler_setup ();
1279 * Only some CPUs have the watch exceptions.
1282 set_except_vector(23, handle_watch);
1285 * Initialise interrupt handlers
1287 if (cpu_has_veic || cpu_has_vint) {
1288 int nvec = cpu_has_veic ? 64 : 8;
1289 for (i = 0; i < nvec; i++)
1290 set_vi_handler (i, NULL);
1292 else if (cpu_has_divec)
1293 set_handler(0x200, &except_vec4, 0x8);
1296 * Some CPUs can enable/disable for cache parity detection, but does
1297 * it different ways.
1299 parity_protection_init();
1302 * The Data Bus Errors / Instruction Bus Errors are signaled
1303 * by external hardware. Therefore these two exceptions
1304 * may have board specific handlers.
1309 set_except_vector(1, handle_tlbm);
1310 set_except_vector(2, handle_tlbl);
1311 set_except_vector(3, handle_tlbs);
1313 set_except_vector(4, handle_adel);
1314 set_except_vector(5, handle_ades);
1316 set_except_vector(6, handle_ibe);
1317 set_except_vector(7, handle_dbe);
1319 set_except_vector(8, handle_sys);
1320 set_except_vector(9, handle_bp);
1321 set_except_vector(10, handle_ri);
1322 set_except_vector(11, handle_cpu);
1323 set_except_vector(12, handle_ov);
1324 set_except_vector(13, handle_tr);
1326 if (current_cpu_data.cputype == CPU_R6000 ||
1327 current_cpu_data.cputype == CPU_R6000A) {
1329 * The R6000 is the only R-series CPU that features a machine
1330 * check exception (similar to the R4000 cache error) and
1331 * unaligned ldc1/sdc1 exception. The handlers have not been
1332 * written yet. Well, anyway there is no R6000 machine on the
1333 * current list of targets for Linux/MIPS.
1334 * (Duh, crap, there is someone with a triple R6k machine)
1336 //set_except_vector(14, handle_mc);
1337 //set_except_vector(15, handle_ndc);
1341 if (board_nmi_handler_setup)
1342 board_nmi_handler_setup();
1344 if (cpu_has_fpu && !cpu_has_nofpuex)
1345 set_except_vector(15, handle_fpe);
1347 set_except_vector(22, handle_mdmx);
1350 set_except_vector(24, handle_mcheck);
1353 set_except_vector(25, handle_mt);
1356 set_except_vector(26, handle_dsp);
1359 /* Special exception: R4[04]00 uses also the divec space. */
1360 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1361 else if (cpu_has_4kex)
1362 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1364 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1367 #ifdef CONFIG_MIPS32_COMPAT
1371 flush_icache_range(ebase, ebase + 0x400);
1372 flush_tlb_handlers();