2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_cpu(void);
57 extern asmlinkage void handle_ov(void);
58 extern asmlinkage void handle_tr(void);
59 extern asmlinkage void handle_fpe(void);
60 extern asmlinkage void handle_mdmx(void);
61 extern asmlinkage void handle_watch(void);
62 extern asmlinkage void handle_mt(void);
63 extern asmlinkage void handle_dsp(void);
64 extern asmlinkage void handle_mcheck(void);
65 extern asmlinkage void handle_reserved(void);
67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
68 struct mips_fpu_struct *ctx);
70 void (*board_be_init)(void);
71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
72 void (*board_nmi_handler_setup)(void);
73 void (*board_ejtag_handler_setup)(void);
74 void (*board_bind_eic_interrupt)(int irq, int regset);
77 static void show_raw_backtrace(unsigned long *sp)
81 printk("Call Trace:");
82 #ifdef CONFIG_KALLSYMS
85 while (!kstack_end(sp)) {
87 if (__kernel_text_address(addr))
93 #ifdef CONFIG_KALLSYMS
94 static int raw_show_trace;
95 static int __init set_raw_show_trace(char *str)
100 __setup("raw_show_trace", set_raw_show_trace);
102 extern unsigned long unwind_stack(struct task_struct *task,
103 unsigned long **sp, unsigned long pc);
104 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
106 unsigned long *sp = (long *)regs->regs[29];
107 unsigned long pc = regs->cp0_epc;
110 if (raw_show_trace || !__kernel_text_address(pc)) {
111 show_raw_backtrace(sp);
114 printk("Call Trace:\n");
115 while (__kernel_text_address(pc)) {
117 pc = unwind_stack(task, &sp, pc);
119 pc = regs->regs[31]; /* leaf? */
125 #define show_backtrace(task, r) show_raw_backtrace((long *)(r)->regs[29]);
129 * This routine abuses get_user()/put_user() to reference pointers
130 * with at least a bit of error checking ...
132 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
134 const int field = 2 * sizeof(unsigned long);
137 unsigned long *sp = (unsigned long *)regs->regs[29];
141 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
142 if (i && ((i % (64 / field)) == 0))
149 if (__get_user(stackdata, sp++)) {
150 printk(" (Bad stack address)");
154 printk(" %0*lx", field, stackdata);
158 show_backtrace(task, regs);
161 static noinline void prepare_frametrace(struct pt_regs *regs)
163 __asm__ __volatile__(
174 : "=m" (regs->cp0_epc),
175 "=m" (regs->regs[29]), "=m" (regs->regs[31])
179 void show_stack(struct task_struct *task, unsigned long *sp)
183 regs.regs[29] = (unsigned long)sp;
187 if (task && task != current) {
188 regs.regs[29] = task->thread.reg29;
190 regs.cp0_epc = task->thread.reg31;
192 prepare_frametrace(®s);
195 show_stacktrace(task, ®s);
199 * The architecture-independent dump_stack generator
201 void dump_stack(void)
205 #ifdef CONFIG_KALLSYMS
206 if (!raw_show_trace) {
208 prepare_frametrace(®s);
209 show_backtrace(current, ®s);
213 show_raw_backtrace(&stack);
216 EXPORT_SYMBOL(dump_stack);
218 void show_code(unsigned int *pc)
224 for(i = -3 ; i < 6 ; i++) {
226 if (__get_user(insn, pc + i)) {
227 printk(" (Bad address in epc)\n");
230 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
234 void show_regs(struct pt_regs *regs)
236 const int field = 2 * sizeof(unsigned long);
237 unsigned int cause = regs->cp0_cause;
240 printk("Cpu %d\n", smp_processor_id());
243 * Saved main processor registers
245 for (i = 0; i < 32; ) {
249 printk(" %0*lx", field, 0UL);
250 else if (i == 26 || i == 27)
251 printk(" %*s", field, "");
253 printk(" %0*lx", field, regs->regs[i]);
260 printk("Hi : %0*lx\n", field, regs->hi);
261 printk("Lo : %0*lx\n", field, regs->lo);
264 * Saved cp0 registers
266 printk("epc : %0*lx ", field, regs->cp0_epc);
267 print_symbol("%s ", regs->cp0_epc);
268 printk(" %s\n", print_tainted());
269 printk("ra : %0*lx ", field, regs->regs[31]);
270 print_symbol("%s\n", regs->regs[31]);
272 printk("Status: %08x ", (uint32_t) regs->cp0_status);
274 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
275 if (regs->cp0_status & ST0_KUO)
277 if (regs->cp0_status & ST0_IEO)
279 if (regs->cp0_status & ST0_KUP)
281 if (regs->cp0_status & ST0_IEP)
283 if (regs->cp0_status & ST0_KUC)
285 if (regs->cp0_status & ST0_IEC)
288 if (regs->cp0_status & ST0_KX)
290 if (regs->cp0_status & ST0_SX)
292 if (regs->cp0_status & ST0_UX)
294 switch (regs->cp0_status & ST0_KSU) {
299 printk("SUPERVISOR ");
308 if (regs->cp0_status & ST0_ERL)
310 if (regs->cp0_status & ST0_EXL)
312 if (regs->cp0_status & ST0_IE)
317 printk("Cause : %08x\n", cause);
319 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
320 if (1 <= cause && cause <= 5)
321 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
323 printk("PrId : %08x\n", read_c0_prid());
326 void show_registers(struct pt_regs *regs)
330 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
331 current->comm, current->pid, current_thread_info(), current);
332 show_stacktrace(current, regs);
333 show_code((unsigned int *) regs->cp0_epc);
337 static DEFINE_SPINLOCK(die_lock);
339 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
341 static int die_counter;
342 #ifdef CONFIG_MIPS_MT_SMTC
343 unsigned long dvpret = dvpe();
344 #endif /* CONFIG_MIPS_MT_SMTC */
347 spin_lock_irq(&die_lock);
349 #ifdef CONFIG_MIPS_MT_SMTC
350 mips_mt_regdump(dvpret);
351 #endif /* CONFIG_MIPS_MT_SMTC */
352 printk("%s[#%d]:\n", str, ++die_counter);
353 show_registers(regs);
354 spin_unlock_irq(&die_lock);
357 panic("Fatal exception in interrupt");
360 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
362 panic("Fatal exception");
368 extern const struct exception_table_entry __start___dbe_table[];
369 extern const struct exception_table_entry __stop___dbe_table[];
371 void __declare_dbe_table(void)
373 __asm__ __volatile__(
374 ".section\t__dbe_table,\"a\"\n\t"
379 /* Given an address, look for it in the exception tables. */
380 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
382 const struct exception_table_entry *e;
384 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
386 e = search_module_dbetables(addr);
390 asmlinkage void do_be(struct pt_regs *regs)
392 const int field = 2 * sizeof(unsigned long);
393 const struct exception_table_entry *fixup = NULL;
394 int data = regs->cp0_cause & 4;
395 int action = MIPS_BE_FATAL;
397 /* XXX For now. Fixme, this searches the wrong table ... */
398 if (data && !user_mode(regs))
399 fixup = search_dbe_tables(exception_epc(regs));
402 action = MIPS_BE_FIXUP;
404 if (board_be_handler)
405 action = board_be_handler(regs, fixup != 0);
408 case MIPS_BE_DISCARD:
412 regs->cp0_epc = fixup->nextinsn;
421 * Assume it would be too dangerous to continue ...
423 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
424 data ? "Data" : "Instruction",
425 field, regs->cp0_epc, field, regs->regs[31]);
426 die_if_kernel("Oops", regs);
427 force_sig(SIGBUS, current);
430 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
432 unsigned int __user *epc;
434 epc = (unsigned int __user *) regs->cp0_epc +
435 ((regs->cp0_cause & CAUSEF_BD) != 0);
436 if (!get_user(*opcode, epc))
439 force_sig(SIGSEGV, current);
447 #define OPCODE 0xfc000000
448 #define BASE 0x03e00000
449 #define RT 0x001f0000
450 #define OFFSET 0x0000ffff
451 #define LL 0xc0000000
452 #define SC 0xe0000000
453 #define SPEC3 0x7c000000
454 #define RD 0x0000f800
455 #define FUNC 0x0000003f
456 #define RDHWR 0x0000003b
459 * The ll_bit is cleared by r*_switch.S
462 unsigned long ll_bit;
464 static struct task_struct *ll_task = NULL;
466 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
468 unsigned long value, __user *vaddr;
473 * analyse the ll instruction that just caused a ri exception
474 * and put the referenced address to addr.
477 /* sign extend offset */
478 offset = opcode & OFFSET;
482 vaddr = (unsigned long __user *)
483 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
485 if ((unsigned long)vaddr & 3) {
489 if (get_user(value, vaddr)) {
496 if (ll_task == NULL || ll_task == current) {
505 compute_return_epc(regs);
507 regs->regs[(opcode & RT) >> 16] = value;
512 force_sig(signal, current);
515 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
517 unsigned long __user *vaddr;
523 * analyse the sc instruction that just caused a ri exception
524 * and put the referenced address to addr.
527 /* sign extend offset */
528 offset = opcode & OFFSET;
532 vaddr = (unsigned long __user *)
533 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
534 reg = (opcode & RT) >> 16;
536 if ((unsigned long)vaddr & 3) {
543 if (ll_bit == 0 || ll_task != current) {
544 compute_return_epc(regs);
552 if (put_user(regs->regs[reg], vaddr)) {
557 compute_return_epc(regs);
563 force_sig(signal, current);
567 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
568 * opcodes are supposed to result in coprocessor unusable exceptions if
569 * executed on ll/sc-less processors. That's the theory. In practice a
570 * few processors such as NEC's VR4100 throw reserved instruction exceptions
571 * instead, so we're doing the emulation thing in both exception handlers.
573 static inline int simulate_llsc(struct pt_regs *regs)
577 if (unlikely(get_insn_opcode(regs, &opcode)))
580 if ((opcode & OPCODE) == LL) {
581 simulate_ll(regs, opcode);
584 if ((opcode & OPCODE) == SC) {
585 simulate_sc(regs, opcode);
589 return -EFAULT; /* Strange things going on ... */
593 * Simulate trapping 'rdhwr' instructions to provide user accessible
594 * registers not implemented in hardware. The only current use of this
595 * is the thread area pointer.
597 static inline int simulate_rdhwr(struct pt_regs *regs)
599 struct thread_info *ti = task_thread_info(current);
602 if (unlikely(get_insn_opcode(regs, &opcode)))
605 if (unlikely(compute_return_epc(regs)))
608 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
609 int rd = (opcode & RD) >> 11;
610 int rt = (opcode & RT) >> 16;
613 regs->regs[rt] = ti->tp_value;
624 asmlinkage void do_ov(struct pt_regs *regs)
628 die_if_kernel("Integer overflow", regs);
630 info.si_code = FPE_INTOVF;
631 info.si_signo = SIGFPE;
633 info.si_addr = (void __user *) regs->cp0_epc;
634 force_sig_info(SIGFPE, &info, current);
638 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
640 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
642 die_if_kernel("FP exception in kernel code", regs);
644 if (fcr31 & FPU_CSR_UNI_X) {
649 #ifdef CONFIG_PREEMPT
650 if (!is_fpu_owner()) {
651 /* We might lose fpu before disabling preempt... */
653 BUG_ON(!used_math());
658 * Unimplemented operation exception. If we've got the full
659 * software emulator on-board, let's use it...
661 * Force FPU to dump state into task/thread context. We're
662 * moving a lot of data here for what is probably a single
663 * instruction, but the alternative is to pre-decode the FP
664 * register operands before invoking the emulator, which seems
665 * a bit extreme for what should be an infrequent event.
668 /* Ensure 'resume' not overwrite saved fp context again. */
673 /* Run the emulator */
674 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu);
678 own_fpu(); /* Using the FPU again. */
680 * We can't allow the emulated instruction to leave any of
681 * the cause bit set in $fcr31.
683 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
685 /* Restore the hardware register state */
690 /* If something went wrong, signal */
692 force_sig(sig, current);
697 force_sig(SIGFPE, current);
700 asmlinkage void do_bp(struct pt_regs *regs)
702 unsigned int opcode, bcode;
705 die_if_kernel("Break instruction in kernel code", regs);
707 if (get_insn_opcode(regs, &opcode))
711 * There is the ancient bug in the MIPS assemblers that the break
712 * code starts left to bit 16 instead to bit 6 in the opcode.
713 * Gas is bug-compatible, but not always, grrr...
714 * We handle both cases with a simple heuristics. --macro
716 bcode = ((opcode >> 6) & ((1 << 20) - 1));
717 if (bcode < (1 << 10))
721 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
722 * insns, even for break codes that indicate arithmetic failures.
724 * But should we continue the brokenness??? --macro
727 case BRK_OVERFLOW << 10:
728 case BRK_DIVZERO << 10:
729 if (bcode == (BRK_DIVZERO << 10))
730 info.si_code = FPE_INTDIV;
732 info.si_code = FPE_INTOVF;
733 info.si_signo = SIGFPE;
735 info.si_addr = (void __user *) regs->cp0_epc;
736 force_sig_info(SIGFPE, &info, current);
739 force_sig(SIGTRAP, current);
743 asmlinkage void do_tr(struct pt_regs *regs)
745 unsigned int opcode, tcode = 0;
748 die_if_kernel("Trap instruction in kernel code", regs);
750 if (get_insn_opcode(regs, &opcode))
753 /* Immediate versions don't provide a code. */
754 if (!(opcode & OPCODE))
755 tcode = ((opcode >> 6) & ((1 << 10) - 1));
758 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
759 * insns, even for trap codes that indicate arithmetic failures.
761 * But should we continue the brokenness??? --macro
766 if (tcode == BRK_DIVZERO)
767 info.si_code = FPE_INTDIV;
769 info.si_code = FPE_INTOVF;
770 info.si_signo = SIGFPE;
772 info.si_addr = (void __user *) regs->cp0_epc;
773 force_sig_info(SIGFPE, &info, current);
776 force_sig(SIGTRAP, current);
780 asmlinkage void do_ri(struct pt_regs *regs)
782 die_if_kernel("Reserved instruction in kernel code", regs);
785 if (!simulate_llsc(regs))
788 if (!simulate_rdhwr(regs))
791 force_sig(SIGILL, current);
794 asmlinkage void do_cpu(struct pt_regs *regs)
798 die_if_kernel("do_cpu invoked from kernel context!", regs);
800 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
805 if (!simulate_llsc(regs))
808 if (!simulate_rdhwr(regs))
817 if (used_math()) { /* Using the FPU again. */
819 } else { /* First time FPU user. */
827 int sig = fpu_emulator_cop1Handler(regs,
828 ¤t->thread.fpu);
830 force_sig(sig, current);
831 #ifdef CONFIG_MIPS_MT_FPAFF
834 * MIPS MT processors may have fewer FPU contexts
835 * than CPU threads. If we've emulated more than
836 * some threshold number of instructions, force
837 * migration to a "CPU" that has FP support.
839 if(mt_fpemul_threshold > 0
840 && ((current->thread.emulated_fp++
841 > mt_fpemul_threshold))) {
843 * If there's no FPU present, or if the
844 * application has already restricted
845 * the allowed set to exclude any CPUs
846 * with FPUs, we'll skip the procedure.
848 if (cpus_intersects(current->cpus_allowed,
853 current->thread.user_cpus_allowed,
855 set_cpus_allowed(current, tmask);
856 current->thread.mflags |= MF_FPUBOUND;
860 #endif /* CONFIG_MIPS_MT_FPAFF */
867 die_if_kernel("do_cpu invoked from kernel context!", regs);
871 force_sig(SIGILL, current);
874 asmlinkage void do_mdmx(struct pt_regs *regs)
876 force_sig(SIGILL, current);
879 asmlinkage void do_watch(struct pt_regs *regs)
882 * We use the watch exception where available to detect stack
887 panic("Caught WATCH exception - probably caused by stack overflow.");
890 asmlinkage void do_mcheck(struct pt_regs *regs)
892 const int field = 2 * sizeof(unsigned long);
893 int multi_match = regs->cp0_status & ST0_TS;
898 printk("Index : %0x\n", read_c0_index());
899 printk("Pagemask: %0x\n", read_c0_pagemask());
900 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
901 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
902 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
907 show_code((unsigned int *) regs->cp0_epc);
910 * Some chips may have other causes of machine check (e.g. SB1
913 panic("Caught Machine Check exception - %scaused by multiple "
914 "matching entries in the TLB.",
915 (multi_match) ? "" : "not ");
918 asmlinkage void do_mt(struct pt_regs *regs)
922 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
923 >> VPECONTROL_EXCPT_SHIFT;
926 printk(KERN_DEBUG "Thread Underflow\n");
929 printk(KERN_DEBUG "Thread Overflow\n");
932 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
935 printk(KERN_DEBUG "Gating Storage Exception\n");
938 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
941 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
944 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
948 die_if_kernel("MIPS MT Thread exception in kernel", regs);
950 force_sig(SIGILL, current);
954 asmlinkage void do_dsp(struct pt_regs *regs)
957 panic("Unexpected DSP exception\n");
959 force_sig(SIGILL, current);
962 asmlinkage void do_reserved(struct pt_regs *regs)
965 * Game over - no way to handle this if it ever occurs. Most probably
966 * caused by a new unknown cpu type or after another deadly
967 * hard/software error.
970 panic("Caught reserved exception %ld - should not happen.",
971 (regs->cp0_cause & 0x7f) >> 2);
974 asmlinkage void do_default_vi(struct pt_regs *regs)
977 panic("Caught unexpected vectored interrupt.");
981 * Some MIPS CPUs can enable/disable for cache parity detection, but do
984 static inline void parity_protection_init(void)
986 switch (current_cpu_data.cputype) {
990 write_c0_ecc(0x80000000);
991 back_to_back_c0_hazard();
992 /* Set the PE bit (bit 31) in the c0_errctl register. */
993 printk(KERN_INFO "Cache parity protection %sabled\n",
994 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
998 /* Clear the DE bit (bit 16) in the c0_status register. */
999 printk(KERN_INFO "Enable cache parity protection for "
1000 "MIPS 20KC/25KF CPUs.\n");
1001 clear_c0_status(ST0_DE);
1008 asmlinkage void cache_parity_error(void)
1010 const int field = 2 * sizeof(unsigned long);
1011 unsigned int reg_val;
1013 /* For the moment, report the problem and hang. */
1014 printk("Cache error exception:\n");
1015 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1016 reg_val = read_c0_cacheerr();
1017 printk("c0_cacheerr == %08x\n", reg_val);
1019 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1020 reg_val & (1<<30) ? "secondary" : "primary",
1021 reg_val & (1<<31) ? "data" : "insn");
1022 printk("Error bits: %s%s%s%s%s%s%s\n",
1023 reg_val & (1<<29) ? "ED " : "",
1024 reg_val & (1<<28) ? "ET " : "",
1025 reg_val & (1<<26) ? "EE " : "",
1026 reg_val & (1<<25) ? "EB " : "",
1027 reg_val & (1<<24) ? "EI " : "",
1028 reg_val & (1<<23) ? "E1 " : "",
1029 reg_val & (1<<22) ? "E0 " : "");
1030 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1032 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1033 if (reg_val & (1<<22))
1034 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1036 if (reg_val & (1<<23))
1037 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1040 panic("Can't handle the cache error!");
1044 * SDBBP EJTAG debug exception handler.
1045 * We skip the instruction and return to the next instruction.
1047 void ejtag_exception_handler(struct pt_regs *regs)
1049 const int field = 2 * sizeof(unsigned long);
1050 unsigned long depc, old_epc;
1053 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1054 depc = read_c0_depc();
1055 debug = read_c0_debug();
1056 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1057 if (debug & 0x80000000) {
1059 * In branch delay slot.
1060 * We cheat a little bit here and use EPC to calculate the
1061 * debug return address (DEPC). EPC is restored after the
1064 old_epc = regs->cp0_epc;
1065 regs->cp0_epc = depc;
1066 __compute_return_epc(regs);
1067 depc = regs->cp0_epc;
1068 regs->cp0_epc = old_epc;
1071 write_c0_depc(depc);
1074 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1075 write_c0_debug(debug | 0x100);
1080 * NMI exception handler.
1082 void nmi_exception_handler(struct pt_regs *regs)
1084 #ifdef CONFIG_MIPS_MT_SMTC
1085 unsigned long dvpret = dvpe();
1087 printk("NMI taken!!!!\n");
1088 mips_mt_regdump(dvpret);
1091 printk("NMI taken!!!!\n");
1092 #endif /* CONFIG_MIPS_MT_SMTC */
1097 #define VECTORSPACING 0x100 /* for EI/VI mode */
1099 unsigned long ebase;
1100 unsigned long exception_handlers[32];
1101 unsigned long vi_handlers[64];
1104 * As a side effect of the way this is implemented we're limited
1105 * to interrupt handlers in the address range from
1106 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1108 void *set_except_vector(int n, void *addr)
1110 unsigned long handler = (unsigned long) addr;
1111 unsigned long old_handler = exception_handlers[n];
1113 exception_handlers[n] = handler;
1114 if (n == 0 && cpu_has_divec) {
1115 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1116 (0x03ffffff & (handler >> 2));
1117 flush_icache_range(ebase + 0x200, ebase + 0x204);
1119 return (void *)old_handler;
1122 #ifdef CONFIG_CPU_MIPSR2_SRS
1124 * MIPSR2 shadow register set allocation
1128 static struct shadow_registers {
1130 * Number of shadow register sets supported
1132 unsigned long sr_supported;
1134 * Bitmap of allocated shadow registers
1136 unsigned long sr_allocated;
1139 static void mips_srs_init(void)
1141 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1142 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1143 shadow_registers.sr_supported);
1144 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1147 int mips_srs_max(void)
1149 return shadow_registers.sr_supported;
1152 int mips_srs_alloc(void)
1154 struct shadow_registers *sr = &shadow_registers;
1158 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1159 if (set >= sr->sr_supported)
1162 if (test_and_set_bit(set, &sr->sr_allocated))
1168 void mips_srs_free(int set)
1170 struct shadow_registers *sr = &shadow_registers;
1172 clear_bit(set, &sr->sr_allocated);
1175 static void *set_vi_srs_handler(int n, void *addr, int srs)
1177 unsigned long handler;
1178 unsigned long old_handler = vi_handlers[n];
1182 if (!cpu_has_veic && !cpu_has_vint)
1186 handler = (unsigned long) do_default_vi;
1189 handler = (unsigned long) addr;
1190 vi_handlers[n] = (unsigned long) addr;
1192 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1194 if (srs >= mips_srs_max())
1195 panic("Shadow register set %d not supported", srs);
1198 if (board_bind_eic_interrupt)
1199 board_bind_eic_interrupt (n, srs);
1200 } else if (cpu_has_vint) {
1201 /* SRSMap is only defined if shadow sets are implemented */
1202 if (mips_srs_max() > 1)
1203 change_c0_srsmap (0xf << n*4, srs << n*4);
1208 * If no shadow set is selected then use the default handler
1209 * that does normal register saving and a standard interrupt exit
1212 extern char except_vec_vi, except_vec_vi_lui;
1213 extern char except_vec_vi_ori, except_vec_vi_end;
1214 #ifdef CONFIG_MIPS_MT_SMTC
1216 * We need to provide the SMTC vectored interrupt handler
1217 * not only with the address of the handler, but with the
1218 * Status.IM bit to be masked before going there.
1220 extern char except_vec_vi_mori;
1221 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1222 #endif /* CONFIG_MIPS_MT_SMTC */
1223 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1224 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1225 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1227 if (handler_len > VECTORSPACING) {
1229 * Sigh... panicing won't help as the console
1230 * is probably not configured :(
1232 panic ("VECTORSPACING too small");
1235 memcpy (b, &except_vec_vi, handler_len);
1236 #ifdef CONFIG_MIPS_MT_SMTC
1238 printk("Vector index %d exceeds SMTC maximum\n", n);
1239 w = (u32 *)(b + mori_offset);
1240 *w = (*w & 0xffff0000) | (0x100 << n);
1241 #endif /* CONFIG_MIPS_MT_SMTC */
1242 w = (u32 *)(b + lui_offset);
1243 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1244 w = (u32 *)(b + ori_offset);
1245 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1246 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1250 * In other cases jump directly to the interrupt handler
1252 * It is the handlers responsibility to save registers if required
1253 * (eg hi/lo) and return from the exception using "eret"
1256 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1258 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1261 return (void *)old_handler;
1264 void *set_vi_handler(int n, void *addr)
1266 return set_vi_srs_handler(n, addr, 0);
1271 static inline void mips_srs_init(void)
1275 #endif /* CONFIG_CPU_MIPSR2_SRS */
1278 * This is used by native signal handling
1280 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1281 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1283 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1284 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1286 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1287 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1290 static int smp_save_fp_context(struct sigcontext *sc)
1293 ? _save_fp_context(sc)
1294 : fpu_emulator_save_context(sc);
1297 static int smp_restore_fp_context(struct sigcontext *sc)
1300 ? _restore_fp_context(sc)
1301 : fpu_emulator_restore_context(sc);
1305 static inline void signal_init(void)
1308 /* For now just do the cpu_has_fpu check when the functions are invoked */
1309 save_fp_context = smp_save_fp_context;
1310 restore_fp_context = smp_restore_fp_context;
1313 save_fp_context = _save_fp_context;
1314 restore_fp_context = _restore_fp_context;
1316 save_fp_context = fpu_emulator_save_context;
1317 restore_fp_context = fpu_emulator_restore_context;
1322 #ifdef CONFIG_MIPS32_COMPAT
1325 * This is used by 32-bit signal stuff on the 64-bit kernel
1327 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1328 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1330 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1331 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1333 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1334 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1336 static inline void signal32_init(void)
1339 save_fp_context32 = _save_fp_context32;
1340 restore_fp_context32 = _restore_fp_context32;
1342 save_fp_context32 = fpu_emulator_save_context32;
1343 restore_fp_context32 = fpu_emulator_restore_context32;
1348 extern void cpu_cache_init(void);
1349 extern void tlb_init(void);
1350 extern void flush_tlb_handlers(void);
1352 void __init per_cpu_trap_init(void)
1354 unsigned int cpu = smp_processor_id();
1355 unsigned int status_set = ST0_CU0;
1356 #ifdef CONFIG_MIPS_MT_SMTC
1357 int secondaryTC = 0;
1358 int bootTC = (cpu == 0);
1361 * Only do per_cpu_trap_init() for first TC of Each VPE.
1362 * Note that this hack assumes that the SMTC init code
1363 * assigns TCs consecutively and in ascending order.
1366 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1367 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1369 #endif /* CONFIG_MIPS_MT_SMTC */
1372 * Disable coprocessors and select 32-bit or 64-bit addressing
1373 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1374 * flag that some firmware may have left set and the TS bit (for
1375 * IP27). Set XX for ISA IV code to work.
1378 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1380 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1381 status_set |= ST0_XX;
1382 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1386 set_c0_status(ST0_MX);
1388 #ifdef CONFIG_CPU_MIPSR2
1389 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1392 #ifdef CONFIG_MIPS_MT_SMTC
1394 #endif /* CONFIG_MIPS_MT_SMTC */
1397 * Interrupt handling.
1399 if (cpu_has_veic || cpu_has_vint) {
1400 write_c0_ebase (ebase);
1401 /* Setting vector spacing enables EI/VI mode */
1402 change_c0_intctl (0x3e0, VECTORSPACING);
1404 if (cpu_has_divec) {
1405 if (cpu_has_mipsmt) {
1406 unsigned int vpflags = dvpe();
1407 set_c0_cause(CAUSEF_IV);
1410 set_c0_cause(CAUSEF_IV);
1412 #ifdef CONFIG_MIPS_MT_SMTC
1414 #endif /* CONFIG_MIPS_MT_SMTC */
1416 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1417 TLBMISS_HANDLER_SETUP();
1419 atomic_inc(&init_mm.mm_count);
1420 current->active_mm = &init_mm;
1421 BUG_ON(current->mm);
1422 enter_lazy_tlb(&init_mm, current);
1424 #ifdef CONFIG_MIPS_MT_SMTC
1426 #endif /* CONFIG_MIPS_MT_SMTC */
1429 #ifdef CONFIG_MIPS_MT_SMTC
1431 #endif /* CONFIG_MIPS_MT_SMTC */
1434 /* Install CPU exception handler */
1435 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1437 memcpy((void *)(ebase + offset), addr, size);
1438 flush_icache_range(ebase + offset, ebase + offset + size);
1441 /* Install uncached CPU exception handler */
1442 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1445 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1448 unsigned long uncached_ebase = TO_UNCAC(ebase);
1451 memcpy((void *)(uncached_ebase + offset), addr, size);
1454 void __init trap_init(void)
1456 extern char except_vec3_generic, except_vec3_r4000;
1457 extern char except_vec4;
1460 if (cpu_has_veic || cpu_has_vint)
1461 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1467 per_cpu_trap_init();
1470 * Copy the generic exception handlers to their final destination.
1471 * This will be overriden later as suitable for a particular
1474 set_handler(0x180, &except_vec3_generic, 0x80);
1477 * Setup default vectors
1479 for (i = 0; i <= 31; i++)
1480 set_except_vector(i, handle_reserved);
1483 * Copy the EJTAG debug exception vector handler code to it's final
1486 if (cpu_has_ejtag && board_ejtag_handler_setup)
1487 board_ejtag_handler_setup ();
1490 * Only some CPUs have the watch exceptions.
1493 set_except_vector(23, handle_watch);
1496 * Initialise interrupt handlers
1498 if (cpu_has_veic || cpu_has_vint) {
1499 int nvec = cpu_has_veic ? 64 : 8;
1500 for (i = 0; i < nvec; i++)
1501 set_vi_handler(i, NULL);
1503 else if (cpu_has_divec)
1504 set_handler(0x200, &except_vec4, 0x8);
1507 * Some CPUs can enable/disable for cache parity detection, but does
1508 * it different ways.
1510 parity_protection_init();
1513 * The Data Bus Errors / Instruction Bus Errors are signaled
1514 * by external hardware. Therefore these two exceptions
1515 * may have board specific handlers.
1520 set_except_vector(0, handle_int);
1521 set_except_vector(1, handle_tlbm);
1522 set_except_vector(2, handle_tlbl);
1523 set_except_vector(3, handle_tlbs);
1525 set_except_vector(4, handle_adel);
1526 set_except_vector(5, handle_ades);
1528 set_except_vector(6, handle_ibe);
1529 set_except_vector(7, handle_dbe);
1531 set_except_vector(8, handle_sys);
1532 set_except_vector(9, handle_bp);
1533 set_except_vector(10, handle_ri);
1534 set_except_vector(11, handle_cpu);
1535 set_except_vector(12, handle_ov);
1536 set_except_vector(13, handle_tr);
1538 if (current_cpu_data.cputype == CPU_R6000 ||
1539 current_cpu_data.cputype == CPU_R6000A) {
1541 * The R6000 is the only R-series CPU that features a machine
1542 * check exception (similar to the R4000 cache error) and
1543 * unaligned ldc1/sdc1 exception. The handlers have not been
1544 * written yet. Well, anyway there is no R6000 machine on the
1545 * current list of targets for Linux/MIPS.
1546 * (Duh, crap, there is someone with a triple R6k machine)
1548 //set_except_vector(14, handle_mc);
1549 //set_except_vector(15, handle_ndc);
1553 if (board_nmi_handler_setup)
1554 board_nmi_handler_setup();
1556 if (cpu_has_fpu && !cpu_has_nofpuex)
1557 set_except_vector(15, handle_fpe);
1559 set_except_vector(22, handle_mdmx);
1562 set_except_vector(24, handle_mcheck);
1565 set_except_vector(25, handle_mt);
1568 set_except_vector(26, handle_dsp);
1571 /* Special exception: R4[04]00 uses also the divec space. */
1572 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1573 else if (cpu_has_4kex)
1574 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1576 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1579 #ifdef CONFIG_MIPS32_COMPAT
1583 flush_icache_range(ebase, ebase + 0x400);
1584 flush_tlb_handlers();