2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
44 #include <asm/stacktrace.h>
46 extern asmlinkage void handle_int(void);
47 extern asmlinkage void handle_tlbm(void);
48 extern asmlinkage void handle_tlbl(void);
49 extern asmlinkage void handle_tlbs(void);
50 extern asmlinkage void handle_adel(void);
51 extern asmlinkage void handle_ades(void);
52 extern asmlinkage void handle_ibe(void);
53 extern asmlinkage void handle_dbe(void);
54 extern asmlinkage void handle_sys(void);
55 extern asmlinkage void handle_bp(void);
56 extern asmlinkage void handle_ri(void);
57 extern asmlinkage void handle_ri_rdhwr_vivt(void);
58 extern asmlinkage void handle_ri_rdhwr(void);
59 extern asmlinkage void handle_cpu(void);
60 extern asmlinkage void handle_ov(void);
61 extern asmlinkage void handle_tr(void);
62 extern asmlinkage void handle_fpe(void);
63 extern asmlinkage void handle_mdmx(void);
64 extern asmlinkage void handle_watch(void);
65 extern asmlinkage void handle_mt(void);
66 extern asmlinkage void handle_dsp(void);
67 extern asmlinkage void handle_mcheck(void);
68 extern asmlinkage void handle_reserved(void);
70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
71 struct mips_fpu_struct *ctx, int has_fpu);
73 void (*board_be_init)(void);
74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
75 void (*board_nmi_handler_setup)(void);
76 void (*board_ejtag_handler_setup)(void);
77 void (*board_bind_eic_interrupt)(int irq, int regset);
80 static void show_raw_backtrace(unsigned long reg29)
82 unsigned long *sp = (unsigned long *)reg29;
85 printk("Call Trace:");
86 #ifdef CONFIG_KALLSYMS
89 while (!kstack_end(sp)) {
91 if (__kernel_text_address(addr))
97 #ifdef CONFIG_KALLSYMS
99 static int __init set_raw_show_trace(char *str)
104 __setup("raw_show_trace", set_raw_show_trace);
107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
109 unsigned long sp = regs->regs[29];
110 unsigned long ra = regs->regs[31];
111 unsigned long pc = regs->cp0_epc;
113 if (raw_show_trace || !__kernel_text_address(pc)) {
114 show_raw_backtrace(sp);
117 printk("Call Trace:\n");
120 pc = unwind_stack(task, &sp, pc, &ra);
126 * This routine abuses get_user()/put_user() to reference pointers
127 * with at least a bit of error checking ...
129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
131 const int field = 2 * sizeof(unsigned long);
134 unsigned long *sp = (unsigned long *)regs->regs[29];
138 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
139 if (i && ((i % (64 / field)) == 0))
146 if (__get_user(stackdata, sp++)) {
147 printk(" (Bad stack address)");
151 printk(" %0*lx", field, stackdata);
155 show_backtrace(task, regs);
158 void show_stack(struct task_struct *task, unsigned long *sp)
162 regs.regs[29] = (unsigned long)sp;
166 if (task && task != current) {
167 regs.regs[29] = task->thread.reg29;
169 regs.cp0_epc = task->thread.reg31;
171 prepare_frametrace(®s);
174 show_stacktrace(task, ®s);
178 * The architecture-independent dump_stack generator
180 void dump_stack(void)
184 prepare_frametrace(®s);
185 show_backtrace(current, ®s);
188 EXPORT_SYMBOL(dump_stack);
190 void show_code(unsigned int *pc)
196 for(i = -3 ; i < 6 ; i++) {
198 if (__get_user(insn, pc + i)) {
199 printk(" (Bad address in epc)\n");
202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
206 void show_regs(struct pt_regs *regs)
208 const int field = 2 * sizeof(unsigned long);
209 unsigned int cause = regs->cp0_cause;
212 printk("Cpu %d\n", smp_processor_id());
215 * Saved main processor registers
217 for (i = 0; i < 32; ) {
221 printk(" %0*lx", field, 0UL);
222 else if (i == 26 || i == 27)
223 printk(" %*s", field, "");
225 printk(" %0*lx", field, regs->regs[i]);
232 printk("Hi : %0*lx\n", field, regs->hi);
233 printk("Lo : %0*lx\n", field, regs->lo);
236 * Saved cp0 registers
238 printk("epc : %0*lx ", field, regs->cp0_epc);
239 print_symbol("%s ", regs->cp0_epc);
240 printk(" %s\n", print_tainted());
241 printk("ra : %0*lx ", field, regs->regs[31]);
242 print_symbol("%s\n", regs->regs[31]);
244 printk("Status: %08x ", (uint32_t) regs->cp0_status);
246 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
247 if (regs->cp0_status & ST0_KUO)
249 if (regs->cp0_status & ST0_IEO)
251 if (regs->cp0_status & ST0_KUP)
253 if (regs->cp0_status & ST0_IEP)
255 if (regs->cp0_status & ST0_KUC)
257 if (regs->cp0_status & ST0_IEC)
260 if (regs->cp0_status & ST0_KX)
262 if (regs->cp0_status & ST0_SX)
264 if (regs->cp0_status & ST0_UX)
266 switch (regs->cp0_status & ST0_KSU) {
271 printk("SUPERVISOR ");
280 if (regs->cp0_status & ST0_ERL)
282 if (regs->cp0_status & ST0_EXL)
284 if (regs->cp0_status & ST0_IE)
289 printk("Cause : %08x\n", cause);
291 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
292 if (1 <= cause && cause <= 5)
293 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
295 printk("PrId : %08x\n", read_c0_prid());
298 void show_registers(struct pt_regs *regs)
302 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
303 current->comm, current->pid, current_thread_info(), current);
304 show_stacktrace(current, regs);
305 show_code((unsigned int *) regs->cp0_epc);
309 static DEFINE_SPINLOCK(die_lock);
311 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
313 static int die_counter;
314 #ifdef CONFIG_MIPS_MT_SMTC
315 unsigned long dvpret = dvpe();
316 #endif /* CONFIG_MIPS_MT_SMTC */
319 spin_lock_irq(&die_lock);
321 #ifdef CONFIG_MIPS_MT_SMTC
322 mips_mt_regdump(dvpret);
323 #endif /* CONFIG_MIPS_MT_SMTC */
324 printk("%s[#%d]:\n", str, ++die_counter);
325 show_registers(regs);
326 spin_unlock_irq(&die_lock);
329 panic("Fatal exception in interrupt");
332 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
334 panic("Fatal exception");
340 extern const struct exception_table_entry __start___dbe_table[];
341 extern const struct exception_table_entry __stop___dbe_table[];
343 void __declare_dbe_table(void)
345 __asm__ __volatile__(
346 ".section\t__dbe_table,\"a\"\n\t"
351 /* Given an address, look for it in the exception tables. */
352 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
354 const struct exception_table_entry *e;
356 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
358 e = search_module_dbetables(addr);
362 asmlinkage void do_be(struct pt_regs *regs)
364 const int field = 2 * sizeof(unsigned long);
365 const struct exception_table_entry *fixup = NULL;
366 int data = regs->cp0_cause & 4;
367 int action = MIPS_BE_FATAL;
369 /* XXX For now. Fixme, this searches the wrong table ... */
370 if (data && !user_mode(regs))
371 fixup = search_dbe_tables(exception_epc(regs));
374 action = MIPS_BE_FIXUP;
376 if (board_be_handler)
377 action = board_be_handler(regs, fixup != 0);
380 case MIPS_BE_DISCARD:
384 regs->cp0_epc = fixup->nextinsn;
393 * Assume it would be too dangerous to continue ...
395 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
396 data ? "Data" : "Instruction",
397 field, regs->cp0_epc, field, regs->regs[31]);
398 die_if_kernel("Oops", regs);
399 force_sig(SIGBUS, current);
406 #define OPCODE 0xfc000000
407 #define BASE 0x03e00000
408 #define RT 0x001f0000
409 #define OFFSET 0x0000ffff
410 #define LL 0xc0000000
411 #define SC 0xe0000000
412 #define SPEC3 0x7c000000
413 #define RD 0x0000f800
414 #define FUNC 0x0000003f
415 #define RDHWR 0x0000003b
418 * The ll_bit is cleared by r*_switch.S
421 unsigned long ll_bit;
423 static struct task_struct *ll_task = NULL;
425 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
427 unsigned long value, __user *vaddr;
432 * analyse the ll instruction that just caused a ri exception
433 * and put the referenced address to addr.
436 /* sign extend offset */
437 offset = opcode & OFFSET;
441 vaddr = (unsigned long __user *)
442 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
444 if ((unsigned long)vaddr & 3) {
448 if (get_user(value, vaddr)) {
455 if (ll_task == NULL || ll_task == current) {
464 compute_return_epc(regs);
466 regs->regs[(opcode & RT) >> 16] = value;
471 force_sig(signal, current);
474 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
476 unsigned long __user *vaddr;
482 * analyse the sc instruction that just caused a ri exception
483 * and put the referenced address to addr.
486 /* sign extend offset */
487 offset = opcode & OFFSET;
491 vaddr = (unsigned long __user *)
492 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
493 reg = (opcode & RT) >> 16;
495 if ((unsigned long)vaddr & 3) {
502 if (ll_bit == 0 || ll_task != current) {
503 compute_return_epc(regs);
511 if (put_user(regs->regs[reg], vaddr)) {
516 compute_return_epc(regs);
522 force_sig(signal, current);
526 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
527 * opcodes are supposed to result in coprocessor unusable exceptions if
528 * executed on ll/sc-less processors. That's the theory. In practice a
529 * few processors such as NEC's VR4100 throw reserved instruction exceptions
530 * instead, so we're doing the emulation thing in both exception handlers.
532 static inline int simulate_llsc(struct pt_regs *regs)
536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
539 if ((opcode & OPCODE) == LL) {
540 simulate_ll(regs, opcode);
543 if ((opcode & OPCODE) == SC) {
544 simulate_sc(regs, opcode);
548 return -EFAULT; /* Strange things going on ... */
551 force_sig(SIGSEGV, current);
556 * Simulate trapping 'rdhwr' instructions to provide user accessible
557 * registers not implemented in hardware. The only current use of this
558 * is the thread area pointer.
560 static inline int simulate_rdhwr(struct pt_regs *regs)
562 struct thread_info *ti = task_thread_info(current);
565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
568 if (unlikely(compute_return_epc(regs)))
571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
572 int rd = (opcode & RD) >> 11;
573 int rt = (opcode & RT) >> 16;
576 regs->regs[rt] = ti->tp_value;
587 force_sig(SIGSEGV, current);
591 asmlinkage void do_ov(struct pt_regs *regs)
595 die_if_kernel("Integer overflow", regs);
597 info.si_code = FPE_INTOVF;
598 info.si_signo = SIGFPE;
600 info.si_addr = (void __user *) regs->cp0_epc;
601 force_sig_info(SIGFPE, &info, current);
605 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
607 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
609 die_if_kernel("FP exception in kernel code", regs);
611 if (fcr31 & FPU_CSR_UNI_X) {
616 #ifdef CONFIG_PREEMPT
617 if (!is_fpu_owner()) {
618 /* We might lose fpu before disabling preempt... */
620 BUG_ON(!used_math());
625 * Unimplemented operation exception. If we've got the full
626 * software emulator on-board, let's use it...
628 * Force FPU to dump state into task/thread context. We're
629 * moving a lot of data here for what is probably a single
630 * instruction, but the alternative is to pre-decode the FP
631 * register operands before invoking the emulator, which seems
632 * a bit extreme for what should be an infrequent event.
635 /* Ensure 'resume' not overwrite saved fp context again. */
640 /* Run the emulator */
641 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1);
645 own_fpu(); /* Using the FPU again. */
647 * We can't allow the emulated instruction to leave any of
648 * the cause bit set in $fcr31.
650 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
652 /* Restore the hardware register state */
657 /* If something went wrong, signal */
659 force_sig(sig, current);
664 force_sig(SIGFPE, current);
667 asmlinkage void do_bp(struct pt_regs *regs)
669 unsigned int opcode, bcode;
672 die_if_kernel("Break instruction in kernel code", regs);
674 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
678 * There is the ancient bug in the MIPS assemblers that the break
679 * code starts left to bit 16 instead to bit 6 in the opcode.
680 * Gas is bug-compatible, but not always, grrr...
681 * We handle both cases with a simple heuristics. --macro
683 bcode = ((opcode >> 6) & ((1 << 20) - 1));
684 if (bcode < (1 << 10))
688 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
689 * insns, even for break codes that indicate arithmetic failures.
691 * But should we continue the brokenness??? --macro
694 case BRK_OVERFLOW << 10:
695 case BRK_DIVZERO << 10:
696 if (bcode == (BRK_DIVZERO << 10))
697 info.si_code = FPE_INTDIV;
699 info.si_code = FPE_INTOVF;
700 info.si_signo = SIGFPE;
702 info.si_addr = (void __user *) regs->cp0_epc;
703 force_sig_info(SIGFPE, &info, current);
706 force_sig(SIGTRAP, current);
710 force_sig(SIGSEGV, current);
713 asmlinkage void do_tr(struct pt_regs *regs)
715 unsigned int opcode, tcode = 0;
718 die_if_kernel("Trap instruction in kernel code", regs);
720 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
723 /* Immediate versions don't provide a code. */
724 if (!(opcode & OPCODE))
725 tcode = ((opcode >> 6) & ((1 << 10) - 1));
728 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
729 * insns, even for trap codes that indicate arithmetic failures.
731 * But should we continue the brokenness??? --macro
736 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV;
739 info.si_code = FPE_INTOVF;
740 info.si_signo = SIGFPE;
742 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current);
746 force_sig(SIGTRAP, current);
750 force_sig(SIGSEGV, current);
753 asmlinkage void do_ri(struct pt_regs *regs)
755 die_if_kernel("Reserved instruction in kernel code", regs);
758 if (!simulate_llsc(regs))
761 if (!simulate_rdhwr(regs))
764 force_sig(SIGILL, current);
767 asmlinkage void do_cpu(struct pt_regs *regs)
771 die_if_kernel("do_cpu invoked from kernel context!", regs);
773 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
778 if (!simulate_llsc(regs))
781 if (!simulate_rdhwr(regs))
790 if (used_math()) { /* Using the FPU again. */
792 } else { /* First time FPU user. */
802 sig = fpu_emulator_cop1Handler(regs,
803 ¤t->thread.fpu, 0);
805 force_sig(sig, current);
806 #ifdef CONFIG_MIPS_MT_FPAFF
809 * MIPS MT processors may have fewer FPU contexts
810 * than CPU threads. If we've emulated more than
811 * some threshold number of instructions, force
812 * migration to a "CPU" that has FP support.
814 if(mt_fpemul_threshold > 0
815 && ((current->thread.emulated_fp++
816 > mt_fpemul_threshold))) {
818 * If there's no FPU present, or if the
819 * application has already restricted
820 * the allowed set to exclude any CPUs
821 * with FPUs, we'll skip the procedure.
823 if (cpus_intersects(current->cpus_allowed,
828 current->thread.user_cpus_allowed,
830 set_cpus_allowed(current, tmask);
831 current->thread.mflags |= MF_FPUBOUND;
835 #endif /* CONFIG_MIPS_MT_FPAFF */
842 die_if_kernel("do_cpu invoked from kernel context!", regs);
846 force_sig(SIGILL, current);
849 asmlinkage void do_mdmx(struct pt_regs *regs)
851 force_sig(SIGILL, current);
854 asmlinkage void do_watch(struct pt_regs *regs)
857 * We use the watch exception where available to detect stack
862 panic("Caught WATCH exception - probably caused by stack overflow.");
865 asmlinkage void do_mcheck(struct pt_regs *regs)
867 const int field = 2 * sizeof(unsigned long);
868 int multi_match = regs->cp0_status & ST0_TS;
873 printk("Index : %0x\n", read_c0_index());
874 printk("Pagemask: %0x\n", read_c0_pagemask());
875 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
876 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
877 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
882 show_code((unsigned int *) regs->cp0_epc);
885 * Some chips may have other causes of machine check (e.g. SB1
888 panic("Caught Machine Check exception - %scaused by multiple "
889 "matching entries in the TLB.",
890 (multi_match) ? "" : "not ");
893 asmlinkage void do_mt(struct pt_regs *regs)
897 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
898 >> VPECONTROL_EXCPT_SHIFT;
901 printk(KERN_DEBUG "Thread Underflow\n");
904 printk(KERN_DEBUG "Thread Overflow\n");
907 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
910 printk(KERN_DEBUG "Gating Storage Exception\n");
913 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
916 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
919 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
923 die_if_kernel("MIPS MT Thread exception in kernel", regs);
925 force_sig(SIGILL, current);
929 asmlinkage void do_dsp(struct pt_regs *regs)
932 panic("Unexpected DSP exception\n");
934 force_sig(SIGILL, current);
937 asmlinkage void do_reserved(struct pt_regs *regs)
940 * Game over - no way to handle this if it ever occurs. Most probably
941 * caused by a new unknown cpu type or after another deadly
942 * hard/software error.
945 panic("Caught reserved exception %ld - should not happen.",
946 (regs->cp0_cause & 0x7f) >> 2);
949 asmlinkage void do_default_vi(struct pt_regs *regs)
952 panic("Caught unexpected vectored interrupt.");
956 * Some MIPS CPUs can enable/disable for cache parity detection, but do
959 static inline void parity_protection_init(void)
961 switch (current_cpu_data.cputype) {
965 write_c0_ecc(0x80000000);
966 back_to_back_c0_hazard();
967 /* Set the PE bit (bit 31) in the c0_errctl register. */
968 printk(KERN_INFO "Cache parity protection %sabled\n",
969 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
973 /* Clear the DE bit (bit 16) in the c0_status register. */
974 printk(KERN_INFO "Enable cache parity protection for "
975 "MIPS 20KC/25KF CPUs.\n");
976 clear_c0_status(ST0_DE);
983 asmlinkage void cache_parity_error(void)
985 const int field = 2 * sizeof(unsigned long);
986 unsigned int reg_val;
988 /* For the moment, report the problem and hang. */
989 printk("Cache error exception:\n");
990 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
991 reg_val = read_c0_cacheerr();
992 printk("c0_cacheerr == %08x\n", reg_val);
994 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
995 reg_val & (1<<30) ? "secondary" : "primary",
996 reg_val & (1<<31) ? "data" : "insn");
997 printk("Error bits: %s%s%s%s%s%s%s\n",
998 reg_val & (1<<29) ? "ED " : "",
999 reg_val & (1<<28) ? "ET " : "",
1000 reg_val & (1<<26) ? "EE " : "",
1001 reg_val & (1<<25) ? "EB " : "",
1002 reg_val & (1<<24) ? "EI " : "",
1003 reg_val & (1<<23) ? "E1 " : "",
1004 reg_val & (1<<22) ? "E0 " : "");
1005 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1007 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1008 if (reg_val & (1<<22))
1009 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1011 if (reg_val & (1<<23))
1012 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1015 panic("Can't handle the cache error!");
1019 * SDBBP EJTAG debug exception handler.
1020 * We skip the instruction and return to the next instruction.
1022 void ejtag_exception_handler(struct pt_regs *regs)
1024 const int field = 2 * sizeof(unsigned long);
1025 unsigned long depc, old_epc;
1028 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1029 depc = read_c0_depc();
1030 debug = read_c0_debug();
1031 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1032 if (debug & 0x80000000) {
1034 * In branch delay slot.
1035 * We cheat a little bit here and use EPC to calculate the
1036 * debug return address (DEPC). EPC is restored after the
1039 old_epc = regs->cp0_epc;
1040 regs->cp0_epc = depc;
1041 __compute_return_epc(regs);
1042 depc = regs->cp0_epc;
1043 regs->cp0_epc = old_epc;
1046 write_c0_depc(depc);
1049 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1050 write_c0_debug(debug | 0x100);
1055 * NMI exception handler.
1057 void nmi_exception_handler(struct pt_regs *regs)
1059 #ifdef CONFIG_MIPS_MT_SMTC
1060 unsigned long dvpret = dvpe();
1062 printk("NMI taken!!!!\n");
1063 mips_mt_regdump(dvpret);
1066 printk("NMI taken!!!!\n");
1067 #endif /* CONFIG_MIPS_MT_SMTC */
1072 #define VECTORSPACING 0x100 /* for EI/VI mode */
1074 unsigned long ebase;
1075 unsigned long exception_handlers[32];
1076 unsigned long vi_handlers[64];
1079 * As a side effect of the way this is implemented we're limited
1080 * to interrupt handlers in the address range from
1081 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1083 void *set_except_vector(int n, void *addr)
1085 unsigned long handler = (unsigned long) addr;
1086 unsigned long old_handler = exception_handlers[n];
1088 exception_handlers[n] = handler;
1089 if (n == 0 && cpu_has_divec) {
1090 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1091 (0x03ffffff & (handler >> 2));
1092 flush_icache_range(ebase + 0x200, ebase + 0x204);
1094 return (void *)old_handler;
1097 #ifdef CONFIG_CPU_MIPSR2_SRS
1099 * MIPSR2 shadow register set allocation
1103 static struct shadow_registers {
1105 * Number of shadow register sets supported
1107 unsigned long sr_supported;
1109 * Bitmap of allocated shadow registers
1111 unsigned long sr_allocated;
1114 static void mips_srs_init(void)
1116 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1117 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1118 shadow_registers.sr_supported);
1119 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1122 int mips_srs_max(void)
1124 return shadow_registers.sr_supported;
1127 int mips_srs_alloc(void)
1129 struct shadow_registers *sr = &shadow_registers;
1133 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1134 if (set >= sr->sr_supported)
1137 if (test_and_set_bit(set, &sr->sr_allocated))
1143 void mips_srs_free(int set)
1145 struct shadow_registers *sr = &shadow_registers;
1147 clear_bit(set, &sr->sr_allocated);
1150 static void *set_vi_srs_handler(int n, void *addr, int srs)
1152 unsigned long handler;
1153 unsigned long old_handler = vi_handlers[n];
1157 if (!cpu_has_veic && !cpu_has_vint)
1161 handler = (unsigned long) do_default_vi;
1164 handler = (unsigned long) addr;
1165 vi_handlers[n] = (unsigned long) addr;
1167 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1169 if (srs >= mips_srs_max())
1170 panic("Shadow register set %d not supported", srs);
1173 if (board_bind_eic_interrupt)
1174 board_bind_eic_interrupt (n, srs);
1175 } else if (cpu_has_vint) {
1176 /* SRSMap is only defined if shadow sets are implemented */
1177 if (mips_srs_max() > 1)
1178 change_c0_srsmap (0xf << n*4, srs << n*4);
1183 * If no shadow set is selected then use the default handler
1184 * that does normal register saving and a standard interrupt exit
1187 extern char except_vec_vi, except_vec_vi_lui;
1188 extern char except_vec_vi_ori, except_vec_vi_end;
1189 #ifdef CONFIG_MIPS_MT_SMTC
1191 * We need to provide the SMTC vectored interrupt handler
1192 * not only with the address of the handler, but with the
1193 * Status.IM bit to be masked before going there.
1195 extern char except_vec_vi_mori;
1196 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1197 #endif /* CONFIG_MIPS_MT_SMTC */
1198 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1199 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1200 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1202 if (handler_len > VECTORSPACING) {
1204 * Sigh... panicing won't help as the console
1205 * is probably not configured :(
1207 panic ("VECTORSPACING too small");
1210 memcpy (b, &except_vec_vi, handler_len);
1211 #ifdef CONFIG_MIPS_MT_SMTC
1213 printk("Vector index %d exceeds SMTC maximum\n", n);
1214 w = (u32 *)(b + mori_offset);
1215 *w = (*w & 0xffff0000) | (0x100 << n);
1216 #endif /* CONFIG_MIPS_MT_SMTC */
1217 w = (u32 *)(b + lui_offset);
1218 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1219 w = (u32 *)(b + ori_offset);
1220 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1221 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1225 * In other cases jump directly to the interrupt handler
1227 * It is the handlers responsibility to save registers if required
1228 * (eg hi/lo) and return from the exception using "eret"
1231 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1233 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1236 return (void *)old_handler;
1239 void *set_vi_handler(int n, void *addr)
1241 return set_vi_srs_handler(n, addr, 0);
1246 static inline void mips_srs_init(void)
1250 #endif /* CONFIG_CPU_MIPSR2_SRS */
1253 * This is used by native signal handling
1255 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1256 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1258 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1259 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1261 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1262 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1265 static int smp_save_fp_context(struct sigcontext *sc)
1268 ? _save_fp_context(sc)
1269 : fpu_emulator_save_context(sc);
1272 static int smp_restore_fp_context(struct sigcontext *sc)
1275 ? _restore_fp_context(sc)
1276 : fpu_emulator_restore_context(sc);
1280 static inline void signal_init(void)
1283 /* For now just do the cpu_has_fpu check when the functions are invoked */
1284 save_fp_context = smp_save_fp_context;
1285 restore_fp_context = smp_restore_fp_context;
1288 save_fp_context = _save_fp_context;
1289 restore_fp_context = _restore_fp_context;
1291 save_fp_context = fpu_emulator_save_context;
1292 restore_fp_context = fpu_emulator_restore_context;
1297 #ifdef CONFIG_MIPS32_COMPAT
1300 * This is used by 32-bit signal stuff on the 64-bit kernel
1302 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1303 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1305 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1306 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1308 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1309 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1311 static inline void signal32_init(void)
1314 save_fp_context32 = _save_fp_context32;
1315 restore_fp_context32 = _restore_fp_context32;
1317 save_fp_context32 = fpu_emulator_save_context32;
1318 restore_fp_context32 = fpu_emulator_restore_context32;
1323 extern void cpu_cache_init(void);
1324 extern void tlb_init(void);
1325 extern void flush_tlb_handlers(void);
1327 void __init per_cpu_trap_init(void)
1329 unsigned int cpu = smp_processor_id();
1330 unsigned int status_set = ST0_CU0;
1331 #ifdef CONFIG_MIPS_MT_SMTC
1332 int secondaryTC = 0;
1333 int bootTC = (cpu == 0);
1336 * Only do per_cpu_trap_init() for first TC of Each VPE.
1337 * Note that this hack assumes that the SMTC init code
1338 * assigns TCs consecutively and in ascending order.
1341 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1342 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1344 #endif /* CONFIG_MIPS_MT_SMTC */
1347 * Disable coprocessors and select 32-bit or 64-bit addressing
1348 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1349 * flag that some firmware may have left set and the TS bit (for
1350 * IP27). Set XX for ISA IV code to work.
1353 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1355 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1356 status_set |= ST0_XX;
1357 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1361 set_c0_status(ST0_MX);
1363 #ifdef CONFIG_CPU_MIPSR2
1364 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1367 #ifdef CONFIG_MIPS_MT_SMTC
1369 #endif /* CONFIG_MIPS_MT_SMTC */
1372 * Interrupt handling.
1374 if (cpu_has_veic || cpu_has_vint) {
1375 write_c0_ebase (ebase);
1376 /* Setting vector spacing enables EI/VI mode */
1377 change_c0_intctl (0x3e0, VECTORSPACING);
1379 if (cpu_has_divec) {
1380 if (cpu_has_mipsmt) {
1381 unsigned int vpflags = dvpe();
1382 set_c0_cause(CAUSEF_IV);
1385 set_c0_cause(CAUSEF_IV);
1387 #ifdef CONFIG_MIPS_MT_SMTC
1389 #endif /* CONFIG_MIPS_MT_SMTC */
1391 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1392 TLBMISS_HANDLER_SETUP();
1394 atomic_inc(&init_mm.mm_count);
1395 current->active_mm = &init_mm;
1396 BUG_ON(current->mm);
1397 enter_lazy_tlb(&init_mm, current);
1399 #ifdef CONFIG_MIPS_MT_SMTC
1401 #endif /* CONFIG_MIPS_MT_SMTC */
1404 #ifdef CONFIG_MIPS_MT_SMTC
1406 #endif /* CONFIG_MIPS_MT_SMTC */
1409 /* Install CPU exception handler */
1410 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1412 memcpy((void *)(ebase + offset), addr, size);
1413 flush_icache_range(ebase + offset, ebase + offset + size);
1416 /* Install uncached CPU exception handler */
1417 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1420 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1423 unsigned long uncached_ebase = TO_UNCAC(ebase);
1426 memcpy((void *)(uncached_ebase + offset), addr, size);
1429 static int __initdata rdhwr_noopt;
1430 static int __init set_rdhwr_noopt(char *str)
1436 __setup("rdhwr_noopt", set_rdhwr_noopt);
1438 void __init trap_init(void)
1440 extern char except_vec3_generic, except_vec3_r4000;
1441 extern char except_vec4;
1444 if (cpu_has_veic || cpu_has_vint)
1445 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1451 per_cpu_trap_init();
1454 * Copy the generic exception handlers to their final destination.
1455 * This will be overriden later as suitable for a particular
1458 set_handler(0x180, &except_vec3_generic, 0x80);
1461 * Setup default vectors
1463 for (i = 0; i <= 31; i++)
1464 set_except_vector(i, handle_reserved);
1467 * Copy the EJTAG debug exception vector handler code to it's final
1470 if (cpu_has_ejtag && board_ejtag_handler_setup)
1471 board_ejtag_handler_setup ();
1474 * Only some CPUs have the watch exceptions.
1477 set_except_vector(23, handle_watch);
1480 * Initialise interrupt handlers
1482 if (cpu_has_veic || cpu_has_vint) {
1483 int nvec = cpu_has_veic ? 64 : 8;
1484 for (i = 0; i < nvec; i++)
1485 set_vi_handler(i, NULL);
1487 else if (cpu_has_divec)
1488 set_handler(0x200, &except_vec4, 0x8);
1491 * Some CPUs can enable/disable for cache parity detection, but does
1492 * it different ways.
1494 parity_protection_init();
1497 * The Data Bus Errors / Instruction Bus Errors are signaled
1498 * by external hardware. Therefore these two exceptions
1499 * may have board specific handlers.
1504 set_except_vector(0, handle_int);
1505 set_except_vector(1, handle_tlbm);
1506 set_except_vector(2, handle_tlbl);
1507 set_except_vector(3, handle_tlbs);
1509 set_except_vector(4, handle_adel);
1510 set_except_vector(5, handle_ades);
1512 set_except_vector(6, handle_ibe);
1513 set_except_vector(7, handle_dbe);
1515 set_except_vector(8, handle_sys);
1516 set_except_vector(9, handle_bp);
1517 set_except_vector(10, rdhwr_noopt ? handle_ri :
1518 (cpu_has_vtag_icache ?
1519 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1520 set_except_vector(11, handle_cpu);
1521 set_except_vector(12, handle_ov);
1522 set_except_vector(13, handle_tr);
1524 if (current_cpu_data.cputype == CPU_R6000 ||
1525 current_cpu_data.cputype == CPU_R6000A) {
1527 * The R6000 is the only R-series CPU that features a machine
1528 * check exception (similar to the R4000 cache error) and
1529 * unaligned ldc1/sdc1 exception. The handlers have not been
1530 * written yet. Well, anyway there is no R6000 machine on the
1531 * current list of targets for Linux/MIPS.
1532 * (Duh, crap, there is someone with a triple R6k machine)
1534 //set_except_vector(14, handle_mc);
1535 //set_except_vector(15, handle_ndc);
1539 if (board_nmi_handler_setup)
1540 board_nmi_handler_setup();
1542 if (cpu_has_fpu && !cpu_has_nofpuex)
1543 set_except_vector(15, handle_fpe);
1545 set_except_vector(22, handle_mdmx);
1548 set_except_vector(24, handle_mcheck);
1551 set_except_vector(25, handle_mt);
1554 set_except_vector(26, handle_dsp);
1557 /* Special exception: R4[04]00 uses also the divec space. */
1558 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1559 else if (cpu_has_4kex)
1560 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1562 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1565 #ifdef CONFIG_MIPS32_COMPAT
1569 flush_icache_range(ebase, ebase + 0x400);
1570 flush_tlb_handlers();