2 * GE Fanuc SBC610 Device Tree Source
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
25 compatible = "gef,sbc610";
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xf8005000 0x1000>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
88 compatible = "gef,fpga-regs";
92 #interrupt-cells = <1>;
94 compatible = "gef,fpga-pic";
95 reg = <0x4 0x4000 0x20>;
98 interrupt-parent = <&mpic>;
101 gef_gpio: gpio@7,14000 {
103 compatible = "gef,sbc610-gpio";
104 reg = <0x7 0x14000 0x24>;
110 #address-cells = <1>;
112 #interrupt-cells = <2>;
114 compatible = "simple-bus";
115 ranges = <0x0 0xfef00000 0x00100000>;
116 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
117 bus-frequency = <33333333>;
120 #address-cells = <1>;
122 compatible = "fsl-i2c";
123 reg = <0x3000 0x100>;
124 interrupts = <0x2b 0x2>;
125 interrupt-parent = <&mpic>;
129 compatible = "epson,rx8581";
134 compatible = "dallas,ds1682";
140 #address-cells = <1>;
142 compatible = "fsl-i2c";
143 reg = <0x3100 0x100>;
144 interrupts = <0x2b 0x2>;
145 interrupt-parent = <&mpic>;
150 #address-cells = <1>;
152 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
154 ranges = <0x0 0x21100 0x200>;
157 compatible = "fsl,mpc8641-dma-channel",
158 "fsl,eloplus-dma-channel";
161 interrupt-parent = <&mpic>;
165 compatible = "fsl,mpc8641-dma-channel",
166 "fsl,eloplus-dma-channel";
169 interrupt-parent = <&mpic>;
173 compatible = "fsl,mpc8641-dma-channel",
174 "fsl,eloplus-dma-channel";
177 interrupt-parent = <&mpic>;
181 compatible = "fsl,mpc8641-dma-channel",
182 "fsl,eloplus-dma-channel";
185 interrupt-parent = <&mpic>;
191 #address-cells = <1>;
193 compatible = "fsl,gianfar-mdio";
194 reg = <0x24520 0x20>;
196 phy0: ethernet-phy@0 {
197 interrupt-parent = <&gef_pic>;
198 interrupts = <0x9 0x4>;
201 phy2: ethernet-phy@2 {
202 interrupt-parent = <&gef_pic>;
203 interrupts = <0x8 0x4>;
208 enet0: ethernet@24000 {
209 device_type = "network";
211 compatible = "gianfar";
212 reg = <0x24000 0x1000>;
213 local-mac-address = [ 00 00 00 00 00 00 ];
214 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
215 interrupt-parent = <&mpic>;
216 phy-handle = <&phy0>;
217 phy-connection-type = "gmii";
220 enet1: ethernet@26000 {
221 device_type = "network";
223 compatible = "gianfar";
224 reg = <0x26000 0x1000>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
227 interrupt-parent = <&mpic>;
228 phy-handle = <&phy2>;
229 phy-connection-type = "gmii";
232 serial0: serial@4500 {
234 device_type = "serial";
235 compatible = "ns16550";
236 reg = <0x4500 0x100>;
237 clock-frequency = <0>;
238 interrupts = <0x2a 0x2>;
239 interrupt-parent = <&mpic>;
242 serial1: serial@4600 {
244 device_type = "serial";
245 compatible = "ns16550";
246 reg = <0x4600 0x100>;
247 clock-frequency = <0>;
248 interrupts = <0x1c 0x2>;
249 interrupt-parent = <&mpic>;
253 clock-frequency = <0>;
254 interrupt-controller;
255 #address-cells = <0>;
256 #interrupt-cells = <2>;
257 reg = <0x40000 0x40000>;
258 compatible = "chrp,open-pic";
259 device_type = "open-pic";
262 global-utilities@e0000 {
263 compatible = "fsl,mpc8641-guts";
264 reg = <0xe0000 0x1000>;
269 pci0: pcie@fef08000 {
270 compatible = "fsl,mpc8641-pcie";
272 #interrupt-cells = <1>;
274 #address-cells = <3>;
275 reg = <0xfef08000 0x1000>;
276 bus-range = <0x0 0xff>;
277 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
278 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
279 clock-frequency = <33333333>;
280 interrupt-parent = <&mpic>;
281 interrupts = <0x18 0x2>;
282 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
284 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
285 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
286 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
287 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
293 #address-cells = <3>;
295 ranges = <0x02000000 0x0 0x80000000
296 0x02000000 0x0 0x80000000
299 0x01000000 0x0 0x00000000
300 0x01000000 0x0 0x00000000