2 * MPC8315E RDB Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,mpc8315erdb";
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <16384>;
39 i-cache-size = <16384>;
40 timebase-frequency = <0>; // from bootloader
41 bus-frequency = <0>; // from bootloader
42 clock-frequency = <0>; // from bootloader
47 device_type = "memory";
48 reg = <0x00000000 0x08000000>; // 128MB at 0
54 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00002000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
79 compatible = "fsl,mpc8315-fcm-nand",
81 reg = <0x1 0x0 0x2000>;
89 reg = <0x100000 0x300000>;
92 reg = <0x400000 0x1c00000>;
101 compatible = "fsl,mpc8315-immr", "simple-bus";
102 ranges = <0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
113 #address-cells = <1>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <14 0x8>;
119 interrupt-parent = <&ipic>;
122 compatible = "dallas,ds1339";
128 compatible = "fsl,mc9s08qg8-mpc8315erdb",
129 "fsl,mcu-mpc8349emitx";
137 compatible = "fsl,spi";
138 reg = <0x7000 0x1000>;
139 interrupts = <16 0x8>;
140 interrupt-parent = <&ipic>;
145 #address-cells = <1>;
147 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
149 ranges = <0 0x8100 0x1a8>;
150 interrupt-parent = <&ipic>;
154 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
157 interrupt-parent = <&ipic>;
161 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
164 interrupt-parent = <&ipic>;
168 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
171 interrupt-parent = <&ipic>;
175 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
178 interrupt-parent = <&ipic>;
184 compatible = "fsl-usb2-dr";
185 reg = <0x23000 0x1000>;
186 #address-cells = <1>;
188 interrupt-parent = <&ipic>;
189 interrupts = <38 0x8>;
194 #address-cells = <1>;
196 compatible = "fsl,gianfar-mdio";
197 reg = <0x24520 0x20>;
198 phy0: ethernet-phy@0 {
199 interrupt-parent = <&ipic>;
200 interrupts = <20 0x8>;
202 device_type = "ethernet-phy";
204 phy1: ethernet-phy@1 {
205 interrupt-parent = <&ipic>;
206 interrupts = <19 0x8>;
208 device_type = "ethernet-phy";
212 device_type = "tbi-phy";
217 #address-cells = <1>;
219 compatible = "fsl,gianfar-tbi";
220 reg = <0x25520 0x20>;
224 device_type = "tbi-phy";
229 enet0: ethernet@24000 {
231 device_type = "network";
233 compatible = "gianfar";
234 reg = <0x24000 0x1000>;
235 local-mac-address = [ 00 00 00 00 00 00 ];
236 interrupts = <32 0x8 33 0x8 34 0x8>;
237 interrupt-parent = <&ipic>;
238 tbi-handle = <&tbi0>;
239 phy-handle = < &phy0 >;
242 enet1: ethernet@25000 {
244 device_type = "network";
246 compatible = "gianfar";
247 reg = <0x25000 0x1000>;
248 local-mac-address = [ 00 00 00 00 00 00 ];
249 interrupts = <35 0x8 36 0x8 37 0x8>;
250 interrupt-parent = <&ipic>;
251 tbi-handle = <&tbi1>;
252 phy-handle = < &phy1 >;
255 serial0: serial@4500 {
257 device_type = "serial";
258 compatible = "ns16550";
259 reg = <0x4500 0x100>;
260 clock-frequency = <133333333>;
261 interrupts = <9 0x8>;
262 interrupt-parent = <&ipic>;
265 serial1: serial@4600 {
267 device_type = "serial";
268 compatible = "ns16550";
269 reg = <0x4600 0x100>;
270 clock-frequency = <133333333>;
271 interrupts = <10 0x8>;
272 interrupt-parent = <&ipic>;
276 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
277 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
279 reg = <0x30000 0x10000>;
280 interrupts = <11 0x8>;
281 interrupt-parent = <&ipic>;
282 fsl,num-channels = <4>;
283 fsl,channel-fifo-len = <24>;
284 fsl,exec-units-mask = <0x97c>;
285 fsl,descriptor-types-mask = <0x3ab0abf>;
289 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
290 reg = <0x18000 0x1000>;
292 interrupts = <44 0x8>;
293 interrupt-parent = <&ipic>;
297 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
298 reg = <0x19000 0x1000>;
300 interrupts = <45 0x8>;
301 interrupt-parent = <&ipic>;
305 * interrupts cell = <intr #, sense>
306 * sense values match linux IORESOURCE_IRQ_* defines:
307 * sense == 8: Level, low assertion
308 * sense == 2: Edge, high-to-low change
310 ipic: interrupt-controller@700 {
311 interrupt-controller;
312 #address-cells = <0>;
313 #interrupt-cells = <2>;
315 device_type = "ipic";
320 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
322 /* IDSEL 0x0E -mini PCI */
323 0x7000 0x0 0x0 0x1 &ipic 18 0x8
324 0x7000 0x0 0x0 0x2 &ipic 18 0x8
325 0x7000 0x0 0x0 0x3 &ipic 18 0x8
326 0x7000 0x0 0x0 0x4 &ipic 18 0x8
328 /* IDSEL 0x0F -mini PCI */
329 0x7800 0x0 0x0 0x1 &ipic 17 0x8
330 0x7800 0x0 0x0 0x2 &ipic 17 0x8
331 0x7800 0x0 0x0 0x3 &ipic 17 0x8
332 0x7800 0x0 0x0 0x4 &ipic 17 0x8
334 /* IDSEL 0x10 - PCI slot */
335 0x8000 0x0 0x0 0x1 &ipic 48 0x8
336 0x8000 0x0 0x0 0x2 &ipic 17 0x8
337 0x8000 0x0 0x0 0x3 &ipic 48 0x8
338 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
339 interrupt-parent = <&ipic>;
340 interrupts = <66 0x8>;
341 bus-range = <0x0 0x0>;
342 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
343 0x42000000 0 0x80000000 0x80000000 0 0x10000000
344 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
345 clock-frequency = <66666666>;
346 #interrupt-cells = <1>;
348 #address-cells = <3>;
349 reg = <0xe0008500 0x100 /* internal registers */
350 0xe0008300 0x8>; /* config space access registers */
351 compatible = "fsl,mpc8349-pci";
355 pci1: pcie@e0009000 {
356 #address-cells = <3>;
358 #interrupt-cells = <1>;
360 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
361 reg = <0xe0009000 0x00001000>;
362 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
363 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
365 interrupt-map-mask = <0xf800 0 0 7>;
366 interrupt-map = <0 0 0 1 &ipic 1 8
370 clock-frequency = <0>;
373 #address-cells = <3>;
377 ranges = <0x02000000 0 0xa0000000
378 0x02000000 0 0xa0000000
380 0x01000000 0 0x00000000
381 0x01000000 0 0x00000000
386 pci2: pcie@e000a000 {
387 #address-cells = <3>;
389 #interrupt-cells = <1>;
391 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
392 reg = <0xe000a000 0x00001000>;
393 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
394 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
396 interrupt-map-mask = <0xf800 0 0 7>;
397 interrupt-map = <0 0 0 1 &ipic 2 8
401 clock-frequency = <0>;
404 #address-cells = <3>;
408 ranges = <0x02000000 0 0xc0000000
409 0x02000000 0 0xc0000000
411 0x01000000 0 0x00000000
412 0x01000000 0 0x00000000