2 * MPC8360E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 /memreserve/ 00000000 1000000;
21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <32768>; // L1, 32K
43 i-cache-size = <32768>; // L1, 32K
44 timebase-frequency = <66000000>;
45 bus-frequency = <264000000>;
46 clock-frequency = <528000000>;
51 device_type = "memory";
52 reg = <0x00000000 0x10000000>;
56 device_type = "board-control";
57 reg = <0xf8000000 0x8000>;
64 ranges = <0x0 0xe0000000 0x00100000>;
65 reg = <0xe0000000 0x00000200>;
66 bus-frequency = <264000000>;
69 device_type = "watchdog";
70 compatible = "mpc83xx_wdt";
78 compatible = "fsl-i2c";
80 interrupts = <14 0x8>;
81 interrupt-parent = <&ipic>;
85 compatible = "dallas,ds1374";
94 compatible = "fsl-i2c";
96 interrupts = <15 0x8>;
97 interrupt-parent = <&ipic>;
101 serial0: serial@4500 {
103 device_type = "serial";
104 compatible = "ns16550";
105 reg = <0x4500 0x100>;
106 clock-frequency = <264000000>;
107 interrupts = <9 0x8>;
108 interrupt-parent = <&ipic>;
111 serial1: serial@4600 {
113 device_type = "serial";
114 compatible = "ns16550";
115 reg = <0x4600 0x100>;
116 clock-frequency = <264000000>;
117 interrupts = <10 0x8>;
118 interrupt-parent = <&ipic>;
122 #address-cells = <1>;
124 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
126 ranges = <0 0x8100 0x1a8>;
127 interrupt-parent = <&ipic>;
131 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
133 interrupt-parent = <&ipic>;
137 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
139 interrupt-parent = <&ipic>;
143 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
145 interrupt-parent = <&ipic>;
149 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
151 interrupt-parent = <&ipic>;
157 compatible = "fsl,sec2.0";
158 reg = <0x30000 0x10000>;
159 interrupts = <11 0x8>;
160 interrupt-parent = <&ipic>;
161 fsl,num-channels = <4>;
162 fsl,channel-fifo-len = <24>;
163 fsl,exec-units-mask = <0x7e>;
164 fsl,descriptor-types-mask = <0x01010ebf>;
168 interrupt-controller;
169 #address-cells = <0>;
170 #interrupt-cells = <2>;
172 device_type = "ipic";
176 reg = <0x1400 0x100>;
177 device_type = "par_io";
182 /* port pin dir open_drain assignment has_irq */
183 0 3 1 0 1 0 /* TxD0 */
184 0 4 1 0 1 0 /* TxD1 */
185 0 5 1 0 1 0 /* TxD2 */
186 0 6 1 0 1 0 /* TxD3 */
187 1 6 1 0 3 0 /* TxD4 */
188 1 7 1 0 1 0 /* TxD5 */
189 1 9 1 0 2 0 /* TxD6 */
190 1 10 1 0 2 0 /* TxD7 */
191 0 9 2 0 1 0 /* RxD0 */
192 0 10 2 0 1 0 /* RxD1 */
193 0 11 2 0 1 0 /* RxD2 */
194 0 12 2 0 1 0 /* RxD3 */
195 0 13 2 0 1 0 /* RxD4 */
196 1 1 2 0 2 0 /* RxD5 */
197 1 0 2 0 2 0 /* RxD6 */
198 1 4 2 0 2 0 /* RxD7 */
199 0 7 1 0 1 0 /* TX_EN */
200 0 8 1 0 1 0 /* TX_ER */
201 0 15 2 0 1 0 /* RX_DV */
202 0 16 2 0 1 0 /* RX_ER */
203 0 0 2 0 1 0 /* RX_CLK */
204 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
205 2 8 2 0 1 0>; /* GTX125 - CLK9 */
209 /* port pin dir open_drain assignment has_irq */
210 0 17 1 0 1 0 /* TxD0 */
211 0 18 1 0 1 0 /* TxD1 */
212 0 19 1 0 1 0 /* TxD2 */
213 0 20 1 0 1 0 /* TxD3 */
214 1 2 1 0 1 0 /* TxD4 */
215 1 3 1 0 2 0 /* TxD5 */
216 1 5 1 0 3 0 /* TxD6 */
217 1 8 1 0 3 0 /* TxD7 */
218 0 23 2 0 1 0 /* RxD0 */
219 0 24 2 0 1 0 /* RxD1 */
220 0 25 2 0 1 0 /* RxD2 */
221 0 26 2 0 1 0 /* RxD3 */
222 0 27 2 0 1 0 /* RxD4 */
223 1 12 2 0 2 0 /* RxD5 */
224 1 13 2 0 3 0 /* RxD6 */
225 1 11 2 0 2 0 /* RxD7 */
226 0 21 1 0 1 0 /* TX_EN */
227 0 22 1 0 1 0 /* TX_ER */
228 0 29 2 0 1 0 /* RX_DV */
229 0 30 2 0 1 0 /* RX_ER */
230 0 31 2 0 1 0 /* RX_CLK */
231 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
232 2 3 2 0 1 0 /* GTX125 - CLK4 */
233 0 1 3 0 2 0 /* MDIO */
234 0 2 1 0 1 0>; /* MDC */
241 #address-cells = <1>;
244 compatible = "fsl,qe";
245 ranges = <0x0 0xe0100000 0x00100000>;
246 reg = <0xe0100000 0x480>;
248 bus-frequency = <396000000>;
251 #address-cells = <1>;
253 compatible = "fsl,qe-muram", "fsl,cpm-muram";
254 ranges = <0x0 0x00010000 0x0000c000>;
257 compatible = "fsl,qe-muram-data",
258 "fsl,cpm-muram-data";
265 compatible = "fsl,spi";
268 interrupt-parent = <&qeic>;
274 compatible = "fsl,spi";
277 interrupt-parent = <&qeic>;
282 compatible = "qe_udc";
283 reg = <0x6c0 0x40 0x8b00 0x100>;
285 interrupt-parent = <&qeic>;
290 device_type = "network";
291 compatible = "ucc_geth";
293 reg = <0x2000 0x200>;
295 interrupt-parent = <&qeic>;
296 local-mac-address = [ 00 00 00 00 00 00 ];
297 rx-clock-name = "none";
298 tx-clock-name = "clk9";
299 phy-handle = <&phy0>;
300 phy-connection-type = "rgmii-id";
301 pio-handle = <&pio1>;
305 device_type = "network";
306 compatible = "ucc_geth";
308 reg = <0x3000 0x200>;
310 interrupt-parent = <&qeic>;
311 local-mac-address = [ 00 00 00 00 00 00 ];
312 rx-clock-name = "none";
313 tx-clock-name = "clk4";
314 phy-handle = <&phy1>;
315 phy-connection-type = "rgmii-id";
316 pio-handle = <&pio2>;
320 #address-cells = <1>;
323 compatible = "fsl,ucc-mdio";
325 phy0: ethernet-phy@00 {
326 interrupt-parent = <&ipic>;
327 interrupts = <17 0x8>;
329 device_type = "ethernet-phy";
331 phy1: ethernet-phy@01 {
332 interrupt-parent = <&ipic>;
333 interrupts = <18 0x8>;
335 device_type = "ethernet-phy";
339 qeic: interrupt-controller@80 {
340 interrupt-controller;
341 compatible = "fsl,qe-ic";
342 #address-cells = <0>;
343 #interrupt-cells = <1>;
346 interrupts = <32 0x8 33 0x8>; // high:32 low:33
347 interrupt-parent = <&ipic>;
353 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
356 /* IDSEL 0x11 AD17 */
357 0x8800 0x0 0x0 0x1 &ipic 20 0x8
358 0x8800 0x0 0x0 0x2 &ipic 21 0x8
359 0x8800 0x0 0x0 0x3 &ipic 22 0x8
360 0x8800 0x0 0x0 0x4 &ipic 23 0x8
362 /* IDSEL 0x12 AD18 */
363 0x9000 0x0 0x0 0x1 &ipic 22 0x8
364 0x9000 0x0 0x0 0x2 &ipic 23 0x8
365 0x9000 0x0 0x0 0x3 &ipic 20 0x8
366 0x9000 0x0 0x0 0x4 &ipic 21 0x8
368 /* IDSEL 0x13 AD19 */
369 0x9800 0x0 0x0 0x1 &ipic 23 0x8
370 0x9800 0x0 0x0 0x2 &ipic 20 0x8
371 0x9800 0x0 0x0 0x3 &ipic 21 0x8
372 0x9800 0x0 0x0 0x4 &ipic 22 0x8
375 0xa800 0x0 0x0 0x1 &ipic 20 0x8
376 0xa800 0x0 0x0 0x2 &ipic 21 0x8
377 0xa800 0x0 0x0 0x3 &ipic 22 0x8
378 0xa800 0x0 0x0 0x4 &ipic 23 0x8
381 0xb000 0x0 0x0 0x1 &ipic 23 0x8
382 0xb000 0x0 0x0 0x2 &ipic 20 0x8
383 0xb000 0x0 0x0 0x3 &ipic 21 0x8
384 0xb000 0x0 0x0 0x4 &ipic 22 0x8
387 0xb800 0x0 0x0 0x1 &ipic 22 0x8
388 0xb800 0x0 0x0 0x2 &ipic 23 0x8
389 0xb800 0x0 0x0 0x3 &ipic 20 0x8
390 0xb800 0x0 0x0 0x4 &ipic 21 0x8
393 0xc000 0x0 0x0 0x1 &ipic 21 0x8
394 0xc000 0x0 0x0 0x2 &ipic 22 0x8
395 0xc000 0x0 0x0 0x3 &ipic 23 0x8
396 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
397 interrupt-parent = <&ipic>;
398 interrupts = <66 0x8>;
400 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
401 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
402 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
403 clock-frequency = <66666666>;
404 #interrupt-cells = <1>;
406 #address-cells = <3>;
407 reg = <0xe0008500 0x100>;
408 compatible = "fsl,mpc8349-pci";