2 * MPC8377E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,mpc8377emds";
16 compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
41 clock-frequency = <0>;
46 device_type = "memory";
47 reg = <0x00000000 0x20000000>; // 512MB at 0
53 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
54 reg = <0xe0005000 0x1000>;
55 interrupts = <77 0x8>;
56 interrupt-parent = <&ipic>;
58 // booting from NOR flash
59 ranges = <0 0x0 0xfe000000 0x02000000
60 1 0x0 0xf8000000 0x00008000
61 3 0x0 0xe0600000 0x00008000>;
66 compatible = "cfi-flash";
67 reg = <0 0x0 0x2000000>;
77 reg = <0x100000 0x800000>;
81 reg = <0x1d00000 0x200000>;
85 reg = <0x1f00000 0x100000>;
91 compatible = "fsl,mpc837xmds-bcsr";
97 compatible = "fsl,mpc8377-fcm-nand",
102 reg = <0x0 0x100000>;
107 reg = <0x100000 0x300000>;
111 reg = <0x400000 0x1c00000>;
117 #address-cells = <1>;
120 compatible = "simple-bus";
121 ranges = <0x0 0xe0000000 0x00100000>;
122 reg = <0xe0000000 0x00000200>;
126 compatible = "mpc83xx_wdt";
131 #address-cells = <1>;
134 compatible = "fsl-i2c";
135 reg = <0x3000 0x100>;
136 interrupts = <14 0x8>;
137 interrupt-parent = <&ipic>;
141 compatible = "dallas,ds1374";
143 interrupts = <19 0x8>;
144 interrupt-parent = <&ipic>;
149 #address-cells = <1>;
152 compatible = "fsl-i2c";
153 reg = <0x3100 0x100>;
154 interrupts = <15 0x8>;
155 interrupt-parent = <&ipic>;
161 compatible = "fsl,spi";
162 reg = <0x7000 0x1000>;
163 interrupts = <16 0x8>;
164 interrupt-parent = <&ipic>;
169 compatible = "fsl-usb2-dr";
170 reg = <0x23000 0x1000>;
171 #address-cells = <1>;
173 interrupt-parent = <&ipic>;
174 interrupts = <38 0x8>;
180 #address-cells = <1>;
182 compatible = "fsl,gianfar-mdio";
183 reg = <0x24520 0x20>;
184 phy2: ethernet-phy@2 {
185 interrupt-parent = <&ipic>;
186 interrupts = <17 0x8>;
188 device_type = "ethernet-phy";
190 phy3: ethernet-phy@3 {
191 interrupt-parent = <&ipic>;
192 interrupts = <18 0x8>;
194 device_type = "ethernet-phy";
198 device_type = "tbi-phy";
203 #address-cells = <1>;
205 compatible = "fsl,gianfar-tbi";
206 reg = <0x25520 0x20>;
210 device_type = "tbi-phy";
215 enet0: ethernet@24000 {
217 device_type = "network";
219 compatible = "gianfar";
220 reg = <0x24000 0x1000>;
221 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <32 0x8 33 0x8 34 0x8>;
223 phy-connection-type = "mii";
224 interrupt-parent = <&ipic>;
225 tbi-handle = <&tbi0>;
226 phy-handle = <&phy2>;
229 enet1: ethernet@25000 {
231 device_type = "network";
233 compatible = "gianfar";
234 reg = <0x25000 0x1000>;
235 local-mac-address = [ 00 00 00 00 00 00 ];
236 interrupts = <35 0x8 36 0x8 37 0x8>;
237 phy-connection-type = "mii";
238 interrupt-parent = <&ipic>;
239 tbi-handle = <&tbi1>;
240 phy-handle = <&phy3>;
243 serial0: serial@4500 {
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4500 0x100>;
248 clock-frequency = <0>;
249 interrupts = <9 0x8>;
250 interrupt-parent = <&ipic>;
253 serial1: serial@4600 {
255 device_type = "serial";
256 compatible = "ns16550";
257 reg = <0x4600 0x100>;
258 clock-frequency = <0>;
259 interrupts = <10 0x8>;
260 interrupt-parent = <&ipic>;
264 #address-cells = <1>;
266 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
268 ranges = <0 0x8100 0x1a8>;
269 interrupt-parent = <&ipic>;
270 interrupts = <0x47 8>;
273 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
276 interrupt-parent = <&ipic>;
277 interrupts = <0x47 8>;
280 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
283 interrupt-parent = <&ipic>;
284 interrupts = <0x47 8>;
287 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
290 interrupt-parent = <&ipic>;
291 interrupts = <0x47 8>;
294 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
297 interrupt-parent = <&ipic>;
298 interrupts = <0x47 8>;
303 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
304 "fsl,sec2.1", "fsl,sec2.0";
305 reg = <0x30000 0x10000>;
306 interrupts = <11 0x8>;
307 interrupt-parent = <&ipic>;
308 fsl,num-channels = <4>;
309 fsl,channel-fifo-len = <24>;
310 fsl,exec-units-mask = <0x9fe>;
311 fsl,descriptor-types-mask = <0x3ab0ebf>;
316 compatible = "fsl,esdhc";
317 reg = <0x2e000 0x1000>;
318 interrupts = <42 0x8>;
319 interrupt-parent = <&ipic>;
323 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
324 reg = <0x18000 0x1000>;
325 interrupts = <44 0x8>;
326 interrupt-parent = <&ipic>;
330 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
331 reg = <0x19000 0x1000>;
332 interrupts = <45 0x8>;
333 interrupt-parent = <&ipic>;
337 * interrupts cell = <intr #, sense>
338 * sense values match linux IORESOURCE_IRQ_* defines:
339 * sense == 8: Level, low assertion
340 * sense == 2: Edge, high-to-low change
343 compatible = "fsl,ipic";
344 interrupt-controller;
345 #address-cells = <0>;
346 #interrupt-cells = <2>;
353 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
357 0x8800 0x0 0x0 0x1 &ipic 20 0x8
358 0x8800 0x0 0x0 0x2 &ipic 21 0x8
359 0x8800 0x0 0x0 0x3 &ipic 22 0x8
360 0x8800 0x0 0x0 0x4 &ipic 23 0x8
363 0x9000 0x0 0x0 0x1 &ipic 22 0x8
364 0x9000 0x0 0x0 0x2 &ipic 23 0x8
365 0x9000 0x0 0x0 0x3 &ipic 20 0x8
366 0x9000 0x0 0x0 0x4 &ipic 21 0x8
369 0x9800 0x0 0x0 0x1 &ipic 23 0x8
370 0x9800 0x0 0x0 0x2 &ipic 20 0x8
371 0x9800 0x0 0x0 0x3 &ipic 21 0x8
372 0x9800 0x0 0x0 0x4 &ipic 22 0x8
375 0xa800 0x0 0x0 0x1 &ipic 20 0x8
376 0xa800 0x0 0x0 0x2 &ipic 21 0x8
377 0xa800 0x0 0x0 0x3 &ipic 22 0x8
378 0xa800 0x0 0x0 0x4 &ipic 23 0x8
381 0xb000 0x0 0x0 0x1 &ipic 23 0x8
382 0xb000 0x0 0x0 0x2 &ipic 20 0x8
383 0xb000 0x0 0x0 0x3 &ipic 21 0x8
384 0xb000 0x0 0x0 0x4 &ipic 22 0x8
387 0xb800 0x0 0x0 0x1 &ipic 22 0x8
388 0xb800 0x0 0x0 0x2 &ipic 23 0x8
389 0xb800 0x0 0x0 0x3 &ipic 20 0x8
390 0xb800 0x0 0x0 0x4 &ipic 21 0x8
393 0xc000 0x0 0x0 0x1 &ipic 21 0x8
394 0xc000 0x0 0x0 0x2 &ipic 22 0x8
395 0xc000 0x0 0x0 0x3 &ipic 23 0x8
396 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
397 interrupt-parent = <&ipic>;
398 interrupts = <66 0x8>;
399 bus-range = <0x0 0x0>;
400 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
401 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
402 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
403 clock-frequency = <0>;
404 #interrupt-cells = <1>;
406 #address-cells = <3>;
407 reg = <0xe0008500 0x100 /* internal registers */
408 0xe0008300 0x8>; /* config space access registers */
409 compatible = "fsl,mpc8349-pci";