2 * MPC8377E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,mpc8377emds";
16 compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
55 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
60 // booting from NOR flash
61 ranges = <0 0x0 0xfe000000 0x02000000
62 1 0x0 0xf8000000 0x00008000
63 3 0x0 0xe0600000 0x00008000>;
68 compatible = "cfi-flash";
69 reg = <0 0x0 0x2000000>;
79 reg = <0x100000 0x800000>;
83 reg = <0x1d00000 0x200000>;
87 reg = <0x1f00000 0x100000>;
93 compatible = "fsl,mpc837xmds-bcsr";
99 compatible = "fsl,mpc8377-fcm-nand",
101 reg = <3 0x0 0x8000>;
104 reg = <0x0 0x100000>;
109 reg = <0x100000 0x300000>;
113 reg = <0x400000 0x1c00000>;
119 #address-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0x0 0xe0000000 0x00100000>;
124 reg = <0xe0000000 0x00000200>;
128 compatible = "mpc83xx_wdt";
133 #address-cells = <1>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <14 0x8>;
139 interrupt-parent = <&ipic>;
143 compatible = "dallas,ds1374";
145 interrupts = <19 0x8>;
146 interrupt-parent = <&ipic>;
151 #address-cells = <1>;
154 compatible = "fsl-i2c";
155 reg = <0x3100 0x100>;
156 interrupts = <15 0x8>;
157 interrupt-parent = <&ipic>;
163 compatible = "fsl,spi";
164 reg = <0x7000 0x1000>;
165 interrupts = <16 0x8>;
166 interrupt-parent = <&ipic>;
171 compatible = "fsl-usb2-dr";
172 reg = <0x23000 0x1000>;
173 #address-cells = <1>;
175 interrupt-parent = <&ipic>;
176 interrupts = <38 0x8>;
182 #address-cells = <1>;
184 compatible = "fsl,gianfar-mdio";
185 reg = <0x24520 0x20>;
186 phy2: ethernet-phy@2 {
187 interrupt-parent = <&ipic>;
188 interrupts = <17 0x8>;
190 device_type = "ethernet-phy";
192 phy3: ethernet-phy@3 {
193 interrupt-parent = <&ipic>;
194 interrupts = <18 0x8>;
196 device_type = "ethernet-phy";
200 device_type = "tbi-phy";
205 #address-cells = <1>;
207 compatible = "fsl,gianfar-tbi";
208 reg = <0x25520 0x20>;
212 device_type = "tbi-phy";
217 enet0: ethernet@24000 {
219 device_type = "network";
221 compatible = "gianfar";
222 reg = <0x24000 0x1000>;
223 local-mac-address = [ 00 00 00 00 00 00 ];
224 interrupts = <32 0x8 33 0x8 34 0x8>;
225 phy-connection-type = "mii";
226 interrupt-parent = <&ipic>;
227 tbi-handle = <&tbi0>;
228 phy-handle = <&phy2>;
231 enet1: ethernet@25000 {
233 device_type = "network";
235 compatible = "gianfar";
236 reg = <0x25000 0x1000>;
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 interrupts = <35 0x8 36 0x8 37 0x8>;
239 phy-connection-type = "mii";
240 interrupt-parent = <&ipic>;
241 tbi-handle = <&tbi1>;
242 phy-handle = <&phy3>;
245 serial0: serial@4500 {
247 device_type = "serial";
248 compatible = "ns16550";
249 reg = <0x4500 0x100>;
250 clock-frequency = <0>;
251 interrupts = <9 0x8>;
252 interrupt-parent = <&ipic>;
255 serial1: serial@4600 {
257 device_type = "serial";
258 compatible = "ns16550";
259 reg = <0x4600 0x100>;
260 clock-frequency = <0>;
261 interrupts = <10 0x8>;
262 interrupt-parent = <&ipic>;
266 #address-cells = <1>;
268 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
270 ranges = <0 0x8100 0x1a8>;
271 interrupt-parent = <&ipic>;
272 interrupts = <0x47 8>;
275 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
278 interrupt-parent = <&ipic>;
279 interrupts = <0x47 8>;
282 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
285 interrupt-parent = <&ipic>;
286 interrupts = <0x47 8>;
289 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
292 interrupt-parent = <&ipic>;
293 interrupts = <0x47 8>;
296 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
299 interrupt-parent = <&ipic>;
300 interrupts = <0x47 8>;
305 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
306 "fsl,sec2.1", "fsl,sec2.0";
307 reg = <0x30000 0x10000>;
308 interrupts = <11 0x8>;
309 interrupt-parent = <&ipic>;
310 fsl,num-channels = <4>;
311 fsl,channel-fifo-len = <24>;
312 fsl,exec-units-mask = <0x9fe>;
313 fsl,descriptor-types-mask = <0x3ab0ebf>;
317 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
318 reg = <0x2e000 0x1000>;
319 interrupts = <42 0x8>;
320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
326 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
327 reg = <0x18000 0x1000>;
328 interrupts = <44 0x8>;
329 interrupt-parent = <&ipic>;
333 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
334 reg = <0x19000 0x1000>;
335 interrupts = <45 0x8>;
336 interrupt-parent = <&ipic>;
340 * interrupts cell = <intr #, sense>
341 * sense values match linux IORESOURCE_IRQ_* defines:
342 * sense == 8: Level, low assertion
343 * sense == 2: Edge, high-to-low change
346 compatible = "fsl,ipic";
347 interrupt-controller;
348 #address-cells = <0>;
349 #interrupt-cells = <2>;
356 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 0x8800 0x0 0x0 0x1 &ipic 20 0x8
361 0x8800 0x0 0x0 0x2 &ipic 21 0x8
362 0x8800 0x0 0x0 0x3 &ipic 22 0x8
363 0x8800 0x0 0x0 0x4 &ipic 23 0x8
366 0x9000 0x0 0x0 0x1 &ipic 22 0x8
367 0x9000 0x0 0x0 0x2 &ipic 23 0x8
368 0x9000 0x0 0x0 0x3 &ipic 20 0x8
369 0x9000 0x0 0x0 0x4 &ipic 21 0x8
372 0x9800 0x0 0x0 0x1 &ipic 23 0x8
373 0x9800 0x0 0x0 0x2 &ipic 20 0x8
374 0x9800 0x0 0x0 0x3 &ipic 21 0x8
375 0x9800 0x0 0x0 0x4 &ipic 22 0x8
378 0xa800 0x0 0x0 0x1 &ipic 20 0x8
379 0xa800 0x0 0x0 0x2 &ipic 21 0x8
380 0xa800 0x0 0x0 0x3 &ipic 22 0x8
381 0xa800 0x0 0x0 0x4 &ipic 23 0x8
384 0xb000 0x0 0x0 0x1 &ipic 23 0x8
385 0xb000 0x0 0x0 0x2 &ipic 20 0x8
386 0xb000 0x0 0x0 0x3 &ipic 21 0x8
387 0xb000 0x0 0x0 0x4 &ipic 22 0x8
390 0xb800 0x0 0x0 0x1 &ipic 22 0x8
391 0xb800 0x0 0x0 0x2 &ipic 23 0x8
392 0xb800 0x0 0x0 0x3 &ipic 20 0x8
393 0xb800 0x0 0x0 0x4 &ipic 21 0x8
396 0xc000 0x0 0x0 0x1 &ipic 21 0x8
397 0xc000 0x0 0x0 0x2 &ipic 22 0x8
398 0xc000 0x0 0x0 0x3 &ipic 23 0x8
399 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
400 interrupt-parent = <&ipic>;
401 interrupts = <66 0x8>;
402 bus-range = <0x0 0x0>;
403 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
404 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
405 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
406 clock-frequency = <0>;
407 #interrupt-cells = <1>;
409 #address-cells = <3>;
410 reg = <0xe0008500 0x100 /* internal registers */
411 0xe0008300 0x8>; /* config space access registers */
412 compatible = "fsl,mpc8349-pci";
416 pci1: pcie@e0009000 {
417 #address-cells = <3>;
419 #interrupt-cells = <1>;
421 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
422 reg = <0xe0009000 0x00001000>;
423 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
424 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
426 interrupt-map-mask = <0xf800 0 0 7>;
427 interrupt-map = <0 0 0 1 &ipic 1 8
431 clock-frequency = <0>;
434 #address-cells = <3>;
438 ranges = <0x02000000 0 0xa8000000
439 0x02000000 0 0xa8000000
441 0x01000000 0 0x00000000
442 0x01000000 0 0x00000000
447 pci2: pcie@e000a000 {
448 #address-cells = <3>;
450 #interrupt-cells = <1>;
452 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
453 reg = <0xe000a000 0x00001000>;
454 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
455 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
457 interrupt-map-mask = <0xf800 0 0 7>;
458 interrupt-map = <0 0 0 1 &ipic 2 8
462 clock-frequency = <0>;
465 #address-cells = <3>;
469 ranges = <0x02000000 0 0xc8000000
470 0x02000000 0 0xc8000000
472 0x01000000 0 0x00000000
473 0x01000000 0 0x00000000