arch/powerpc/boot/dts/mpc8378_mds.dts

   1 /*
   2  * MPC8378E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,mpc8378emds";
  16         compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8378@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;
  38                         i-cache-line-size = <32>;
  39                         d-cache-size = <32768>;
  40                         i-cache-size = <32768>;
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  50         };
  51
  52         localbus@e0005000 {
  53                 #address-cells = <2>;
  54                 #size-cells = <1>;
  55                 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
  56                 reg = <0xe0005000 0x1000>;
  57                 interrupts = <77 0x8>;
  58                 interrupt-parent = <&ipic>;
  59
  60                 // booting from NOR flash
  61                 ranges = <0 0x0 0xfe000000 0x02000000
  62                           1 0x0 0xf8000000 0x00008000
  63                           3 0x0 0xe0600000 0x00008000>;
  64
  65                 flash@0,0 {
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         compatible = "cfi-flash";
  69                         reg = <0 0x0 0x2000000>;
  70                         bank-width = <2>;
  71                         device-width = <1>;
  72
  73                         u-boot@0 {
  74                                 reg = <0x0 0x100000>;
  75                                 read-only;
  76                         };
  77
  78                         fs@100000 {
  79                                 reg = <0x100000 0x800000>;
  80                         };
  81
  82                         kernel@1d00000 {
  83                                 reg = <0x1d00000 0x200000>;
  84                         };
  85
  86                         dtb@1f00000 {
  87                                 reg = <0x1f00000 0x100000>;
  88                         };
  89                 };
  90
  91                 bcsr@1,0 {
  92                         reg = <1 0x0 0x8000>;
  93                         compatible = "fsl,mpc837xmds-bcsr";
  94                 };
  95
  96                 nand@3,0 {
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         compatible = "fsl,mpc8378-fcm-nand",
 100                                      "fsl,elbc-fcm-nand";
 101                         reg = <3 0x0 0x8000>;
 102
 103                         u-boot@0 {
 104                                 reg = <0x0 0x100000>;
 105                                 read-only;
 106                         };
 107
 108                         kernel@100000 {
 109                                 reg = <0x100000 0x300000>;
 110                         };
 111
 112                         fs@400000 {
 113                                 reg = <0x400000 0x1c00000>;
 114                         };
 115                 };
 116         };
 117
 118         soc@e0000000 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 device_type = "soc";
 122                 compatible = "simple-bus";
 123                 ranges = <0x0 0xe0000000 0x00100000>;
 124                 reg = <0xe0000000 0x00000200>;
 125                 bus-frequency = <0>;
 126
 127                 wdt@200 {
 128                         compatible = "mpc83xx_wdt";
 129                         reg = <0x200 0x100>;
 130                 };
 131
 132                 i2c@3000 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         cell-index = <0>;
 136                         compatible = "fsl-i2c";
 137                         reg = <0x3000 0x100>;
 138                         interrupts = <14 0x8>;
 139                         interrupt-parent = <&ipic>;
 140                         dfsrr;
 141
 142                         rtc@68 {
 143                                 compatible = "dallas,ds1374";
 144                                 reg = <0x68>;
 145                                 interrupts = <19 0x8>;
 146                                 interrupt-parent = <&ipic>;
 147                         };
 148                 };
 149
 150                 i2c@3100 {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         cell-index = <1>;
 154                         compatible = "fsl-i2c";
 155                         reg = <0x3100 0x100>;
 156                         interrupts = <15 0x8>;
 157                         interrupt-parent = <&ipic>;
 158                         dfsrr;
 159                 };
 160
 161                 spi@7000 {
 162                         cell-index = <0>;
 163                         compatible = "fsl,spi";
 164                         reg = <0x7000 0x1000>;
 165                         interrupts = <16 0x8>;
 166                         interrupt-parent = <&ipic>;
 167                         mode = "cpu";
 168                 };
 169
 170                 dma@82a8 {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
 174                         reg = <0x82a8 4>;
 175                         ranges = <0 0x8100 0x1a8>;
 176                         interrupt-parent = <&ipic>;
 177                         interrupts = <71 8>;
 178                         cell-index = <0>;
 179                         dma-channel@0 {
 180                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 181                                 reg = <0 0x80>;
 182                                 cell-index = <0>;
 183                                 interrupt-parent = <&ipic>;
 184                                 interrupts = <71 8>;
 185                         };
 186                         dma-channel@80 {
 187                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 188                                 reg = <0x80 0x80>;
 189                                 cell-index = <1>;
 190                                 interrupt-parent = <&ipic>;
 191                                 interrupts = <71 8>;
 192                         };
 193                         dma-channel@100 {
 194                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 195                                 reg = <0x100 0x80>;
 196                                 cell-index = <2>;
 197                                 interrupt-parent = <&ipic>;
 198                                 interrupts = <71 8>;
 199                         };
 200                         dma-channel@180 {
 201                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 202                                 reg = <0x180 0x28>;
 203                                 cell-index = <3>;
 204                                 interrupt-parent = <&ipic>;
 205                                 interrupts = <71 8>;
 206                         };
 207                 };
 208
 209                 usb@23000 {
 210                         compatible = "fsl-usb2-dr";
 211                         reg = <0x23000 0x1000>;
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         interrupt-parent = <&ipic>;
 215                         interrupts = <38 0x8>;
 216                         dr_mode = "host";
 217                         phy_type = "ulpi";
 218                 };
 219
 220                 mdio@24520 {
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         compatible = "fsl,gianfar-mdio";
 224                         reg = <0x24520 0x20>;
 225                         phy2: ethernet-phy@2 {
 226                                 interrupt-parent = <&ipic>;
 227                                 interrupts = <17 0x8>;
 228                                 reg = <0x2>;
 229                                 device_type = "ethernet-phy";
 230                         };
 231                         phy3: ethernet-phy@3 {
 232                                 interrupt-parent = <&ipic>;
 233                                 interrupts = <18 0x8>;
 234                                 reg = <0x3>;
 235                                 device_type = "ethernet-phy";
 236                         };
 237                         tbi0: tbi-phy@11 {
 238                                 reg = <0x11>;
 239                                 device_type = "tbi-phy";
 240                         };
 241                 };
 242
 243                 mdio@25520 {
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         compatible = "fsl,gianfar-tbi";
 247                         reg = <0x25520 0x20>;
 248
 249                         tbi1: tbi-phy@11 {
 250                                 reg = <0x11>;
 251                                 device_type = "tbi-phy";
 252                         };
 253                 };
 254
 255
 256                 enet0: ethernet@24000 {
 257                         cell-index = <0>;
 258                         device_type = "network";
 259                         model = "eTSEC";
 260                         compatible = "gianfar";
 261                         reg = <0x24000 0x1000>;
 262                         local-mac-address = [ 00 00 00 00 00 00 ];
 263                         interrupts = <32 0x8 33 0x8 34 0x8>;
 264                         phy-connection-type = "mii";
 265                         interrupt-parent = <&ipic>;
 266                         tbi-handle = <&tbi0>;
 267                         phy-handle = <&phy2>;
 268                 };
 269
 270                 enet1: ethernet@25000 {
 271                         cell-index = <1>;
 272                         device_type = "network";
 273                         model = "eTSEC";
 274                         compatible = "gianfar";
 275                         reg = <0x25000 0x1000>;
 276                         local-mac-address = [ 00 00 00 00 00 00 ];
 277                         interrupts = <35 0x8 36 0x8 37 0x8>;
 278                         phy-connection-type = "mii";
 279                         interrupt-parent = <&ipic>;
 280                         tbi-handle = <&tbi1>;
 281                         phy-handle = <&phy3>;
 282                 };
 283
 284                 serial0: serial@4500 {
 285                         cell-index = <0>;
 286                         device_type = "serial";
 287                         compatible = "ns16550";
 288                         reg = <0x4500 0x100>;
 289                         clock-frequency = <0>;
 290                         interrupts = <9 0x8>;
 291                         interrupt-parent = <&ipic>;
 292                 };
 293
 294                 serial1: serial@4600 {
 295                         cell-index = <1>;
 296                         device_type = "serial";
 297                         compatible = "ns16550";
 298                         reg = <0x4600 0x100>;
 299                         clock-frequency = <0>;
 300                         interrupts = <10 0x8>;
 301                         interrupt-parent = <&ipic>;
 302                 };
 303
 304                 crypto@30000 {
 305                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 306                                      "fsl,sec2.1", "fsl,sec2.0";
 307                         reg = <0x30000 0x10000>;
 308                         interrupts = <11 0x8>;
 309                         interrupt-parent = <&ipic>;
 310                         fsl,num-channels = <4>;
 311                         fsl,channel-fifo-len = <24>;
 312                         fsl,exec-units-mask = <0x9fe>;
 313                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 314                 };
 315
 316                 sdhci@2e000 {
 317                         compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
 318                         reg = <0x2e000 0x1000>;
 319                         interrupts = <42 0x8>;
 320                         interrupt-parent = <&ipic>;
 321                         /* Filled in by U-Boot */
 322                         clock-frequency = <0>;
 323                 };
 324
 325                 /* IPIC
 326                  * interrupts cell = <intr #, sense>
 327                  * sense values match linux IORESOURCE_IRQ_* defines:
 328                  * sense == 8: Level, low assertion
 329                  * sense == 2: Edge, high-to-low change
 330                  */
 331                 ipic: pic@700 {
 332                         compatible = "fsl,ipic";
 333                         interrupt-controller;
 334                         #address-cells = <0>;
 335                         #interrupt-cells = <2>;
 336                         reg = <0x700 0x100>;
 337                 };
 338         };
 339
 340         pci0: pci@e0008500 {
 341                 cell-index = <0>;
 342                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 343                 interrupt-map = <
 344
 345                                 /* IDSEL 0x11 */
 346                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 347                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 348                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 349                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 350
 351                                 /* IDSEL 0x12 */
 352                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 353                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 354                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 355                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 356
 357                                 /* IDSEL 0x13 */
 358                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 359                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 360                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 361                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 362
 363                                 /* IDSEL 0x15 */
 364                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 365                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 366                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 367                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 368
 369                                 /* IDSEL 0x16 */
 370                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 371                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 372                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 373                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 374
 375                                 /* IDSEL 0x17 */
 376                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 377                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 378                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 379                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 380
 381                                 /* IDSEL 0x18 */
 382                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 383                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 384                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 385                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 386                 interrupt-parent = <&ipic>;
 387                 interrupts = <66 0x8>;
 388                 bus-range = <0x0 0x0>;
 389                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 390                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 391                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 392                 clock-frequency = <0>;
 393                 #interrupt-cells = <1>;
 394                 #size-cells = <2>;
 395                 #address-cells = <3>;
 396                 reg = <0xe0008500 0x100         /* internal registers */
 397                        0xe0008300 0x8>;         /* config space access registers */
 398                 compatible = "fsl,mpc8349-pci";
 399                 device_type = "pci";
 400         };
 401
 402         pci1: pcie@e0009000 {
 403                 #address-cells = <3>;
 404                 #size-cells = <2>;
 405                 #interrupt-cells = <1>;
 406                 device_type = "pci";
 407                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
 408                 reg = <0xe0009000 0x00001000>;
 409                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 410                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 411                 bus-range = <0 255>;
 412                 interrupt-map-mask = <0xf800 0 0 7>;
 413                 interrupt-map = <0 0 0 1 &ipic 1 8
 414                                  0 0 0 2 &ipic 1 8
 415                                  0 0 0 3 &ipic 1 8
 416                                  0 0 0 4 &ipic 1 8>;
 417                 clock-frequency = <0>;
 418
 419                 pcie@0 {
 420                         #address-cells = <3>;
 421                         #size-cells = <2>;
 422                         device_type = "pci";
 423                         reg = <0 0 0 0 0>;
 424                         ranges = <0x02000000 0 0xa8000000
 425                                   0x02000000 0 0xa8000000
 426                                   0 0x10000000
 427                                   0x01000000 0 0x00000000
 428                                   0x01000000 0 0x00000000
 429                                   0 0x00800000>;
 430                 };
 431         };
 432
 433         pci2: pcie@e000a000 {
 434                 #address-cells = <3>;
 435                 #size-cells = <2>;
 436                 #interrupt-cells = <1>;
 437                 device_type = "pci";
 438                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
 439                 reg = <0xe000a000 0x00001000>;
 440                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 441                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 442                 bus-range = <0 255>;
 443                 interrupt-map-mask = <0xf800 0 0 7>;
 444                 interrupt-map = <0 0 0 1 &ipic 2 8
 445                                  0 0 0 2 &ipic 2 8
 446                                  0 0 0 3 &ipic 2 8
 447                                  0 0 0 4 &ipic 2 8>;
 448                 clock-frequency = <0>;
 449
 450                 pcie@0 {
 451                         #address-cells = <3>;
 452                         #size-cells = <2>;
 453                         device_type = "pci";
 454                         reg = <0 0 0 0 0>;
 455                         ranges = <0x02000000 0 0xc8000000
 456                                   0x02000000 0 0xc8000000
 457                                   0 0x10000000
 458                                   0x01000000 0 0x00000000
 459                                   0x01000000 0 0x00000000
 460                                   0 0x00800000>;
 461                 };
 462         };
 463 };