2 * MPC8548 CDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "MPC8548CDS", "MPC85xxCDS";
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
38 device_type = "memory";
39 reg = <00000000 08000000>; // 128M at 0x0
45 #interrupt-cells = <2>;
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M
51 memory-controller@2000 {
52 compatible = "fsl,8548-memory-controller";
54 interrupt-parent = <&mpic>;
58 l2-cache-controller@20000 {
59 compatible = "fsl,8548-l2-cache-controller";
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <80000>; // L2, 512K
63 interrupt-parent = <&mpic>;
69 compatible = "fsl-i2c";
72 interrupt-parent = <&mpic>;
80 compatible = "gianfar";
82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
86 device_type = "ethernet-phy";
88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
92 device_type = "ethernet-phy";
94 phy2: ethernet-phy@2 {
95 interrupt-parent = <&mpic>;
98 device_type = "ethernet-phy";
100 phy3: ethernet-phy@3 {
101 interrupt-parent = <&mpic>;
104 device_type = "ethernet-phy";
109 #address-cells = <1>;
111 device_type = "network";
113 compatible = "gianfar";
115 local-mac-address = [ 00 00 00 00 00 00 ];
116 interrupts = <1d 2 1e 2 22 2>;
117 interrupt-parent = <&mpic>;
118 phy-handle = <&phy0>;
122 #address-cells = <1>;
124 device_type = "network";
126 compatible = "gianfar";
128 local-mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <23 2 24 2 28 2>;
130 interrupt-parent = <&mpic>;
131 phy-handle = <&phy1>;
134 /* eTSEC 3/4 are currently broken
136 #address-cells = <1>;
138 device_type = "network";
140 compatible = "gianfar";
142 local-mac-address = [ 00 00 00 00 00 00 ];
143 interrupts = <1f 2 20 2 21 2>;
144 interrupt-parent = <&mpic>;
145 phy-handle = <&phy2>;
149 #address-cells = <1>;
151 device_type = "network";
153 compatible = "gianfar";
155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <25 2 26 2 27 2>;
157 interrupt-parent = <&mpic>;
158 phy-handle = <&phy3>;
163 device_type = "serial";
164 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot?
168 interrupt-parent = <&mpic>;
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot?
177 interrupt-parent = <&mpic>;
180 global-utilities@e0000 { //global utilities reg
181 compatible = "fsl,mpc8548-guts";
187 interrupt-map-mask = <1f800 0 0 7>;
189 /* IDSEL 0x4 (PCIX Slot 2) */
190 02000 0 0 1 &mpic 0 1
191 02000 0 0 2 &mpic 1 1
192 02000 0 0 3 &mpic 2 1
193 02000 0 0 4 &mpic 3 1
195 /* IDSEL 0x5 (PCIX Slot 3) */
196 02800 0 0 1 &mpic 1 1
197 02800 0 0 2 &mpic 2 1
198 02800 0 0 3 &mpic 3 1
199 02800 0 0 4 &mpic 0 1
201 /* IDSEL 0x6 (PCIX Slot 4) */
202 03000 0 0 1 &mpic 2 1
203 03000 0 0 2 &mpic 3 1
204 03000 0 0 3 &mpic 0 1
205 03000 0 0 4 &mpic 1 1
207 /* IDSEL 0x8 (PCIX Slot 5) */
208 04000 0 0 1 &mpic 0 1
209 04000 0 0 2 &mpic 1 1
210 04000 0 0 3 &mpic 2 1
211 04000 0 0 4 &mpic 3 1
213 /* IDSEL 0xC (Tsi310 bridge) */
214 06000 0 0 1 &mpic 0 1
215 06000 0 0 2 &mpic 1 1
216 06000 0 0 3 &mpic 2 1
217 06000 0 0 4 &mpic 3 1
219 /* IDSEL 0x14 (Slot 2) */
220 0a000 0 0 1 &mpic 0 1
221 0a000 0 0 2 &mpic 1 1
222 0a000 0 0 3 &mpic 2 1
223 0a000 0 0 4 &mpic 3 1
225 /* IDSEL 0x15 (Slot 3) */
226 0a800 0 0 1 &mpic 1 1
227 0a800 0 0 2 &mpic 2 1
228 0a800 0 0 3 &mpic 3 1
229 0a800 0 0 4 &mpic 0 1
231 /* IDSEL 0x16 (Slot 4) */
232 0b000 0 0 1 &mpic 2 1
233 0b000 0 0 2 &mpic 3 1
234 0b000 0 0 3 &mpic 0 1
235 0b000 0 0 4 &mpic 1 1
237 /* IDSEL 0x18 (Slot 5) */
238 0c000 0 0 1 &mpic 0 1
239 0c000 0 0 2 &mpic 1 1
240 0c000 0 0 3 &mpic 2 1
241 0c000 0 0 4 &mpic 3 1
243 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
244 0E000 0 0 1 &mpic 0 1
245 0E000 0 0 2 &mpic 1 1
246 0E000 0 0 3 &mpic 2 1
247 0E000 0 0 4 &mpic 3 1
249 /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
250 11000 0 0 1 &mpic 2 1
251 11000 0 0 2 &mpic 3 1
252 11000 0 0 3 &mpic 0 1
253 11000 0 0 4 &mpic 1 1
256 12000 0 0 1 &mpic 0 1
257 12000 0 0 2 &mpic 1 1
258 12000 0 0 3 &mpic 2 1
259 12000 0 0 4 &mpic 3 1>;
261 interrupt-parent = <&mpic>;
264 ranges = <02000000 0 80000000 80000000 0 10000000
265 01000000 0 00000000 e2000000 0 00800000>;
266 clock-frequency = <3f940aa>;
267 #interrupt-cells = <1>;
269 #address-cells = <3>;
271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
275 clock-frequency = <0>;
276 interrupt-controller;
277 device_type = "interrupt-controller";
278 reg = <12000 0 0 0 1>;
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
282 compatible = "chrp,iic";
285 interrupt-parent = <&pci1>;
290 interrupt-map-mask = <f800 0 0 7>;
297 a800 0 0 4 &mpic b 1>;
299 interrupt-parent = <&mpic>;
302 ranges = <02000000 0 90000000 90000000 0 10000000
303 01000000 0 00000000 e2800000 0 00800000>;
304 clock-frequency = <3f940aa>;
305 #interrupt-cells = <1>;
307 #address-cells = <3>;
309 compatible = "fsl,mpc8540-pci";
314 interrupt-map-mask = <f800 0 0 7>;
317 /* IDSEL 0x0 (PEX) */
318 00000 0 0 1 &mpic 0 1
319 00000 0 0 2 &mpic 1 1
320 00000 0 0 3 &mpic 2 1
321 00000 0 0 4 &mpic 3 1>;
323 interrupt-parent = <&mpic>;
326 ranges = <02000000 0 a0000000 a0000000 0 20000000
327 01000000 0 00000000 e3000000 0 08000000>;
328 clock-frequency = <1fca055>;
329 #interrupt-cells = <1>;
331 #address-cells = <3>;
333 compatible = "fsl,mpc8548-pcie";
338 clock-frequency = <0>;
339 interrupt-controller;
340 #address-cells = <0>;
341 #interrupt-cells = <2>;
344 compatible = "chrp,open-pic";
345 device_type = "open-pic";