2 * MPC8555 CDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "MPC8548CDS", "MPC85xxCDS";
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
38 device_type = "memory";
39 reg = <00000000 08000000>; // 128M at 0x0
45 #interrupt-cells = <2>;
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M
51 memory-controller@2000 {
52 compatible = "fsl,8548-memory-controller";
54 interrupt-parent = <&mpic>;
58 l2-cache-controller@20000 {
59 compatible = "fsl,8548-l2-cache-controller";
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <80000>; // L2, 512K
63 interrupt-parent = <&mpic>;
69 compatible = "fsl-i2c";
72 interrupt-parent = <&mpic>;
80 compatible = "gianfar";
82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
86 device_type = "ethernet-phy";
88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
92 device_type = "ethernet-phy";
94 phy2: ethernet-phy@2 {
95 interrupt-parent = <&mpic>;
98 device_type = "ethernet-phy";
100 phy3: ethernet-phy@3 {
101 interrupt-parent = <&mpic>;
104 device_type = "ethernet-phy";
109 #address-cells = <1>;
111 device_type = "network";
113 compatible = "gianfar";
115 local-mac-address = [ 00 00 00 00 00 00 ];
116 interrupts = <1d 2 1e 2 22 2>;
117 interrupt-parent = <&mpic>;
118 phy-handle = <&phy0>;
122 #address-cells = <1>;
124 device_type = "network";
126 compatible = "gianfar";
128 local-mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <23 2 24 2 28 2>;
130 interrupt-parent = <&mpic>;
131 phy-handle = <&phy1>;
134 /* eTSEC 3/4 are currently broken
136 #address-cells = <1>;
138 device_type = "network";
140 compatible = "gianfar";
142 local-mac-address = [ 00 00 00 00 00 00 ];
143 interrupts = <1f 2 20 2 21 2>;
144 interrupt-parent = <&mpic>;
145 phy-handle = <&phy2>;
149 #address-cells = <1>;
151 device_type = "network";
153 compatible = "gianfar";
155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <25 2 26 2 27 2>;
157 interrupt-parent = <&mpic>;
158 phy-handle = <&phy3>;
163 device_type = "serial";
164 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot?
168 interrupt-parent = <&mpic>;
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot?
177 interrupt-parent = <&mpic>;
180 global-utilities@e0000 { //global utilities reg
181 compatible = "fsl,mpc8548-guts";
187 interrupt-map-mask = <1f800 0 0 7>;
191 08000 0 0 1 &mpic 0 1
192 08000 0 0 2 &mpic 1 1
193 08000 0 0 3 &mpic 2 1
194 08000 0 0 4 &mpic 3 1
197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>;
235 ranges = <02000000 0 80000000 80000000 0 20000000
236 01000000 0 00000000 e2000000 0 00100000>;
237 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>;
240 #address-cells = <3>;
246 clock-frequency = <0>;
247 interrupt-controller;
248 device_type = "interrupt-controller";
249 reg = <19000 0 0 0 1>;
250 #address-cells = <0>;
251 #interrupt-cells = <2>;
253 compatible = "chrp,iic";
256 interrupt-parent = <&pci1>;
261 interrupt-map-mask = <f800 0 0 7>;
268 a800 0 0 4 &mpic b 1>;
269 interrupt-parent = <&mpic>;
272 ranges = <02000000 0 a0000000 a0000000 0 20000000
273 01000000 0 00000000 e3000000 0 00100000>;
274 clock-frequency = <3f940aa>;
275 #interrupt-cells = <1>;
277 #address-cells = <3>;
284 clock-frequency = <0>;
285 interrupt-controller;
286 #address-cells = <0>;
287 #interrupt-cells = <2>;
290 compatible = "chrp,open-pic";
291 device_type = "open-pic";