arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8548CDS";
  15         compatible = "MPC8548CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8548@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 08000000>;      // 128M at 0x0
  39         };
  40
  41         soc8548@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 device_type = "soc";
  45                 ranges = <00001000 e0001000 000ff000
  46                           80000000 80000000 10000000
  47                           e2000000 e2000000 00800000
  48                           90000000 90000000 10000000
  49                           e2800000 e2800000 00800000
  50                           a0000000 a0000000 20000000
  51                           e3000000 e3000000 01000000>;
  52                 reg = <e0000000 00001000>;      // CCSRBAR
  53                 bus-frequency = <0>;
  54
  55                 memory-controller@2000 {
  56                         compatible = "fsl,8548-memory-controller";
  57                         reg = <2000 1000>;
  58                         interrupt-parent = <&mpic>;
  59                         interrupts = <12 2>;
  60                 };
  61
  62                 l2-cache-controller@20000 {
  63                         compatible = "fsl,8548-l2-cache-controller";
  64                         reg = <20000 1000>;
  65                         cache-line-size = <20>; // 32 bytes
  66                         cache-size = <80000>;   // L2, 512K
  67                         interrupt-parent = <&mpic>;
  68                         interrupts = <10 2>;
  69                 };
  70
  71                 i2c@3000 {
  72                         device_type = "i2c";
  73                         compatible = "fsl-i2c";
  74                         reg = <3000 100>;
  75                         interrupts = <2b 2>;
  76                         interrupt-parent = <&mpic>;
  77                         dfsrr;
  78                 };
  79
  80                 mdio@24520 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                         device_type = "mdio";
  84                         compatible = "gianfar";
  85                         reg = <24520 20>;
  86                         phy0: ethernet-phy@0 {
  87                                 interrupt-parent = <&mpic>;
  88                                 interrupts = <5 1>;
  89                                 reg = <0>;
  90                                 device_type = "ethernet-phy";
  91                         };
  92                         phy1: ethernet-phy@1 {
  93                                 interrupt-parent = <&mpic>;
  94                                 interrupts = <5 1>;
  95                                 reg = <1>;
  96                                 device_type = "ethernet-phy";
  97                         };
  98                         phy2: ethernet-phy@2 {
  99                                 interrupt-parent = <&mpic>;
 100                                 interrupts = <5 1>;
 101                                 reg = <2>;
 102                                 device_type = "ethernet-phy";
 103                         };
 104                         phy3: ethernet-phy@3 {
 105                                 interrupt-parent = <&mpic>;
 106                                 interrupts = <5 1>;
 107                                 reg = <3>;
 108                                 device_type = "ethernet-phy";
 109                         };
 110                 };
 111
 112                 ethernet@24000 {
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         device_type = "network";
 116                         model = "eTSEC";
 117                         compatible = "gianfar";
 118                         reg = <24000 1000>;
 119                         local-mac-address = [ 00 00 00 00 00 00 ];
 120                         interrupts = <1d 2 1e 2 22 2>;
 121                         interrupt-parent = <&mpic>;
 122                         phy-handle = <&phy0>;
 123                 };
 124
 125                 ethernet@25000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         device_type = "network";
 129                         model = "eTSEC";
 130                         compatible = "gianfar";
 131                         reg = <25000 1000>;
 132                         local-mac-address = [ 00 00 00 00 00 00 ];
 133                         interrupts = <23 2 24 2 28 2>;
 134                         interrupt-parent = <&mpic>;
 135                         phy-handle = <&phy1>;
 136                 };
 137
 138 /* eTSEC 3/4 are currently broken
 139                 ethernet@26000 {
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         device_type = "network";
 143                         model = "eTSEC";
 144                         compatible = "gianfar";
 145                         reg = <26000 1000>;
 146                         local-mac-address = [ 00 00 00 00 00 00 ];
 147                         interrupts = <1f 2 20 2 21 2>;
 148                         interrupt-parent = <&mpic>;
 149                         phy-handle = <&phy2>;
 150                 };
 151
 152                 ethernet@27000 {
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         device_type = "network";
 156                         model = "eTSEC";
 157                         compatible = "gianfar";
 158                         reg = <27000 1000>;
 159                         local-mac-address = [ 00 00 00 00 00 00 ];
 160                         interrupts = <25 2 26 2 27 2>;
 161                         interrupt-parent = <&mpic>;
 162                         phy-handle = <&phy3>;
 163                 };
 164  */
 165
 166                 serial@4500 {
 167                         device_type = "serial";
 168                         compatible = "ns16550";
 169                         reg = <4500 100>;       // reg base, size
 170                         clock-frequency = <0>;  // should we fill in in uboot?
 171                         interrupts = <2a 2>;
 172                         interrupt-parent = <&mpic>;
 173                 };
 174
 175                 serial@4600 {
 176                         device_type = "serial";
 177                         compatible = "ns16550";
 178                         reg = <4600 100>;       // reg base, size
 179                         clock-frequency = <0>;  // should we fill in in uboot?
 180                         interrupts = <2a 2>;
 181                         interrupt-parent = <&mpic>;
 182                 };
 183
 184                 global-utilities@e0000 {        //global utilities reg
 185                         compatible = "fsl,mpc8548-guts";
 186                         reg = <e0000 1000>;
 187                         fsl,has-rstcr;
 188                 };
 189
 190                 pci@8000 {
 191                         interrupt-map-mask = <f800 0 0 7>;
 192                         interrupt-map = <
 193                                 /* IDSEL 0x4 (PCIX Slot 2) */
 194                                 02000 0 0 1 &mpic 0 1
 195                                 02000 0 0 2 &mpic 1 1
 196                                 02000 0 0 3 &mpic 2 1
 197                                 02000 0 0 4 &mpic 3 1
 198
 199                                 /* IDSEL 0x5 (PCIX Slot 3) */
 200                                 02800 0 0 1 &mpic 1 1
 201                                 02800 0 0 2 &mpic 2 1
 202                                 02800 0 0 3 &mpic 3 1
 203                                 02800 0 0 4 &mpic 0 1
 204
 205                                 /* IDSEL 0x6 (PCIX Slot 4) */
 206                                 03000 0 0 1 &mpic 2 1
 207                                 03000 0 0 2 &mpic 3 1
 208                                 03000 0 0 3 &mpic 0 1
 209                                 03000 0 0 4 &mpic 1 1
 210
 211                                 /* IDSEL 0x8 (PCIX Slot 5) */
 212                                 04000 0 0 1 &mpic 0 1
 213                                 04000 0 0 2 &mpic 1 1
 214                                 04000 0 0 3 &mpic 2 1
 215                                 04000 0 0 4 &mpic 3 1
 216
 217                                 /* IDSEL 0xC (Tsi310 bridge) */
 218                                 06000 0 0 1 &mpic 0 1
 219                                 06000 0 0 2 &mpic 1 1
 220                                 06000 0 0 3 &mpic 2 1
 221                                 06000 0 0 4 &mpic 3 1
 222
 223                                 /* IDSEL 0x14 (Slot 2) */
 224                                 0a000 0 0 1 &mpic 0 1
 225                                 0a000 0 0 2 &mpic 1 1
 226                                 0a000 0 0 3 &mpic 2 1
 227                                 0a000 0 0 4 &mpic 3 1
 228
 229                                 /* IDSEL 0x15 (Slot 3) */
 230                                 0a800 0 0 1 &mpic 1 1
 231                                 0a800 0 0 2 &mpic 2 1
 232                                 0a800 0 0 3 &mpic 3 1
 233                                 0a800 0 0 4 &mpic 0 1
 234
 235                                 /* IDSEL 0x16 (Slot 4) */
 236                                 0b000 0 0 1 &mpic 2 1
 237                                 0b000 0 0 2 &mpic 3 1
 238                                 0b000 0 0 3 &mpic 0 1
 239                                 0b000 0 0 4 &mpic 1 1
 240
 241                                 /* IDSEL 0x18 (Slot 5) */
 242                                 0c000 0 0 1 &mpic 0 1
 243                                 0c000 0 0 2 &mpic 1 1
 244                                 0c000 0 0 3 &mpic 2 1
 245                                 0c000 0 0 4 &mpic 3 1
 246
 247                                 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 248                                 0E000 0 0 1 &mpic 0 1
 249                                 0E000 0 0 2 &mpic 1 1
 250                                 0E000 0 0 3 &mpic 2 1
 251                                 0E000 0 0 4 &mpic 3 1>;
 252
 253                         interrupt-parent = <&mpic>;
 254                         interrupts = <18 2>;
 255                         bus-range = <0 0>;
 256                         ranges = <02000000 0 80000000 80000000 0 10000000
 257                                   01000000 0 00000000 e2000000 0 00800000>;
 258                         clock-frequency = <3f940aa>;
 259                         #interrupt-cells = <1>;
 260                         #size-cells = <2>;
 261                         #address-cells = <3>;
 262                         reg = <8000 1000>;
 263                         compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 264                         device_type = "pci";
 265
 266                         pci_bridge@1c {
 267                                 interrupt-map-mask = <f800 0 0 7>;
 268                                 interrupt-map = <
 269
 270                                         /* IDSEL 0x00 (PrPMC Site) */
 271                                         0000 0 0 1 &mpic 0 1
 272                                         0000 0 0 2 &mpic 1 1
 273                                         0000 0 0 3 &mpic 2 1
 274                                         0000 0 0 4 &mpic 3 1
 275
 276                                         /* IDSEL 0x04 (VIA chip) */
 277                                         2000 0 0 1 &mpic 0 1
 278                                         2000 0 0 2 &mpic 1 1
 279                                         2000 0 0 3 &mpic 2 1
 280                                         2000 0 0 4 &mpic 3 1
 281
 282                                         /* IDSEL 0x05 (8139) */
 283                                         2800 0 0 1 &mpic 1 1
 284
 285                                         /* IDSEL 0x06 (Slot 6) */
 286                                         3000 0 0 1 &mpic 2 1
 287                                         3000 0 0 2 &mpic 3 1
 288                                         3000 0 0 3 &mpic 0 1
 289                                         3000 0 0 4 &mpic 1 1
 290
 291                                         /* IDESL 0x07 (Slot 7) */
 292                                         3800 0 0 1 &mpic 3 1
 293                                         3800 0 0 2 &mpic 0 1
 294                                         3800 0 0 3 &mpic 1 1
 295                                         3800 0 0 4 &mpic 2 1>;
 296
 297                                 reg = <e000 0 0 0 0>;
 298                                 #interrupt-cells = <1>;
 299                                 #size-cells = <2>;
 300                                 #address-cells = <3>;
 301                                 ranges = <02000000 0 80000000
 302                                           02000000 0 80000000
 303                                           0 20000000
 304                                           01000000 0 00000000
 305                                           01000000 0 00000000
 306                                           0 00080000>;
 307                                 clock-frequency = <1fca055>;
 308
 309                                 isa@4 {
 310                                         device_type = "isa";
 311                                         #interrupt-cells = <2>;
 312                                         #size-cells = <1>;
 313                                         #address-cells = <2>;
 314                                         reg = <2000 0 0 0 0>;
 315                                         ranges = <1 0 01000000 0 0 00001000>;
 316                                         interrupt-parent = <&i8259>;
 317
 318                                         i8259: interrupt-controller@20 {
 319                                                 interrupt-controller;
 320                                                 device_type = "interrupt-controller";
 321                                                 reg = <1 20 2
 322                                                        1 a0 2
 323                                                        1 4d0 2>;
 324                                                 #address-cells = <0>;
 325                                                 #interrupt-cells = <2>;
 326                                                 compatible = "chrp,iic";
 327                                                 interrupts = <0 1>;
 328                                                 interrupt-parent = <&mpic>;
 329                                         };
 330
 331                                         rtc@70 {
 332                                                 compatible = "pnpPNP,b00";
 333                                                 reg = <1 70 2>;
 334                                         };
 335                                 };
 336                         };
 337                 };
 338
 339                 pci@9000 {
 340                         interrupt-map-mask = <f800 0 0 7>;
 341                         interrupt-map = <
 342
 343                                 /* IDSEL 0x15 */
 344                                 a800 0 0 1 &mpic b 1
 345                                 a800 0 0 2 &mpic 1 1
 346                                 a800 0 0 3 &mpic 2 1
 347                                 a800 0 0 4 &mpic 3 1>;
 348
 349                         interrupt-parent = <&mpic>;
 350                         interrupts = <19 2>;
 351                         bus-range = <0 0>;
 352                         ranges = <02000000 0 90000000 90000000 0 10000000
 353                                   01000000 0 00000000 e2800000 0 00800000>;
 354                         clock-frequency = <3f940aa>;
 355                         #interrupt-cells = <1>;
 356                         #size-cells = <2>;
 357                         #address-cells = <3>;
 358                         reg = <9000 1000>;
 359                         compatible = "fsl,mpc8540-pci";
 360                         device_type = "pci";
 361                 };
 362                 /* PCI Express */
 363                 pcie@a000 {
 364                         interrupt-map-mask = <f800 0 0 7>;
 365                         interrupt-map = <
 366
 367                                 /* IDSEL 0x0 (PEX) */
 368                                 00000 0 0 1 &mpic 0 1
 369                                 00000 0 0 2 &mpic 1 1
 370                                 00000 0 0 3 &mpic 2 1
 371                                 00000 0 0 4 &mpic 3 1>;
 372
 373                         interrupt-parent = <&mpic>;
 374                         interrupts = <1a 2>;
 375                         bus-range = <0 ff>;
 376                         ranges = <02000000 0 a0000000 a0000000 0 20000000
 377                                   01000000 0 00000000 e3000000 0 08000000>;
 378                         clock-frequency = <1fca055>;
 379                         #interrupt-cells = <1>;
 380                         #size-cells = <2>;
 381                         #address-cells = <3>;
 382                         reg = <a000 1000>;
 383                         compatible = "fsl,mpc8548-pcie";
 384                         device_type = "pci";
 385                 };
 386
 387                 mpic: pic@40000 {
 388                         clock-frequency = <0>;
 389                         interrupt-controller;
 390                         #address-cells = <0>;
 391                         #interrupt-cells = <2>;
 392                         reg = <40000 40000>;
 393                         compatible = "chrp,open-pic";
 394                         device_type = "open-pic";
 395                         big-endian;
 396                 };
 397         };
 398 };