2 * MPC8555 CDS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "MPC8555CDS", "MPC85xxCDS";
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
56 ranges = <0x0 0xe0000000 0x100000>;
57 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
60 memory-controller@2000 {
61 compatible = "fsl,8555-memory-controller";
62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>;
67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8555-l2-cache-controller";
69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; // 32 bytes
71 cache-size = <0x40000>; // L2, 256K
72 interrupt-parent = <&mpic>;
80 compatible = "fsl-i2c";
83 interrupt-parent = <&mpic>;
90 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
92 ranges = <0x0 0x21100 0x200>;
95 compatible = "fsl,mpc8555-dma-channel",
96 "fsl,eloplus-dma-channel";
99 interrupt-parent = <&mpic>;
103 compatible = "fsl,mpc8555-dma-channel",
104 "fsl,eloplus-dma-channel";
107 interrupt-parent = <&mpic>;
111 compatible = "fsl,mpc8555-dma-channel",
112 "fsl,eloplus-dma-channel";
115 interrupt-parent = <&mpic>;
119 compatible = "fsl,mpc8555-dma-channel",
120 "fsl,eloplus-dma-channel";
123 interrupt-parent = <&mpic>;
129 #address-cells = <1>;
131 compatible = "fsl,gianfar-mdio";
132 reg = <0x24520 0x20>;
134 phy0: ethernet-phy@0 {
135 interrupt-parent = <&mpic>;
138 device_type = "ethernet-phy";
140 phy1: ethernet-phy@1 {
141 interrupt-parent = <&mpic>;
144 device_type = "ethernet-phy";
148 enet0: ethernet@24000 {
150 device_type = "network";
152 compatible = "gianfar";
153 reg = <0x24000 0x1000>;
154 local-mac-address = [ 00 00 00 00 00 00 ];
155 interrupts = <29 2 30 2 34 2>;
156 interrupt-parent = <&mpic>;
157 phy-handle = <&phy0>;
160 enet1: ethernet@25000 {
162 device_type = "network";
164 compatible = "gianfar";
165 reg = <0x25000 0x1000>;
166 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <35 2 36 2 40 2>;
168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy1>;
172 serial0: serial@4500 {
174 device_type = "serial";
175 compatible = "ns16550";
176 reg = <0x4500 0x100>; // reg base, size
177 clock-frequency = <0>; // should we fill in in uboot?
179 interrupt-parent = <&mpic>;
182 serial1: serial@4600 {
184 device_type = "serial";
185 compatible = "ns16550";
186 reg = <0x4600 0x100>; // reg base, size
187 clock-frequency = <0>; // should we fill in in uboot?
189 interrupt-parent = <&mpic>;
193 interrupt-controller;
194 #address-cells = <0>;
195 #interrupt-cells = <2>;
196 reg = <0x40000 0x40000>;
197 compatible = "chrp,open-pic";
198 device_type = "open-pic";
202 #address-cells = <1>;
204 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
205 reg = <0x919c0 0x30>;
209 #address-cells = <1>;
211 ranges = <0x0 0x80000 0x10000>;
214 compatible = "fsl,cpm-muram-data";
215 reg = <0x0 0x2000 0x9000 0x1000>;
220 compatible = "fsl,mpc8555-brg",
223 reg = <0x919f0 0x10 0x915f0 0x10>;
227 interrupt-controller;
228 #address-cells = <0>;
229 #interrupt-cells = <2>;
231 interrupt-parent = <&mpic>;
232 reg = <0x90c00 0x80>;
233 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
240 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
244 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
245 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
246 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
247 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
250 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
251 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
252 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
253 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
255 /* IDSEL 0x12 (Slot 1) */
256 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
261 /* IDSEL 0x13 (Slot 2) */
262 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
267 /* IDSEL 0x14 (Slot 3) */
268 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
273 /* IDSEL 0x15 (Slot 4) */
274 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
275 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
276 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
277 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
279 /* Bus 1 (Tundra Bridge) */
280 /* IDSEL 0x12 (ISA bridge) */
281 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
282 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
283 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
284 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
285 interrupt-parent = <&mpic>;
288 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
289 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
290 clock-frequency = <66666666>;
291 #interrupt-cells = <1>;
293 #address-cells = <3>;
294 reg = <0xe0008000 0x1000>;
295 compatible = "fsl,mpc8540-pci";
299 interrupt-controller;
300 device_type = "interrupt-controller";
301 reg = <0x19000 0x0 0x0 0x0 0x1>;
302 #address-cells = <0>;
303 #interrupt-cells = <2>;
304 compatible = "chrp,iic";
306 interrupt-parent = <&pci0>;
312 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
316 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
317 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
318 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
319 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
320 interrupt-parent = <&mpic>;
323 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
324 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
325 clock-frequency = <66666666>;
326 #interrupt-cells = <1>;
328 #address-cells = <3>;
329 reg = <0xe0009000 0x1000>;
330 compatible = "fsl,mpc8540-pci";