arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 /*
  14 /memreserve/    00000000 1000000;
  15 */
  16
  17 / {
  18         model = "MPC8568EMDS";
  19         compatible = "MPC8568EMDS", "MPC85xxMDS";
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 PowerPC,8568@0 {
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         d-cache-line-size = <20>;       // 32 bytes
  31                         i-cache-line-size = <20>;       // 32 bytes
  32                         d-cache-size = <8000>;          // L1, 32K
  33                         i-cache-size = <8000>;          // L1, 32K
  34                         timebase-frequency = <0>;
  35                         bus-frequency = <0>;
  36                         clock-frequency = <0>;
  37                         32-bit;
  38                 };
  39         };
  40
  41         memory {
  42                 device_type = "memory";
  43                 reg = <00000000 10000000>;
  44         };
  45
  46         bcsr@f8000000 {
  47                 device_type = "board-control";
  48                 reg = <f8000000 8000>;
  49         };
  50
  51         soc8568@e0000000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 #interrupt-cells = <2>;
  55                 device_type = "soc";
  56                 ranges = <0 e0000000 00100000>;
  57                 reg = <e0000000 00100000>;
  58                 bus-frequency = <0>;
  59
  60                 memory-controller@2000 {
  61                         compatible = "fsl,8568-memory-controller";
  62                         reg = <2000 1000>;
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <2 2>;
  65                 };
  66
  67                 l2-cache-controller@20000 {
  68                         compatible = "fsl,8568-l2-cache-controller";
  69                         reg = <20000 1000>;
  70                         cache-line-size = <20>; // 32 bytes
  71                         cache-size = <80000>;   // L2, 512K
  72                         interrupt-parent = <&mpic>;
  73                         interrupts = <0 2>;
  74                 };
  75
  76                 i2c@3000 {
  77                         device_type = "i2c";
  78                         compatible = "fsl-i2c";
  79                         reg = <3000 100>;
  80                         interrupts = <1b 2>;
  81                         interrupt-parent = <&mpic>;
  82                         dfsrr;
  83                 };
  84
  85                 i2c@3100 {
  86                         device_type = "i2c";
  87                         compatible = "fsl-i2c";
  88                         reg = <3100 100>;
  89                         interrupts = <1b 2>;
  90                         interrupt-parent = <&mpic>;
  91                         dfsrr;
  92                 };
  93
  94                 mdio@24520 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         device_type = "mdio";
  98                         compatible = "gianfar";
  99                         reg = <24520 20>;
 100                         phy0: ethernet-phy@0 {
 101                                 interrupt-parent = <&mpic>;
 102                                 interrupts = <31 1>;
 103                                 reg = <0>;
 104                                 device_type = "ethernet-phy";
 105                         };
 106                         phy1: ethernet-phy@1 {
 107                                 interrupt-parent = <&mpic>;
 108                                 interrupts = <32 1>;
 109                                 reg = <1>;
 110                                 device_type = "ethernet-phy";
 111                         };
 112                         phy2: ethernet-phy@2 {
 113                                 interrupt-parent = <&mpic>;
 114                                 interrupts = <31 1>;
 115                                 reg = <2>;
 116                                 device_type = "ethernet-phy";
 117                         };
 118                         phy3: ethernet-phy@3 {
 119                                 interrupt-parent = <&mpic>;
 120                                 interrupts = <32 1>;
 121                                 reg = <3>;
 122                                 device_type = "ethernet-phy";
 123                         };
 124                 };
 125
 126                 ethernet@24000 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         device_type = "network";
 130                         model = "eTSEC";
 131                         compatible = "gianfar";
 132                         reg = <24000 1000>;
 133                         mac-address = [ 00 00 00 00 00 00 ];
 134                         interrupts = <d 2 e 2 12 2>;
 135                         interrupt-parent = <&mpic>;
 136                         phy-handle = <&phy2>;
 137                 };
 138
 139                 ethernet@25000 {
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         device_type = "network";
 143                         model = "eTSEC";
 144                         compatible = "gianfar";
 145                         reg = <25000 1000>;
 146                         mac-address = [ 00 00 00 00 00 00];
 147                         interrupts = <13 2 14 2 18 2>;
 148                         interrupt-parent = <&mpic>;
 149                         phy-handle = <&phy3>;
 150                 };
 151
 152                 serial@4500 {
 153                         device_type = "serial";
 154                         compatible = "ns16550";
 155                         reg = <4500 100>;
 156                         clock-frequency = <0>;
 157                         interrupts = <1a 2>;
 158                         interrupt-parent = <&mpic>;
 159                 };
 160
 161                 serial@4600 {
 162                         device_type = "serial";
 163                         compatible = "ns16550";
 164                         reg = <4600 100>;
 165                         clock-frequency = <0>;
 166                         interrupts = <1a 2>;
 167                         interrupt-parent = <&mpic>;
 168                 };
 169
 170                 crypto@30000 {
 171                         device_type = "crypto";
 172                         model = "SEC2";
 173                         compatible = "talitos";
 174                         reg = <30000 f000>;
 175                         interrupts = <1d 2>;
 176                         interrupt-parent = <&mpic>;
 177                         num-channels = <4>;
 178                         channel-fifo-len = <18>;
 179                         exec-units-mask = <000000fe>;
 180                         descriptor-types-mask = <012b0ebf>;
 181                 };
 182
 183                 mpic: pic@40000 {
 184                         clock-frequency = <0>;
 185                         interrupt-controller;
 186                         #address-cells = <0>;
 187                         #interrupt-cells = <2>;
 188                         reg = <40000 40000>;
 189                         built-in;
 190                         compatible = "chrp,open-pic";
 191                         device_type = "open-pic";
 192                         big-endian;
 193                 };
 194                 par_io@e0100 {
 195                         reg = <e0100 100>;
 196                         device_type = "par_io";
 197                         num-ports = <7>;
 198
 199                         pio1: ucc_pin@01 {
 200                                 pio-map = <
 201                         /* port  pin  dir  open_drain  assignment  has_irq */
 202                                         4  0a  1  0  2  0       /* TxD0 */
 203                                         4  09  1  0  2  0       /* TxD1 */
 204                                         4  08  1  0  2  0       /* TxD2 */
 205                                         4  07  1  0  2  0       /* TxD3 */
 206                                         4  17  1  0  2  0       /* TxD4 */
 207                                         4  16  1  0  2  0       /* TxD5 */
 208                                         4  15  1  0  2  0       /* TxD6 */
 209                                         4  14  1  0  2  0       /* TxD7 */
 210                                         4  0f  2  0  2  0       /* RxD0 */
 211                                         4  0e  2  0  2  0       /* RxD1 */
 212                                         4  0d  2  0  2  0       /* RxD2 */
 213                                         4  0c  2  0  2  0       /* RxD3 */
 214                                         4  1d  2  0  2  0       /* RxD4 */
 215                                         4  1c  2  0  2  0       /* RxD5 */
 216                                         4  1b  2  0  2  0       /* RxD6 */
 217                                         4  1a  2  0  2  0       /* RxD7 */
 218                                         4  0b  1  0  2  0       /* TX_EN */
 219                                         4  18  1  0  2  0       /* TX_ER */
 220                                         4  0f  2  0  2  0       /* RX_DV */
 221                                         4  1e  2  0  2  0       /* RX_ER */
 222                                         4  11  2  0  2  0       /* RX_CLK */
 223                                         4  13  1  0  2  0       /* GTX_CLK */
 224                                         1  1f  2  0  3  0>;     /* GTX125 */
 225                         };
 226                         pio2: ucc_pin@02 {
 227                                 pio-map = <
 228                         /* port  pin  dir  open_drain  assignment  has_irq */
 229                                         5  0a 1  0  2  0   /* TxD0 */
 230                                         5  09 1  0  2  0   /* TxD1 */
 231                                         5  08 1  0  2  0   /* TxD2 */
 232                                         5  07 1  0  2  0   /* TxD3 */
 233                                         5  17 1  0  2  0   /* TxD4 */
 234                                         5  16 1  0  2  0   /* TxD5 */
 235                                         5  15 1  0  2  0   /* TxD6 */
 236                                         5  14 1  0  2  0   /* TxD7 */
 237                                         5  0f 2  0  2  0   /* RxD0 */
 238                                         5  0e 2  0  2  0   /* RxD1 */
 239                                         5  0d 2  0  2  0   /* RxD2 */
 240                                         5  0c 2  0  2  0   /* RxD3 */
 241                                         5  1d 2  0  2  0   /* RxD4 */
 242                                         5  1c 2  0  2  0   /* RxD5 */
 243                                         5  1b 2  0  2  0   /* RxD6 */
 244                                         5  1a 2  0  2  0   /* RxD7 */
 245                                         5  0b 1  0  2  0   /* TX_EN */
 246                                         5  18 1  0  2  0   /* TX_ER */
 247                                         5  10 2  0  2  0   /* RX_DV */
 248                                         5  1e 2  0  2  0   /* RX_ER */
 249                                         5  11 2  0  2  0   /* RX_CLK */
 250                                         5  13 1  0  2  0   /* GTX_CLK */
 251                                         1  1f 2  0  3  0   /* GTX125 */
 252                                         4  06 3  0  2  0   /* MDIO */
 253                                         4  05 1  0  2  0>; /* MDC */
 254                         };
 255                 };
 256         };
 257
 258         qe@e0080000 {
 259                 #address-cells = <1>;
 260                 #size-cells = <1>;
 261                 device_type = "qe";
 262                 model = "QE";
 263                 ranges = <0 e0080000 00040000>;
 264                 reg = <e0080000 480>;
 265                 brg-frequency = <0>;
 266                 bus-frequency = <179A7B00>;
 267
 268                 muram@10000 {
 269                         device_type = "muram";
 270                         ranges = <0 00010000 0000c000>;
 271
 272                         data-only@0{
 273                                 reg = <0 c000>;
 274                         };
 275                 };
 276
 277                 spi@4c0 {
 278                         device_type = "spi";
 279                         compatible = "fsl_spi";
 280                         reg = <4c0 40>;
 281                         interrupts = <2>;
 282                         interrupt-parent = <&qeic>;
 283                         mode = "cpu";
 284                 };
 285
 286                 spi@500 {
 287                         device_type = "spi";
 288                         compatible = "fsl_spi";
 289                         reg = <500 40>;
 290                         interrupts = <1>;
 291                         interrupt-parent = <&qeic>;
 292                         mode = "cpu";
 293                 };
 294
 295                 ucc@2000 {
 296                         device_type = "network";
 297                         compatible = "ucc_geth";
 298                         model = "UCC";
 299                         device-id = <1>;
 300                         reg = <2000 200>;
 301                         interrupts = <20>;
 302                         interrupt-parent = <&qeic>;
 303                         mac-address = [ 00 04 9f 00 23 23 ];
 304                         rx-clock = <0>;
 305                         tx-clock = <19>;
 306                         phy-handle = <&qe_phy0>;
 307                         phy-connection-type = "gmii";
 308                         pio-handle = <&pio1>;
 309                 };
 310
 311                 ucc@3000 {
 312                         device_type = "network";
 313                         compatible = "ucc_geth";
 314                         model = "UCC";
 315                         device-id = <2>;
 316                         reg = <3000 200>;
 317                         interrupts = <21>;
 318                         interrupt-parent = <&qeic>;
 319                         mac-address = [ 00 11 22 33 44 55 ];
 320                         rx-clock = <0>;
 321                         tx-clock = <14>;
 322                         phy-handle = <&qe_phy1>;
 323                         phy-connection-type = "gmii";
 324                         pio-handle = <&pio2>;
 325                 };
 326
 327                 mdio@2120 {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         reg = <2120 18>;
 331                         device_type = "mdio";
 332                         compatible = "ucc_geth_phy";
 333
 334                         /* These are the same PHYs as on
 335                          * gianfar's MDIO bus */
 336                         qe_phy0: ethernet-phy@00 {
 337                                 interrupt-parent = <&mpic>;
 338                                 interrupts = <31 1>;
 339                                 reg = <0>;
 340                                 device_type = "ethernet-phy";
 341                         };
 342                         qe_phy1: ethernet-phy@01 {
 343                                 interrupt-parent = <&mpic>;
 344                                 interrupts = <32 1>;
 345                                 reg = <1>;
 346                                 device_type = "ethernet-phy";
 347                         };
 348                         qe_phy2: ethernet-phy@02 {
 349                                 interrupt-parent = <&mpic>;
 350                                 interrupts = <31 1>;
 351                                 reg = <2>;
 352                                 device_type = "ethernet-phy";
 353                         };
 354                         qe_phy3: ethernet-phy@03 {
 355                                 interrupt-parent = <&mpic>;
 356                                 interrupts = <32 1>;
 357                                 reg = <3>;
 358                                 device_type = "ethernet-phy";
 359                         };
 360                 };
 361
 362                 qeic: qeic@80 {
 363                         interrupt-controller;
 364                         device_type = "qeic";
 365                         #address-cells = <0>;
 366                         #interrupt-cells = <1>;
 367                         reg = <80 80>;
 368                         built-in;
 369                         big-endian;
 370                         interrupts = <1e 2 1e 2>; //high:30 low:30
 371                         interrupt-parent = <&mpic>;
 372                 };
 373
 374         };
 375 };