2 * MPC8568E MDS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
50 device_type = "memory";
51 reg = <0x0 0x10000000>;
55 device_type = "board-control";
56 reg = <0xf8000000 0x8000>;
63 ranges = <0x0 0xe0000000 0x100000>;
64 reg = <0xe0000000 0x1000>;
67 memory-controller@2000 {
68 compatible = "fsl,8568-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
74 L2: l2-cache-controller@20000 {
75 compatible = "fsl,8568-l2-cache-controller";
76 reg = <0x20000 0x1000>;
77 cache-line-size = <32>; // 32 bytes
78 cache-size = <0x80000>; // L2, 512K
79 interrupt-parent = <&mpic>;
87 compatible = "fsl-i2c";
90 interrupt-parent = <&mpic>;
94 compatible = "dallas,ds1374";
100 #address-cells = <1>;
103 compatible = "fsl-i2c";
104 reg = <0x3100 0x100>;
106 interrupt-parent = <&mpic>;
111 #address-cells = <1>;
113 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
115 ranges = <0x0 0x21100 0x200>;
118 compatible = "fsl,mpc8568-dma-channel",
119 "fsl,eloplus-dma-channel";
122 interrupt-parent = <&mpic>;
126 compatible = "fsl,mpc8568-dma-channel",
127 "fsl,eloplus-dma-channel";
130 interrupt-parent = <&mpic>;
134 compatible = "fsl,mpc8568-dma-channel",
135 "fsl,eloplus-dma-channel";
138 interrupt-parent = <&mpic>;
142 compatible = "fsl,mpc8568-dma-channel",
143 "fsl,eloplus-dma-channel";
146 interrupt-parent = <&mpic>;
152 #address-cells = <1>;
154 compatible = "fsl,gianfar-mdio";
155 reg = <0x24520 0x20>;
157 phy0: ethernet-phy@7 {
158 interrupt-parent = <&mpic>;
161 device_type = "ethernet-phy";
163 phy1: ethernet-phy@1 {
164 interrupt-parent = <&mpic>;
167 device_type = "ethernet-phy";
169 phy2: ethernet-phy@2 {
170 interrupt-parent = <&mpic>;
173 device_type = "ethernet-phy";
175 phy3: ethernet-phy@3 {
176 interrupt-parent = <&mpic>;
179 device_type = "ethernet-phy";
183 enet0: ethernet@24000 {
185 device_type = "network";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 local-mac-address = [ 00 00 00 00 00 00 ];
190 interrupts = <29 2 30 2 34 2>;
191 interrupt-parent = <&mpic>;
192 phy-handle = <&phy2>;
195 enet1: ethernet@25000 {
197 device_type = "network";
199 compatible = "gianfar";
200 reg = <0x25000 0x1000>;
201 local-mac-address = [ 00 00 00 00 00 00 ];
202 interrupts = <35 2 36 2 40 2>;
203 interrupt-parent = <&mpic>;
204 phy-handle = <&phy3>;
207 serial0: serial@4500 {
209 device_type = "serial";
210 compatible = "ns16550";
211 reg = <0x4500 0x100>;
212 clock-frequency = <0>;
214 interrupt-parent = <&mpic>;
217 global-utilities@e0000 { //global utilities block
218 compatible = "fsl,mpc8548-guts";
219 reg = <0xe0000 0x1000>;
223 serial1: serial@4600 {
225 device_type = "serial";
226 compatible = "ns16550";
227 reg = <0x4600 0x100>;
228 clock-frequency = <0>;
230 interrupt-parent = <&mpic>;
234 device_type = "crypto";
236 compatible = "talitos";
237 reg = <0x30000 0xf000>;
239 interrupt-parent = <&mpic>;
241 channel-fifo-len = <24>;
242 exec-units-mask = <0xfe>;
243 descriptor-types-mask = <0x12b0ebf>;
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <2>;
250 reg = <0x40000 0x40000>;
251 compatible = "chrp,open-pic";
252 device_type = "open-pic";
256 reg = <0xe0100 0x100>;
257 device_type = "par_io";
262 /* port pin dir open_drain assignment has_irq */
263 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
264 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
265 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
266 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
267 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
268 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
269 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
270 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
271 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
272 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
273 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
274 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
275 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
276 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
277 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
278 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
279 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
280 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
281 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
282 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
283 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
284 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
285 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
290 /* port pin dir open_drain assignment has_irq */
291 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
292 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
293 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
294 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
295 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
296 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
297 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
298 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
299 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
300 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
301 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
302 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
303 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
304 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
305 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
306 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
307 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
308 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
309 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
310 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
311 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
312 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
313 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
314 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
315 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
321 #address-cells = <1>;
324 compatible = "fsl,qe";
325 ranges = <0x0 0xe0080000 0x40000>;
326 reg = <0xe0080000 0x480>;
328 bus-frequency = <396000000>;
331 #address-cells = <1>;
333 compatible = "fsl,qe-muram", "fsl,cpm-muram";
334 ranges = <0x0 0x10000 0x10000>;
337 compatible = "fsl,qe-muram-data",
338 "fsl,cpm-muram-data";
345 compatible = "fsl,spi";
348 interrupt-parent = <&qeic>;
354 compatible = "fsl,spi";
357 interrupt-parent = <&qeic>;
362 device_type = "network";
363 compatible = "ucc_geth";
365 reg = <0x2000 0x200>;
367 interrupt-parent = <&qeic>;
368 local-mac-address = [ 00 00 00 00 00 00 ];
369 rx-clock-name = "none";
370 tx-clock-name = "clk16";
371 pio-handle = <&pio1>;
372 phy-handle = <&phy0>;
373 phy-connection-type = "rgmii-id";
377 device_type = "network";
378 compatible = "ucc_geth";
380 reg = <0x3000 0x200>;
382 interrupt-parent = <&qeic>;
383 local-mac-address = [ 00 00 00 00 00 00 ];
384 rx-clock-name = "none";
385 tx-clock-name = "clk16";
386 pio-handle = <&pio2>;
387 phy-handle = <&phy1>;
388 phy-connection-type = "rgmii-id";
392 #address-cells = <1>;
395 compatible = "fsl,ucc-mdio";
397 /* These are the same PHYs as on
398 * gianfar's MDIO bus */
399 qe_phy0: ethernet-phy@07 {
400 interrupt-parent = <&mpic>;
403 device_type = "ethernet-phy";
405 qe_phy1: ethernet-phy@01 {
406 interrupt-parent = <&mpic>;
409 device_type = "ethernet-phy";
411 qe_phy2: ethernet-phy@02 {
412 interrupt-parent = <&mpic>;
415 device_type = "ethernet-phy";
417 qe_phy3: ethernet-phy@03 {
418 interrupt-parent = <&mpic>;
421 device_type = "ethernet-phy";
425 qeic: interrupt-controller@80 {
426 interrupt-controller;
427 compatible = "fsl,qe-ic";
428 #address-cells = <0>;
429 #interrupt-cells = <1>;
432 interrupts = <46 2 46 2>; //high:30 low:30
433 interrupt-parent = <&mpic>;
440 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
442 /* IDSEL 0x12 AD18 */
443 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
444 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
445 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
446 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
448 /* IDSEL 0x13 AD19 */
449 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
450 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
451 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
452 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
454 interrupt-parent = <&mpic>;
457 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
458 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
459 clock-frequency = <66666666>;
460 #interrupt-cells = <1>;
462 #address-cells = <3>;
463 reg = <0xe0008000 0x1000>;
464 compatible = "fsl,mpc8540-pci";
469 pci1: pcie@e000a000 {
471 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
474 /* IDSEL 0x0 (PEX) */
475 00000 0x0 0x0 0x1 &mpic 0x0 0x1
476 00000 0x0 0x0 0x2 &mpic 0x1 0x1
477 00000 0x0 0x0 0x3 &mpic 0x2 0x1
478 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
480 interrupt-parent = <&mpic>;
483 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
484 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
485 clock-frequency = <33333333>;
486 #interrupt-cells = <1>;
488 #address-cells = <3>;
489 reg = <0xe000a000 0x1000>;
490 compatible = "fsl,mpc8548-pcie";
493 reg = <0x0 0x0 0x0 0x0 0x0>;
495 #address-cells = <3>;
497 ranges = <0x2000000 0x0 0xa0000000
498 0x2000000 0x0 0xa0000000