2 * MPC8572 DS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>;
31 clock-frequency = <0>;
36 device_type = "memory";
37 reg = <00000000 00000000>; // Filled by U-Boot
44 ranges = <00000000 ffe00000 00100000>;
45 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
46 bus-frequency = <0>; // Filled out by uboot.
48 memory-controller@2000 {
49 compatible = "fsl,mpc8572-memory-controller";
51 interrupt-parent = <&mpic>;
55 memory-controller@6000 {
56 compatible = "fsl,mpc8572-memory-controller";
58 interrupt-parent = <&mpic>;
62 l2-cache-controller@20000 {
63 compatible = "fsl,mpc8572-l2-cache-controller";
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
73 compatible = "fsl-i2c";
76 interrupt-parent = <&mpic>;
82 compatible = "fsl-i2c";
85 interrupt-parent = <&mpic>;
93 compatible = "gianfar";
95 phy0: ethernet-phy@0 {
96 interrupt-parent = <&mpic>;
100 phy1: ethernet-phy@1 {
101 interrupt-parent = <&mpic>;
105 phy2: ethernet-phy@2 {
106 interrupt-parent = <&mpic>;
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
118 #address-cells = <1>;
120 device_type = "network";
122 compatible = "gianfar";
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <1d 2 1e 2 22 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy0>;
128 phy-connection-type = "rgmii-id";
132 #address-cells = <1>;
134 device_type = "network";
136 compatible = "gianfar";
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <23 2 24 2 28 2>;
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id";
146 #address-cells = <1>;
148 device_type = "network";
150 compatible = "gianfar";
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <1f 2 20 2 21 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy2>;
156 phy-connection-type = "rgmii-id";
160 #address-cells = <1>;
162 device_type = "network";
164 compatible = "gianfar";
166 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <25 2 26 2 27 2>;
168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy3>;
170 phy-connection-type = "rgmii-id";
174 device_type = "serial";
175 compatible = "ns16550";
177 clock-frequency = <0>;
179 interrupt-parent = <&mpic>;
183 device_type = "serial";
184 compatible = "ns16550";
186 clock-frequency = <0>;
188 interrupt-parent = <&mpic>;
191 global-utilities@e0000 { //global utilities block
192 compatible = "fsl,mpc8572-guts";
198 clock-frequency = <0>;
199 interrupt-controller;
200 #address-cells = <0>;
201 #interrupt-cells = <2>;
203 compatible = "chrp,open-pic";
204 device_type = "open-pic";
210 compatible = "fsl,mpc8548-pcie";
212 #interrupt-cells = <1>;
214 #address-cells = <3>;
215 reg = <ffe08000 1000>;
217 ranges = <02000000 0 80000000 80000000 0 20000000
218 01000000 0 00000000 ffc00000 0 00010000>;
219 clock-frequency = <1fca055>;
220 interrupt-parent = <&mpic>;
222 interrupt-map-mask = <fb00 0 0 0>;
224 /* IDSEL 0x11 - PCI slot 1 */
230 /* IDSEL 0x12 - PCI slot 2 */
237 e000 0 0 0 &i8259 c 2
238 e100 0 0 0 &i8259 9 2
239 e200 0 0 0 &i8259 a 2
240 e300 0 0 0 &i8259 b 2
243 e800 0 0 0 &i8259 6 2
246 f000 0 0 0 &i8259 7 2
247 f100 0 0 0 &i8259 7 2
249 // IDSEL 0x1f IDE/SATA
250 f800 0 0 0 &i8259 e 2
251 f900 0 0 0 &i8259 5 2
258 #address-cells = <3>;
260 ranges = <02000000 0 80000000
270 #address-cells = <3>;
271 ranges = <02000000 0 80000000
280 #interrupt-cells = <2>;
282 #address-cells = <2>;
283 reg = <f000 0 0 0 0>;
284 ranges = <1 0 01000000 0 0
286 interrupt-parent = <&i8259>;
288 i8259: interrupt-controller@20 {
292 interrupt-controller;
293 device_type = "interrupt-controller";
294 #address-cells = <0>;
295 #interrupt-cells = <2>;
296 compatible = "chrp,iic";
298 interrupt-parent = <&mpic>;
303 #address-cells = <1>;
304 reg = <1 60 1 1 64 1>;
305 interrupts = <1 3 c 3>;
311 compatible = "pnpPNP,303";
316 compatible = "pnpPNP,f03";
321 compatible = "pnpPNP,b00";
335 compatible = "fsl,mpc8548-pcie";
337 #interrupt-cells = <1>;
339 #address-cells = <3>;
340 reg = <ffe09000 1000>;
342 ranges = <02000000 0 a0000000 a0000000 0 20000000
343 01000000 0 00000000 ffc10000 0 00010000>;
344 clock-frequency = <1fca055>;
345 interrupt-parent = <&mpic>;
347 interrupt-map-mask = <f800 0 0 7>;
358 #address-cells = <3>;
360 ranges = <02000000 0 a0000000
371 compatible = "fsl,mpc8548-pcie";
373 #interrupt-cells = <1>;
375 #address-cells = <3>;
376 reg = <ffe0a000 1000>;
378 ranges = <02000000 0 c0000000 c0000000 0 20000000
379 01000000 0 00000000 ffc20000 0 00010000>;
380 clock-frequency = <1fca055>;
381 interrupt-parent = <&mpic>;
393 #address-cells = <3>;
395 ranges = <02000000 0 c0000000