3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
38 .tc .sys_call_table[TC],.sys_call_table
40 /* This value is used to mark exception frames on the stack. */
42 .tc ID_72656773_68657265[TC],0x7265677368657265
49 .globl system_call_common
53 addi r1,r1,-INT_FRAME_SIZE
62 ACCOUNT_CPU_USER_ENTRY(r10, r11)
88 addi r9,r1,STACK_FRAME_OVERHEAD
89 ld r11,exception_marker@toc(r2)
90 std r11,-16(r9) /* "regshere" marker */
92 stb r10,PACASOFTIRQEN(r13)
93 stb r10,PACAHARDIRQEN(r13)
95 #ifdef CONFIG_PPC_ISERIES
97 /* Hack for handling interrupts when soft-enabling on iSeries */
98 cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
99 andi. r10,r12,MSR_PR /* from kernel */
100 crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
102 b hardware_interrupt_entry
104 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
115 addi r9,r1,STACK_FRAME_OVERHEAD
117 clrrdi r11,r1,THREAD_SHIFT
119 andi. r11,r10,_TIF_SYSCALL_T_OR_A
121 syscall_dotrace_cont:
122 cmpldi 0,r0,NR_syscalls
125 system_call: /* label this so stack traces look sane */
127 * Need to vector to 32 Bit or default sys_call_table here,
128 * based on caller's run-mode / personality.
130 ld r11,.SYS_CALL_TABLE@toc(2)
131 andi. r10,r10,_TIF_32BIT
133 addi r11,r11,8 /* use 32-bit syscall entries */
142 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
144 bctrl /* Call handler */
149 bl .do_show_syscall_exit
152 clrrdi r12,r1,THREAD_SHIFT
154 /* disable interrupts so current_thread_info()->flags can't change,
155 and so that we don't get interrupted after loading SRR0/1. */
165 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
166 bne- syscall_exit_work
172 stdcx. r0,0,r1 /* to clear the reservation */
176 * Clear RI before restoring r13. If we are returning to
177 * userspace and we take an exception after restoring r13,
178 * we end up corrupting the userspace r13 value.
182 mtmsrd r11,1 /* clear MSR.RI */
184 ACCOUNT_CPU_USER_EXIT(r11, r12)
185 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
193 b . /* prevent speculative execution */
196 oris r5,r5,0x1000 /* Set SO bit in CR */
201 /* Traced system call support */
204 addi r3,r1,STACK_FRAME_OVERHEAD
205 bl .do_syscall_trace_enter
206 ld r0,GPR0(r1) /* Restore original registers */
213 addi r9,r1,STACK_FRAME_OVERHEAD
214 clrrdi r10,r1,THREAD_SHIFT
216 b syscall_dotrace_cont
223 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
224 If TIF_NOERROR is set, just save r3 as it is. */
226 andi. r0,r9,_TIF_RESTOREALL
230 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
232 andi. r0,r9,_TIF_NOERROR
236 oris r5,r5,0x1000 /* Set SO bit in CR */
239 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
242 /* Clear per-syscall TIF flags if any are set. */
244 li r11,_TIF_PERSYSCALL_MASK
245 addi r12,r12,TI_FLAGS
250 subi r12,r12,TI_FLAGS
252 4: /* Anything else left to do? */
253 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
254 beq .ret_from_except_lite
256 /* Re-enable interrupts */
262 addi r3,r1,STACK_FRAME_OVERHEAD
263 bl .do_syscall_trace_leave
266 /* Save non-volatile GPRs, if not already saved. */
278 * The sigsuspend and rt_sigsuspend system calls can call do_signal
279 * and thus put the process into the stopped state where we might
280 * want to examine its user state with ptrace. Therefore we need
281 * to save all the nonvolatile registers (r14 - r31) before calling
282 * the C code. Similarly, fork, vfork and clone need the full
283 * register state on the stack so that it can be copied to the child.
301 _GLOBAL(ppc32_swapcontext)
303 bl .compat_sys_swapcontext
306 _GLOBAL(ppc64_swapcontext)
311 _GLOBAL(ret_from_fork)
318 * This routine switches between two different tasks. The process
319 * state of one is saved on its kernel stack. Then the state
320 * of the other is restored from its kernel stack. The memory
321 * management hardware is updated to the second process's state.
322 * Finally, we can return to the second process, via ret_from_except.
323 * On entry, r3 points to the THREAD for the current task, r4
324 * points to the THREAD for the new task.
326 * Note: there are two ways to get to the "going out" portion
327 * of this code; either by coming in via the entry (_switch)
328 * or via "fork" which must set up an environment equivalent
329 * to the "_switch" path. If you change this you'll have to change
330 * the fork code also.
332 * The code which creates the new task context is in 'copy_thread'
333 * in arch/powerpc/kernel/process.c
339 stdu r1,-SWITCH_FRAME_SIZE(r1)
340 /* r3-r13 are caller saved -- Cort */
343 mflr r20 /* Return to switch caller */
346 #ifdef CONFIG_ALTIVEC
348 oris r0,r0,MSR_VEC@h /* Disable altivec */
349 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
350 std r24,THREAD_VRSAVE(r3)
351 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
352 #endif /* CONFIG_ALTIVEC */
361 std r1,KSP(r3) /* Set old stack pointer */
364 /* We need a sync somewhere here to make sure that if the
365 * previous task gets rescheduled on another CPU, it sees all
366 * stores it has performed on this one.
369 #endif /* CONFIG_SMP */
371 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
372 std r6,PACACURRENT(r13) /* Set new 'current' */
374 ld r8,KSP(r4) /* new stack pointer */
377 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
379 clrrdi r6,r8,28 /* get its ESID */
380 clrrdi r9,r1,28 /* get current sp ESID */
381 END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
383 clrrdi r6,r8,40 /* get its 1T ESID */
384 clrrdi r9,r1,40 /* get current sp 1T ESID */
385 END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
386 clrldi. r0,r6,2 /* is new ESID c00000000? */
387 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
389 beq 2f /* if yes, don't slbie it */
391 /* Bolt in the new stack SLB entry */
392 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
393 oris r0,r6,(SLB_ESID_V)@h
394 ori r0,r0,(SLB_NUM_BOLTED-1)@l
396 li r9,MMU_SEGSIZE_1T /* insert B field */
397 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
398 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
399 END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
401 /* Update the last bolted SLB. No write barriers are needed
402 * here, provided we only update the current CPU's SLB shadow
405 ld r9,PACA_SLBSHADOWPTR(r13)
407 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
408 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
409 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
412 slbie r6 /* Workaround POWER5 < DD2.1 issue */
417 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
418 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
419 because we don't need to leave the 288-byte ABI gap at the
420 top of the kernel stack. */
421 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
423 mr r1,r8 /* start using new stack pointer */
424 std r7,PACAKSAVE(r13)
429 #ifdef CONFIG_ALTIVEC
431 ld r0,THREAD_VRSAVE(r4)
432 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
433 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
434 #endif /* CONFIG_ALTIVEC */
436 /* r3-r13 are destroyed -- Cort */
440 /* convert old thread to its task_struct for return value */
442 ld r7,_NIP(r1) /* Return to _switch caller in new task */
444 addi r1,r1,SWITCH_FRAME_SIZE
448 _GLOBAL(ret_from_except)
451 bne .ret_from_except_lite
454 _GLOBAL(ret_from_except_lite)
456 * Disable interrupts so that current_thread_info()->flags
457 * can't change between when we test it and when we return
458 * from the interrupt.
460 mfmsr r10 /* Get current interrupt state */
461 rldicl r9,r10,48,1 /* clear MSR_EE */
463 mtmsrd r9,1 /* Update machine state */
465 #ifdef CONFIG_PREEMPT
466 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
467 li r0,_TIF_NEED_RESCHED /* bits to check */
470 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
471 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
472 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
475 #else /* !CONFIG_PREEMPT */
476 ld r3,_MSR(r1) /* Returning to user mode? */
478 beq restore /* if not, just restore regs and return */
480 /* Check current_thread_info()->flags */
481 clrrdi r9,r1,THREAD_SHIFT
483 andi. r0,r4,_TIF_USER_WORK_MASK
489 #ifdef CONFIG_PPC_ISERIES
493 /* Check for pending interrupts (iSeries) */
494 ld r3,PACALPPACAPTR(r13)
495 ld r3,LPPACAANYINT(r3)
497 beq+ 4f /* skip do_IRQ if no interrupts */
500 stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
502 mtmsrd r10 /* hard-enable again */
503 addi r3,r1,STACK_FRAME_OVERHEAD
505 b .ret_from_except_lite /* loop back and handle more */
507 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
509 stb r5,PACASOFTIRQEN(r13)
511 /* extract EE bit and use it to restore paca->hard_enabled */
513 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
514 stb r4,PACAHARDIRQEN(r13)
528 stdcx. r0,0,r1 /* to clear the reservation */
531 * Clear RI before restoring r13. If we are returning to
532 * userspace and we take an exception after restoring r13,
533 * we end up corrupting the userspace r13 value.
536 andc r4,r4,r0 /* r0 contains MSR_RI here */
540 * r13 is our per cpu area, only restore it if we are returning to
545 ACCOUNT_CPU_USER_EXIT(r2, r4)
562 b . /* prevent speculative execution */
565 #ifdef CONFIG_PREEMPT
566 andi. r0,r3,MSR_PR /* Returning to user mode? */
568 /* Check that preempt_count() == 0 and interrupts are enabled */
569 lwz r8,TI_PREEMPT(r9)
573 crandc eq,cr1*4+eq,eq
575 /* here we are preempting the current task */
578 stb r0,PACASOFTIRQEN(r13)
579 stb r0,PACAHARDIRQEN(r13)
581 mtmsrd r10,1 /* reenable interrupts */
584 clrrdi r9,r1,THREAD_SHIFT
585 rldicl r10,r10,48,1 /* disable interrupts again */
589 andi. r0,r4,_TIF_NEED_RESCHED
595 /* Enable interrupts */
599 andi. r0,r4,_TIF_NEED_RESCHED
602 b .ret_from_except_lite
606 addi r4,r1,STACK_FRAME_OVERHEAD
611 addi r3,r1,STACK_FRAME_OVERHEAD
612 bl .unrecoverable_exception
615 #ifdef CONFIG_PPC_RTAS
617 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
618 * called with the MMU off.
620 * In addition, we need to be in 32b mode, at least for now.
622 * Note: r3 is an input parameter to rtas, so don't trash it...
627 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
629 /* Because RTAS is running in 32b mode, it clobbers the high order half
630 * of all registers that it saves. We therefore save those registers
631 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
633 SAVE_GPR(2, r1) /* Save the TOC */
634 SAVE_GPR(13, r1) /* Save paca */
635 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
636 SAVE_10GPRS(22, r1) /* ditto */
653 /* Temporary workaround to clear CR until RTAS can be modified to
660 /* There is no way it is acceptable to get here with interrupts enabled,
661 * check it with the asm equivalent of WARN_ON
663 lbz r0,PACASOFTIRQEN(r13)
665 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
668 /* Hard-disable interrupts */
674 /* Unfortunately, the stack pointer and the MSR are also clobbered,
675 * so they are saved in the PACA which allows us to restore
676 * our original state after RTAS returns.
679 std r6,PACASAVEDMSR(r13)
681 /* Setup our real return addr */
682 LOAD_REG_ADDR(r4,.rtas_return_loc)
683 clrldi r4,r4,2 /* convert to realmode address */
687 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
691 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
692 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
695 sync /* disable interrupts so SRR0/1 */
696 mtmsrd r0 /* don't get trashed */
698 LOAD_REG_ADDR(r4, rtas)
699 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
700 ld r4,RTASBASE(r4) /* get the rtas->base value */
705 b . /* prevent speculative execution */
707 _STATIC(rtas_return_loc)
708 /* relocation is off at this point */
709 mfspr r4,SPRN_SPRG3 /* Get PACA */
710 clrldi r4,r4,2 /* convert to realmode address */
718 ld r1,PACAR1(r4) /* Restore our SP */
719 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
720 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
725 b . /* prevent speculative execution */
727 _STATIC(rtas_restore_regs)
728 /* relocation is on at this point */
729 REST_GPR(2, r1) /* Restore the TOC */
730 REST_GPR(13, r1) /* Restore paca */
731 REST_8GPRS(14, r1) /* Restore the non-volatiles */
732 REST_10GPRS(22, r1) /* ditto */
751 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
752 ld r0,16(r1) /* get return address */
755 blr /* return to caller */
757 #endif /* CONFIG_PPC_RTAS */
762 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
764 /* Because PROM is running in 32b mode, it clobbers the high order half
765 * of all registers that it saves. We therefore save those registers
766 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
789 /* Get the PROM entrypoint */
793 /* Switch MSR to 32 bits mode
797 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
800 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
805 /* Restore arguments & enter PROM here... */
809 /* Just make sure that r1 top 32 bits didn't get
814 /* Restore the MSR (back to 64 bits) */
819 /* Restore other registers */
839 addi r1,r1,PROM_FRAME_SIZE