2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 /* Default PCI flags is 0 */
39 unsigned int ppc_pci_flags;
41 void pcibios_make_OF_bus_map(void);
43 static void pcibios_fixup_resources(struct pci_dev* dev);
44 static void fixup_broken_pcnet32(struct pci_dev* dev);
45 static int reparent_resources(struct resource *parent, struct resource *res);
46 static void fixup_cpc710_pci64(struct pci_dev* dev);
48 static u8* pci_to_OF_bus_map;
51 /* By default, we don't re-assign bus numbers. We do this only on
54 static int pci_assign_all_buses;
58 static int pci_bus_count;
61 fixup_hide_host_resource_fsl(struct pci_dev* dev)
63 int i, class = dev->class >> 8;
65 if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
66 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
67 (dev->bus->parent == NULL)) {
68 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
69 dev->resource[i].start = 0;
70 dev->resource[i].end = 0;
71 dev->resource[i].flags = 0;
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
79 fixup_broken_pcnet32(struct pci_dev* dev)
81 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
82 dev->vendor = PCI_VENDOR_ID_AMD;
83 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
89 fixup_cpc710_pci64(struct pci_dev* dev)
91 /* Hide the PCI64 BARs from the kernel as their content doesn't
92 * fit well in the resource management
94 dev->resource[0].start = dev->resource[0].end = 0;
95 dev->resource[0].flags = 0;
96 dev->resource[1].start = dev->resource[1].end = 0;
97 dev->resource[1].flags = 0;
99 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
102 pcibios_fixup_resources(struct pci_dev *dev)
104 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
106 resource_size_t offset, mask;
109 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
112 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
113 struct resource *res = dev->resource + i;
116 if (res->end == 0xffffffff) {
117 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
118 pci_name(dev), i, (u64)res->start, (u64)res->end);
119 res->end -= res->start;
121 res->flags |= IORESOURCE_UNSET;
125 mask = (resource_size_t)-1;
126 if (res->flags & IORESOURCE_MEM) {
127 offset = hose->pci_mem_offset;
128 } else if (res->flags & IORESOURCE_IO) {
129 offset = (unsigned long) hose->io_base_virt
134 res->start = (res->start + offset) & mask;
135 res->end = (res->end + offset) & mask;
136 DBG("PCI: Fixup res %d (0x%lx) of dev %s: %llx -> %llx\n",
137 i, res->flags, pci_name(dev),
138 (u64)res->start - offset, (u64)res->start);
142 /* Call machine specific resource fixup */
143 if (ppc_md.pcibios_fixup_resources)
144 ppc_md.pcibios_fixup_resources(dev);
146 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
148 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
149 struct resource *res)
151 resource_size_t offset = 0, mask = (resource_size_t)-1;
152 struct pci_controller *hose = dev->sysdata;
154 if (hose && res->flags & IORESOURCE_IO) {
155 offset = (unsigned long)hose->io_base_virt - isa_io_base;
157 } else if (hose && res->flags & IORESOURCE_MEM)
158 offset = hose->pci_mem_offset;
159 region->start = (res->start - offset) & mask;
160 region->end = (res->end - offset) & mask;
162 EXPORT_SYMBOL(pcibios_resource_to_bus);
164 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
165 struct pci_bus_region *region)
167 resource_size_t offset = 0, mask = (resource_size_t)-1;
168 struct pci_controller *hose = dev->sysdata;
170 if (hose && res->flags & IORESOURCE_IO) {
171 offset = (unsigned long)hose->io_base_virt - isa_io_base;
173 } else if (hose && res->flags & IORESOURCE_MEM)
174 offset = hose->pci_mem_offset;
175 res->start = (region->start + offset) & mask;
176 res->end = (region->end + offset) & mask;
178 EXPORT_SYMBOL(pcibios_bus_to_resource);
180 static int skip_isa_ioresource_align(struct pci_dev *dev)
182 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
183 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
189 * We need to avoid collisions with `mirrored' VGA ports
190 * and other strange ISA hardware, so we always want the
191 * addresses to be allocated in the 0x000-0x0ff region
194 * Why? Because some silly external IO cards only decode
195 * the low 10 bits of the IO address. The 0x00-0xff region
196 * is reserved for motherboard devices that decode all 16
197 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
198 * but we want to try to avoid allocating at 0x2900-0x2bff
199 * which might have be mirrored at 0x0100-0x03ff..
201 void pcibios_align_resource(void *data, struct resource *res,
202 resource_size_t size, resource_size_t align)
204 struct pci_dev *dev = data;
206 if (res->flags & IORESOURCE_IO) {
207 resource_size_t start = res->start;
209 if (skip_isa_ioresource_align(dev))
212 start = (start + 0x3ff) & ~0x3ff;
217 EXPORT_SYMBOL(pcibios_align_resource);
220 * Handle resources of PCI devices. If the world were perfect, we could
221 * just allocate all the resource regions and do nothing more. It isn't.
222 * On the other hand, we cannot just re-allocate all devices, as it would
223 * require us to know lots of host bridge internals. So we attempt to
224 * keep as much of the original configuration as possible, but tweak it
225 * when it's found to be wrong.
227 * Known BIOS problems we have to work around:
228 * - I/O or memory regions not configured
229 * - regions configured, but not enabled in the command register
230 * - bogus I/O addresses above 64K used
231 * - expansion ROMs left enabled (this may sound harmless, but given
232 * the fact the PCI specs explicitly allow address decoders to be
233 * shared between expansion ROMs and other resource regions, it's
234 * at least dangerous)
237 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
238 * This gives us fixed barriers on where we can allocate.
239 * (2) Allocate resources for all enabled devices. If there is
240 * a collision, just mark the resource as unallocated. Also
241 * disable expansion ROMs during this step.
242 * (3) Try to allocate resources for disabled devices. If the
243 * resources were assigned correctly, everything goes well,
244 * if they weren't, they won't disturb allocation of other
246 * (4) Assign new addresses to resources which were either
247 * not configured at all or misconfigured. If explicitly
248 * requested by the user, configure expansion ROM address
253 pcibios_allocate_bus_resources(struct list_head *bus_list)
257 struct resource *res, *pr;
259 /* Depth-First Search on bus tree */
260 list_for_each_entry(bus, bus_list, node) {
261 for (i = 0; i < 4; ++i) {
262 if ((res = bus->resource[i]) == NULL || !res->flags
263 || res->start > res->end)
265 if (bus->parent == NULL)
266 pr = (res->flags & IORESOURCE_IO)?
267 &ioport_resource : &iomem_resource;
269 /* Don't bother with non-root busses when
270 * re-assigning all resources.
272 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
274 pr = pci_find_parent_resource(bus->self, res);
276 /* this happens when the generic PCI
277 * code (wrongly) decides that this
278 * bridge is transparent -- paulus
284 DBG("PCI: dev %s (bus 0x%02x) bridge rsrc %d: %016llx..%016llx "
285 "(f:0x%08lx), parent %p\n",
286 bus->self ? pci_name(bus->self) : "PHB", bus->number, i,
287 (u64)res->start, (u64)res->end, res->flags, pr);
289 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
290 if (request_resource(pr, res) == 0)
293 * Must be a conflict with an existing entry.
294 * Move that entry (or entries) under the
295 * bridge resource and try again.
297 if (reparent_resources(pr, res) == 0)
301 "PCI: Cannot allocate resource region "
302 "%d of PCI bridge %d, will remap\n",
304 res->flags |= IORESOURCE_UNSET;
306 pcibios_allocate_bus_resources(&bus->children);
311 * Reparent resource children of pr that conflict with res
312 * under res, and make res replace those children.
315 reparent_resources(struct resource *parent, struct resource *res)
317 struct resource *p, **pp;
318 struct resource **firstpp = NULL;
320 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
321 if (p->end < res->start)
323 if (res->end < p->start)
325 if (p->start < res->start || p->end > res->end)
326 return -1; /* not completely contained */
331 return -1; /* didn't find any conflicting entries? */
332 res->parent = parent;
333 res->child = *firstpp;
337 for (p = res->child; p != NULL; p = p->sibling) {
339 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
340 p->name, (u64)p->start, (u64)p->end, res->name);
346 update_bridge_resource(struct pci_dev *dev, struct resource *res)
348 u8 io_base_lo, io_limit_lo;
349 u16 mem_base, mem_limit;
351 resource_size_t start, end, off;
352 struct pci_controller *hose = dev->sysdata;
355 printk("update_bridge_base: no hose?\n");
358 pci_read_config_word(dev, PCI_COMMAND, &cmd);
359 pci_write_config_word(dev, PCI_COMMAND,
360 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
361 if (res->flags & IORESOURCE_IO) {
362 off = (unsigned long) hose->io_base_virt - isa_io_base;
363 start = res->start - off;
364 end = res->end - off;
365 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
366 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
368 io_base_lo |= PCI_IO_RANGE_TYPE_32;
370 io_base_lo |= PCI_IO_RANGE_TYPE_16;
371 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
373 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
375 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
376 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
378 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
380 off = hose->pci_mem_offset;
381 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
382 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
383 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
384 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
386 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
387 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
388 off = hose->pci_mem_offset;
389 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
390 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
391 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
392 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
395 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
396 pci_name(dev), res->flags);
398 pci_write_config_word(dev, PCI_COMMAND, cmd);
401 static inline void alloc_resource(struct pci_dev *dev, int idx)
403 struct resource *pr, *r = &dev->resource[idx];
405 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx (f=%lx)\n",
406 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
407 pr = pci_find_parent_resource(dev, r);
408 if (!pr || (pr->flags & IORESOURCE_UNSET) || request_resource(pr, r) < 0) {
409 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
410 " of device %s, will remap\n", idx, pci_name(dev));
412 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
413 pr, (u64)pr->start, (u64)pr->end, pr->flags);
414 /* We'll assign a new address later */
415 r->flags |= IORESOURCE_UNSET;
422 pcibios_allocate_resources(int pass)
424 struct pci_dev *dev = NULL;
429 for_each_pci_dev(dev) {
430 pci_read_config_word(dev, PCI_COMMAND, &command);
431 for (idx = 0; idx < 6; idx++) {
432 r = &dev->resource[idx];
433 if (r->parent) /* Already allocated */
435 if (!r->flags || (r->flags & IORESOURCE_UNSET))
436 continue; /* Not assigned at all */
437 if (r->flags & IORESOURCE_IO)
438 disabled = !(command & PCI_COMMAND_IO);
440 disabled = !(command & PCI_COMMAND_MEMORY);
441 if (pass == disabled)
442 alloc_resource(dev, idx);
446 r = &dev->resource[PCI_ROM_RESOURCE];
447 if (r->flags & IORESOURCE_ROM_ENABLE) {
448 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
450 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
451 r->flags &= ~IORESOURCE_ROM_ENABLE;
452 pci_read_config_dword(dev, dev->rom_base_reg, ®);
453 pci_write_config_dword(dev, dev->rom_base_reg,
454 reg & ~PCI_ROM_ADDRESS_ENABLE);
461 * Functions below are used on OpenFirmware machines.
464 make_one_node_map(struct device_node* node, u8 pci_bus)
466 const int *bus_range;
469 if (pci_bus >= pci_bus_count)
471 bus_range = of_get_property(node, "bus-range", &len);
472 if (bus_range == NULL || len < 2 * sizeof(int)) {
473 printk(KERN_WARNING "Can't get bus-range for %s, "
474 "assuming it starts at 0\n", node->full_name);
475 pci_to_OF_bus_map[pci_bus] = 0;
477 pci_to_OF_bus_map[pci_bus] = bus_range[0];
479 for (node=node->child; node != 0;node = node->sibling) {
481 const unsigned int *class_code, *reg;
483 class_code = of_get_property(node, "class-code", NULL);
484 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
485 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
487 reg = of_get_property(node, "reg", NULL);
490 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
491 if (!dev || !dev->subordinate) {
495 make_one_node_map(node, dev->subordinate->number);
501 pcibios_make_OF_bus_map(void)
504 struct pci_controller *hose, *tmp;
505 struct property *map_prop;
506 struct device_node *dn;
508 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
509 if (!pci_to_OF_bus_map) {
510 printk(KERN_ERR "Can't allocate OF bus map !\n");
514 /* We fill the bus map with invalid values, that helps
517 for (i=0; i<pci_bus_count; i++)
518 pci_to_OF_bus_map[i] = 0xff;
520 /* For each hose, we begin searching bridges */
521 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
522 struct device_node* node = hose->dn;
526 make_one_node_map(node, hose->first_busno);
528 dn = of_find_node_by_path("/");
529 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
531 BUG_ON(pci_bus_count > map_prop->length);
532 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
536 printk("PCI->OF bus map:\n");
537 for (i=0; i<pci_bus_count; i++) {
538 if (pci_to_OF_bus_map[i] == 0xff)
540 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
545 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
547 static struct device_node*
548 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
550 struct device_node* sub_node;
552 for (; node != 0;node = node->sibling) {
553 const unsigned int *class_code;
555 if (filter(node, data))
558 /* For PCI<->PCI bridges or CardBus bridges, we go down
559 * Note: some OFs create a parent node "multifunc-device" as
560 * a fake root for all functions of a multi-function device,
561 * we go down them as well.
563 class_code = of_get_property(node, "class-code", NULL);
564 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
565 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
566 strcmp(node->name, "multifunc-device"))
568 sub_node = scan_OF_pci_childs(node->child, filter, data);
575 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
578 struct device_node *np = NULL;
582 while ((np = of_get_next_child(parent, np)) != NULL) {
583 reg = of_get_property(np, "reg", &psize);
584 if (reg == NULL || psize < 4)
586 if (((reg[0] >> 8) & 0xff) == devfn)
593 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
595 struct device_node *parent, *np;
597 /* Are we a root bus ? */
598 if (bus->self == NULL || bus->parent == NULL) {
599 struct pci_controller *hose = pci_bus_to_host(bus);
602 return of_node_get(hose->dn);
605 /* not a root bus, we need to get our parent */
606 parent = scan_OF_for_pci_bus(bus->parent);
610 /* now iterate for children for a match */
611 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
618 * Scans the OF tree for a device node matching a PCI device
621 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
623 struct device_node *parent, *np;
628 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
629 parent = scan_OF_for_pci_bus(bus);
632 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
633 np = scan_OF_for_pci_dev(parent, devfn);
635 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
637 /* XXX most callers don't release the returned node
638 * mostly because ppc64 doesn't increase the refcount,
639 * we need to fix that.
643 EXPORT_SYMBOL(pci_busdev_to_OF_node);
646 pci_device_to_OF_node(struct pci_dev *dev)
648 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
650 EXPORT_SYMBOL(pci_device_to_OF_node);
653 find_OF_pci_device_filter(struct device_node* node, void* data)
655 return ((void *)node == data);
659 * Returns the PCI device matching a given OF node
662 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
664 const unsigned int *reg;
665 struct pci_controller* hose;
666 struct pci_dev* dev = NULL;
670 /* Make sure it's really a PCI device */
671 hose = pci_find_hose_for_OF_device(node);
672 if (!hose || !hose->dn)
674 if (!scan_OF_pci_childs(hose->dn->child,
675 find_OF_pci_device_filter, (void *)node))
677 reg = of_get_property(node, "reg", NULL);
680 *bus = (reg[0] >> 16) & 0xff;
681 *devfn = ((reg[0] >> 8) & 0xff);
683 /* Ok, here we need some tweak. If we have already renumbered
684 * all busses, we can't rely on the OF bus number any more.
685 * the pci_to_OF_bus_map is not enough as several PCI busses
686 * may match the same OF bus number.
688 if (!pci_to_OF_bus_map)
691 for_each_pci_dev(dev)
692 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
693 dev->devfn == *devfn) {
694 *bus = dev->bus->number;
701 EXPORT_SYMBOL(pci_device_from_OF_node);
703 /* We create the "pci-OF-bus-map" property now so it appears in the
707 pci_create_OF_bus_map(void)
709 struct property* of_prop;
710 struct device_node *dn;
712 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
715 dn = of_find_node_by_path("/");
717 memset(of_prop, -1, sizeof(struct property) + 256);
718 of_prop->name = "pci-OF-bus-map";
719 of_prop->length = 256;
720 of_prop->value = &of_prop[1];
721 prom_add_property(dn, of_prop);
726 #else /* CONFIG_PPC_OF */
727 void pcibios_make_OF_bus_map(void)
730 #endif /* CONFIG_PPC_OF */
735 struct pci_controller *hose, *tmp;
739 printk(KERN_INFO "PCI: Probing PCI hardware\n");
741 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS)
742 pci_assign_all_buses = 1;
744 /* Scan all of the recorded PCI controllers. */
745 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
746 if (pci_assign_all_buses)
747 hose->first_busno = next_busno;
748 hose->last_busno = 0xff;
749 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
752 pci_bus_add_devices(bus);
753 hose->last_busno = bus->subordinate;
754 if (pci_assign_all_buses || next_busno <= hose->last_busno)
755 next_busno = hose->last_busno + pcibios_assign_bus_offset;
757 pci_bus_count = next_busno;
759 /* OpenFirmware based machines need a map of OF bus
760 * numbers vs. kernel bus numbers since we may have to
763 if (pci_assign_all_buses && have_of)
764 pcibios_make_OF_bus_map();
766 /* Call machine dependent fixup */
767 if (ppc_md.pcibios_fixup)
768 ppc_md.pcibios_fixup();
770 /* Allocate and assign resources. If we re-assign everything, then
771 * we skip the allocate phase
773 pcibios_allocate_bus_resources(&pci_root_buses);
774 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
775 pcibios_allocate_resources(0);
776 pcibios_allocate_resources(1);
778 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
779 DBG("PCI: Assigning unassigned resouces...\n");
780 pci_assign_unassigned_resources();
783 /* Call machine dependent post-init code */
784 if (ppc_md.pcibios_after_init)
785 ppc_md.pcibios_after_init();
790 subsys_initcall(pcibios_init);
792 void pcibios_fixup_bus(struct pci_bus *bus)
794 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
795 unsigned long io_offset;
796 struct resource *res;
800 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
801 if (bus->parent == NULL) {
802 /* This is a host bridge - fill in its resources */
805 bus->resource[0] = res = &hose->io_resource;
808 printk(KERN_ERR "I/O resource not set for host"
809 " bridge %d\n", hose->global_number);
811 res->end = IO_SPACE_LIMIT;
812 res->flags = IORESOURCE_IO;
814 res->start = (res->start + io_offset) & 0xffffffffu;
815 res->end = (res->end + io_offset) & 0xffffffffu;
817 for (i = 0; i < 3; ++i) {
818 res = &hose->mem_resources[i];
822 printk(KERN_ERR "Memory resource not set for "
823 "host bridge %d\n", hose->global_number);
824 res->start = hose->pci_mem_offset;
826 res->flags = IORESOURCE_MEM;
828 bus->resource[i+1] = res;
831 /* This is a subordinate bridge */
832 pci_read_bridge_bases(bus);
834 for (i = 0; i < 4; ++i) {
835 if ((res = bus->resource[i]) == NULL)
837 if (!res->flags || bus->self->transparent)
839 if (io_offset && (res->flags & IORESOURCE_IO)) {
840 res->start = (res->start + io_offset) &
842 res->end = (res->end + io_offset) &
844 } else if (hose->pci_mem_offset
845 && (res->flags & IORESOURCE_MEM)) {
846 res->start += hose->pci_mem_offset;
847 res->end += hose->pci_mem_offset;
852 /* Platform specific bus fixups */
853 if (ppc_md.pcibios_fixup_bus)
854 ppc_md.pcibios_fixup_bus(bus);
856 /* Read default IRQs and fixup if necessary */
857 list_for_each_entry(dev, &bus->devices, bus_list) {
858 pci_read_irq_line(dev);
859 if (ppc_md.pci_irq_fixup)
860 ppc_md.pci_irq_fixup(dev);
864 /* the next one is stolen from the alpha port... */
866 pcibios_update_irq(struct pci_dev *dev, int irq)
868 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
869 /* XXX FIXME - update OF device tree node interrupt property */
872 int pcibios_enable_device(struct pci_dev *dev, int mask)
878 if (ppc_md.pcibios_enable_device_hook)
879 if (ppc_md.pcibios_enable_device_hook(dev, 0))
882 pci_read_config_word(dev, PCI_COMMAND, &cmd);
884 for (idx=0; idx<6; idx++) {
885 r = &dev->resource[idx];
886 if (r->flags & IORESOURCE_UNSET) {
887 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
890 if (r->flags & IORESOURCE_IO)
891 cmd |= PCI_COMMAND_IO;
892 if (r->flags & IORESOURCE_MEM)
893 cmd |= PCI_COMMAND_MEMORY;
895 if (cmd != old_cmd) {
896 printk("PCI: Enabling device %s (%04x -> %04x)\n",
897 pci_name(dev), old_cmd, cmd);
898 pci_write_config_word(dev, PCI_COMMAND, cmd);
903 static struct pci_controller*
904 pci_bus_to_hose(int bus)
906 struct pci_controller *hose, *tmp;
908 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
909 if (bus >= hose->first_busno && bus <= hose->last_busno)
914 /* Provide information on locations of various I/O regions in physical
915 * memory. Do this on a per-card basis so that we choose the right
917 * Note that the returned IO or memory base is a physical address
920 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
922 struct pci_controller* hose;
923 long result = -EOPNOTSUPP;
925 hose = pci_bus_to_hose(bus);
930 case IOBASE_BRIDGE_NUMBER:
931 return (long)hose->first_busno;
933 return (long)hose->pci_mem_offset;
935 return (long)hose->io_base_phys;
937 return (long)isa_io_base;
939 return (long)isa_mem_base;
945 unsigned long pci_address_to_pio(phys_addr_t address)
947 struct pci_controller *hose, *tmp;
949 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
950 unsigned int size = hose->io_resource.end -
951 hose->io_resource.start + 1;
952 if (address >= hose->io_base_phys &&
953 address < (hose->io_base_phys + size)) {
955 (unsigned long)hose->io_base_virt - _IO_BASE;
956 return base + (address - hose->io_base_phys);
959 return (unsigned int)-1;
961 EXPORT_SYMBOL(pci_address_to_pio);
964 * Null PCI config access functions, for the case when we can't
967 #define NULL_PCI_OP(rw, size, type) \
969 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
971 return PCIBIOS_DEVICE_NOT_FOUND; \
975 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
978 return PCIBIOS_DEVICE_NOT_FOUND;
982 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
985 return PCIBIOS_DEVICE_NOT_FOUND;
988 static struct pci_ops null_pci_ops =
990 .read = null_read_config,
991 .write = null_write_config,
995 * These functions are used early on before PCI scanning is done
996 * and all of the pci_dev and pci_bus structures have been created.
998 static struct pci_bus *
999 fake_pci_bus(struct pci_controller *hose, int busnr)
1001 static struct pci_bus bus;
1004 hose = pci_bus_to_hose(busnr);
1006 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1010 bus.ops = hose? hose->ops: &null_pci_ops;
1014 #define EARLY_PCI_OP(rw, size, type) \
1015 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1016 int devfn, int offset, type value) \
1018 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1019 devfn, offset, value); \
1022 EARLY_PCI_OP(read, byte, u8 *)
1023 EARLY_PCI_OP(read, word, u16 *)
1024 EARLY_PCI_OP(read, dword, u32 *)
1025 EARLY_PCI_OP(write, byte, u8)
1026 EARLY_PCI_OP(write, word, u16)
1027 EARLY_PCI_OP(write, dword, u32)
1029 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1030 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1033 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);