2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
48 /* pci_io_base -- the base address from which io bars are offsets.
49 * This is the lowest I/O base address (so bar values are always positive),
50 * and it *must* be the start of ISA space if an ISA bus exists because
51 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
52 * is mapped on the first 64K of IO space
54 unsigned long pci_io_base = ISA_IO_BASE;
55 EXPORT_SYMBOL(pci_io_base);
59 static struct dma_mapping_ops *pci_dma_ops;
61 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
63 pci_dma_ops = dma_ops;
66 struct dma_mapping_ops *get_pci_dma_ops(void)
70 EXPORT_SYMBOL(get_pci_dma_ops);
73 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
75 return dma_set_mask(&dev->dev, mask);
78 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
82 rc = dma_set_mask(&dev->dev, mask);
83 dev->dev.coherent_dma_mask = dev->dma_mask;
88 static void fixup_broken_pcnet32(struct pci_dev* dev)
90 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
91 dev->vendor = PCI_VENDOR_ID_AMD;
92 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
95 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
97 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
100 unsigned long offset = 0;
101 struct pci_controller *hose = pci_bus_to_host(dev->bus);
106 if (res->flags & IORESOURCE_IO)
107 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
109 if (res->flags & IORESOURCE_MEM)
110 offset = hose->pci_mem_offset;
112 region->start = res->start - offset;
113 region->end = res->end - offset;
116 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
117 struct pci_bus_region *region)
119 unsigned long offset = 0;
120 struct pci_controller *hose = pci_bus_to_host(dev->bus);
125 if (res->flags & IORESOURCE_IO)
126 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
128 if (res->flags & IORESOURCE_MEM)
129 offset = hose->pci_mem_offset;
131 res->start = region->start + offset;
132 res->end = region->end + offset;
135 #ifdef CONFIG_HOTPLUG
136 EXPORT_SYMBOL(pcibios_resource_to_bus);
137 EXPORT_SYMBOL(pcibios_bus_to_resource);
141 * We need to avoid collisions with `mirrored' VGA ports
142 * and other strange ISA hardware, so we always want the
143 * addresses to be allocated in the 0x000-0x0ff region
146 * Why? Because some silly external IO cards only decode
147 * the low 10 bits of the IO address. The 0x00-0xff region
148 * is reserved for motherboard devices that decode all 16
149 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
150 * but we want to try to avoid allocating at 0x2900-0x2bff
151 * which might have be mirrored at 0x0100-0x03ff..
153 void pcibios_align_resource(void *data, struct resource *res,
154 resource_size_t size, resource_size_t align)
156 struct pci_dev *dev = data;
157 struct pci_controller *hose = pci_bus_to_host(dev->bus);
158 resource_size_t start = res->start;
159 unsigned long alignto;
161 if (res->flags & IORESOURCE_IO) {
162 unsigned long offset = (unsigned long)hose->io_base_virt -
164 /* Make sure we start at our min on all hoses */
165 if (start - offset < PCIBIOS_MIN_IO)
166 start = PCIBIOS_MIN_IO + offset;
169 * Put everything into 0x00-0xff region modulo 0x400
172 start = (start + 0x3ff) & ~0x3ff;
174 } else if (res->flags & IORESOURCE_MEM) {
175 /* Make sure we start at our min on all hoses */
176 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
177 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
179 /* Align to multiple of size of minimum base. */
180 alignto = max(0x1000UL, align);
181 start = ALIGN(start, alignto);
187 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
190 struct pci_bus *child_bus;
192 list_for_each_entry(dev, &b->devices, bus_list) {
195 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
196 struct resource *r = &dev->resource[i];
198 if (r->parent || !r->start || !r->flags)
200 pci_claim_resource(dev, i);
204 list_for_each_entry(child_bus, &b->children, node)
205 pcibios_claim_one_bus(child_bus);
207 #ifdef CONFIG_HOTPLUG
208 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
211 static void __init pcibios_claim_of_setup(void)
215 list_for_each_entry(b, &pci_root_buses, node)
216 pcibios_claim_one_bus(b);
219 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
224 prop = of_get_property(np, name, &len);
225 if (prop && len >= 4)
230 static unsigned int pci_parse_of_flags(u32 addr0)
232 unsigned int flags = 0;
234 if (addr0 & 0x02000000) {
235 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
236 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
237 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
238 if (addr0 & 0x40000000)
239 flags |= IORESOURCE_PREFETCH
240 | PCI_BASE_ADDRESS_MEM_PREFETCH;
241 } else if (addr0 & 0x01000000)
242 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
247 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
251 struct resource *res;
256 addrs = of_get_property(node, "assigned-addresses", &proplen);
259 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
260 for (; proplen >= 20; proplen -= 20, addrs += 5) {
261 flags = pci_parse_of_flags(addrs[0]);
264 base = of_read_number(&addrs[1], 2);
265 size = of_read_number(&addrs[3], 2);
269 DBG(" base: %llx, size: %llx, i: %x\n",
270 (unsigned long long)base, (unsigned long long)size, i);
272 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
273 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
274 } else if (i == dev->rom_base_reg) {
275 res = &dev->resource[PCI_ROM_RESOURCE];
276 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
278 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
282 res->end = base + size - 1;
284 res->name = pci_name(dev);
285 fixup_resource(res, dev);
289 struct pci_dev *of_create_pci_dev(struct device_node *node,
290 struct pci_bus *bus, int devfn)
295 dev = alloc_pci_dev();
298 type = of_get_property(node, "device_type", NULL);
302 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
306 dev->dev.parent = bus->bridge;
307 dev->dev.bus = &pci_bus_type;
309 dev->multifunction = 0; /* maybe a lie? */
311 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
312 dev->device = get_int_prop(node, "device-id", 0xffff);
313 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
314 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
316 dev->cfg_size = pci_cfg_space_size(dev);
318 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
319 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
320 dev->class = get_int_prop(node, "class-code", 0);
321 dev->revision = get_int_prop(node, "revision-id", 0);
323 DBG(" class: 0x%x\n", dev->class);
324 DBG(" revision: 0x%x\n", dev->revision);
326 dev->current_state = 4; /* unknown power state */
327 dev->error_state = pci_channel_io_normal;
328 dev->dma_mask = 0xffffffff;
330 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
331 /* a PCI-PCI bridge */
332 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
333 dev->rom_base_reg = PCI_ROM_ADDRESS1;
334 } else if (!strcmp(type, "cardbus")) {
335 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
337 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
338 dev->rom_base_reg = PCI_ROM_ADDRESS;
339 /* Maybe do a default OF mapping here */
343 pci_parse_of_addrs(node, dev);
345 DBG(" adding to system ...\n");
347 pci_device_add(dev, bus);
351 EXPORT_SYMBOL(of_create_pci_dev);
353 void __devinit of_scan_bus(struct device_node *node,
356 struct device_node *child = NULL;
361 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
363 while ((child = of_get_next_child(node, child)) != NULL) {
364 DBG(" * %s\n", child->full_name);
365 reg = of_get_property(child, "reg", ®len);
366 if (reg == NULL || reglen < 20)
368 devfn = (reg[0] >> 8) & 0xff;
370 /* create a new pci_dev for this device */
371 dev = of_create_pci_dev(child, bus, devfn);
374 DBG("dev header type: %x\n", dev->hdr_type);
376 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
377 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
378 of_scan_pci_bridge(child, dev);
383 EXPORT_SYMBOL(of_scan_bus);
385 void __devinit of_scan_pci_bridge(struct device_node *node,
389 const u32 *busrange, *ranges;
391 struct resource *res;
395 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
397 /* parse bus-range property */
398 busrange = of_get_property(node, "bus-range", &len);
399 if (busrange == NULL || len != 8) {
400 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
404 ranges = of_get_property(node, "ranges", &len);
405 if (ranges == NULL) {
406 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
411 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
413 printk(KERN_ERR "Failed to create pci bus for %s\n",
418 bus->primary = dev->bus->number;
419 bus->subordinate = busrange[1];
423 /* parse ranges property */
424 /* PCI #address-cells == 3 and #size-cells == 2 always */
425 res = &dev->resource[PCI_BRIDGE_RESOURCES];
426 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
428 bus->resource[i] = res;
432 for (; len >= 32; len -= 32, ranges += 8) {
433 flags = pci_parse_of_flags(ranges[0]);
434 size = of_read_number(&ranges[6], 2);
435 if (flags == 0 || size == 0)
437 if (flags & IORESOURCE_IO) {
438 res = bus->resource[0];
440 printk(KERN_ERR "PCI: ignoring extra I/O range"
441 " for bridge %s\n", node->full_name);
445 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
446 printk(KERN_ERR "PCI: too many memory ranges"
447 " for bridge %s\n", node->full_name);
450 res = bus->resource[i];
453 res->start = of_read_number(&ranges[1], 2);
454 res->end = res->start + size - 1;
456 fixup_resource(res, dev);
458 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
460 DBG(" bus name: %s\n", bus->name);
462 mode = PCI_PROBE_NORMAL;
463 if (ppc_md.pci_probe_mode)
464 mode = ppc_md.pci_probe_mode(bus);
465 DBG(" probe mode: %d\n", mode);
467 if (mode == PCI_PROBE_DEVTREE)
468 of_scan_bus(node, bus);
469 else if (mode == PCI_PROBE_NORMAL)
470 pci_scan_child_bus(bus);
472 EXPORT_SYMBOL(of_scan_pci_bridge);
474 void __devinit scan_phb(struct pci_controller *hose)
477 struct device_node *node = hose->dn;
479 struct resource *res;
481 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
483 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
485 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
486 hose->global_number);
489 bus->secondary = hose->first_busno;
492 pcibios_map_io_space(bus);
494 bus->resource[0] = res = &hose->io_resource;
495 if (res->flags && request_resource(&ioport_resource, res)) {
496 printk(KERN_ERR "Failed to request PCI IO region "
497 "on PCI domain %04x\n", hose->global_number);
498 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
499 res->start, res->end);
502 for (i = 0; i < 3; ++i) {
503 res = &hose->mem_resources[i];
504 bus->resource[i+1] = res;
505 if (res->flags && request_resource(&iomem_resource, res))
506 printk(KERN_ERR "Failed to request PCI memory region "
507 "on PCI domain %04x\n", hose->global_number);
510 mode = PCI_PROBE_NORMAL;
512 if (node && ppc_md.pci_probe_mode)
513 mode = ppc_md.pci_probe_mode(bus);
514 DBG(" probe mode: %d\n", mode);
515 if (mode == PCI_PROBE_DEVTREE) {
516 bus->subordinate = hose->last_busno;
517 of_scan_bus(node, bus);
520 if (mode == PCI_PROBE_NORMAL)
521 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
524 static int __init pcibios_init(void)
526 struct pci_controller *hose, *tmp;
528 /* For now, override phys_mem_access_prot. If we need it,
529 * later, we may move that initialization to each ppc_md
531 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
533 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
535 /* Scan all of the recorded PCI controllers. */
536 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
538 pci_bus_add_devices(hose->bus);
542 pcibios_claim_of_setup();
544 /* FIXME: `else' will be removed when
545 pci_assign_unassigned_resources() is able to work
546 correctly with [partially] allocated PCI tree. */
547 pci_assign_unassigned_resources();
549 /* Call machine dependent final fixup */
550 if (ppc_md.pcibios_fixup)
551 ppc_md.pcibios_fixup();
553 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
558 subsys_initcall(pcibios_init);
560 int pcibios_enable_device(struct pci_dev *dev, int mask)
565 pci_read_config_word(dev, PCI_COMMAND, &cmd);
568 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
569 struct resource *res = &dev->resource[i];
571 /* Only set up the requested stuff */
572 if (!(mask & (1<<i)))
575 if (res->flags & IORESOURCE_IO)
576 cmd |= PCI_COMMAND_IO;
577 if (res->flags & IORESOURCE_MEM)
578 cmd |= PCI_COMMAND_MEMORY;
582 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
584 /* Enable the appropriate bits in the PCI command register. */
585 pci_write_config_word(dev, PCI_COMMAND, cmd);
590 /* Decide whether to display the domain number in /proc */
591 int pci_proc_domain(struct pci_bus *bus)
593 struct pci_controller *hose = pci_bus_to_host(bus);
594 return hose->buid != 0;
598 #ifdef CONFIG_HOTPLUG
600 int pcibios_unmap_io_space(struct pci_bus *bus)
602 struct pci_controller *hose;
604 WARN_ON(bus == NULL);
606 /* If this is not a PHB, we only flush the hash table over
607 * the area mapped by this bridge. We don't play with the PTE
608 * mappings since we might have to deal with sub-page alignemnts
609 * so flushing the hash table is the only sane way to make sure
610 * that no hash entries are covering that removed bridge area
611 * while still allowing other busses overlapping those pages
614 struct resource *res = bus->resource[0];
616 DBG("IO unmapping for PCI-PCI bridge %s\n",
617 pci_name(bus->self));
619 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
620 res->end - res->start + 1);
624 /* Get the host bridge */
625 hose = pci_bus_to_host(bus);
627 /* Check if we have IOs allocated */
628 if (hose->io_base_alloc == 0)
631 DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
632 DBG(" alloc=0x%p\n", hose->io_base_alloc);
634 /* This is a PHB, we fully unmap the IO area */
635 vunmap(hose->io_base_alloc);
639 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
641 #endif /* CONFIG_HOTPLUG */
643 int __devinit pcibios_map_io_space(struct pci_bus *bus)
645 struct vm_struct *area;
646 unsigned long phys_page;
647 unsigned long size_page;
648 unsigned long io_virt_offset;
649 struct pci_controller *hose;
651 WARN_ON(bus == NULL);
653 /* If this not a PHB, nothing to do, page tables still exist and
654 * thus HPTEs will be faulted in when needed
657 DBG("IO mapping for PCI-PCI bridge %s\n",
658 pci_name(bus->self));
659 DBG(" virt=0x%016lx...0x%016lx\n",
660 bus->resource[0]->start + _IO_BASE,
661 bus->resource[0]->end + _IO_BASE);
665 /* Get the host bridge */
666 hose = pci_bus_to_host(bus);
667 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
668 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
670 /* Make sure IO area address is clear */
671 hose->io_base_alloc = NULL;
673 /* If there's no IO to map on that bus, get away too */
674 if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
677 /* Let's allocate some IO space for that guy. We don't pass
678 * VM_IOREMAP because we don't care about alignment tricks that
679 * the core does in that case. Maybe we should due to stupid card
680 * with incomplete address decoding but I'd rather not deal with
681 * those outside of the reserved 64K legacy region.
683 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
686 hose->io_base_alloc = area->addr;
687 hose->io_base_virt = (void __iomem *)(area->addr +
688 hose->io_base_phys - phys_page);
690 DBG("IO mapping for PHB %s\n", hose->dn->full_name);
691 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
692 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
693 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
694 hose->pci_io_size, size_page);
696 /* Establish the mapping */
697 if (__ioremap_at(phys_page, area->addr, size_page,
698 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
701 /* Fixup hose IO resource */
702 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
703 hose->io_resource.start += io_virt_offset;
704 hose->io_resource.end += io_virt_offset;
706 DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
707 hose->io_resource.start, hose->io_resource.end);
711 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
713 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
715 struct pci_controller *hose = pci_bus_to_host(dev->bus);
716 unsigned long offset;
718 if (res->flags & IORESOURCE_IO) {
719 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
720 res->start += offset;
722 } else if (res->flags & IORESOURCE_MEM) {
723 res->start += hose->pci_mem_offset;
724 res->end += hose->pci_mem_offset;
728 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
731 /* Update device resources. */
734 DBG("%s: Fixup resources:\n", pci_name(dev));
735 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
736 struct resource *res = &dev->resource[i];
740 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
741 i, res->flags, res->start, res->end);
743 fixup_resource(res, dev);
745 DBG(" > %08lx:0x%016lx...0x%016lx\n",
746 res->flags, res->start, res->end);
749 EXPORT_SYMBOL(pcibios_fixup_device_resources);
751 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
753 struct dev_archdata *sd = &dev->dev.archdata;
755 sd->of_node = pci_device_to_OF_node(dev);
757 DBG("PCI device %s OF node: %s\n", pci_name(dev),
758 sd->of_node ? sd->of_node->full_name : "<none>");
760 sd->dma_ops = pci_dma_ops;
762 sd->numa_node = pcibus_to_node(dev->bus);
766 if (ppc_md.pci_dma_dev_setup)
767 ppc_md.pci_dma_dev_setup(dev);
769 EXPORT_SYMBOL(pcibios_setup_new_device);
771 static void __devinit do_bus_setup(struct pci_bus *bus)
775 if (ppc_md.pci_dma_bus_setup)
776 ppc_md.pci_dma_bus_setup(bus);
778 list_for_each_entry(dev, &bus->devices, bus_list)
779 pcibios_setup_new_device(dev);
781 /* Read default IRQs and fixup if necessary */
782 list_for_each_entry(dev, &bus->devices, bus_list) {
783 pci_read_irq_line(dev);
784 if (ppc_md.pci_irq_fixup)
785 ppc_md.pci_irq_fixup(dev);
789 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
791 struct pci_dev *dev = bus->self;
792 struct device_node *np;
794 np = pci_bus_to_OF_node(bus);
796 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
798 if (dev && pci_probe_only &&
799 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
800 /* This is a subordinate bridge */
802 pci_read_bridge_bases(bus);
803 pcibios_fixup_device_resources(dev, bus);
811 list_for_each_entry(dev, &bus->devices, bus_list)
812 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
813 pcibios_fixup_device_resources(dev, bus);
815 EXPORT_SYMBOL(pcibios_fixup_bus);
817 unsigned long pci_address_to_pio(phys_addr_t address)
819 struct pci_controller *hose, *tmp;
821 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
822 if (address >= hose->io_base_phys &&
823 address < (hose->io_base_phys + hose->pci_io_size)) {
825 (unsigned long)hose->io_base_virt - _IO_BASE;
826 return base + (address - hose->io_base_phys);
829 return (unsigned int)-1;
831 EXPORT_SYMBOL_GPL(pci_address_to_pio);
834 #define IOBASE_BRIDGE_NUMBER 0
835 #define IOBASE_MEMORY 1
837 #define IOBASE_ISA_IO 3
838 #define IOBASE_ISA_MEM 4
840 long sys_pciconfig_iobase(long which, unsigned long in_bus,
841 unsigned long in_devfn)
843 struct pci_controller* hose;
844 struct list_head *ln;
845 struct pci_bus *bus = NULL;
846 struct device_node *hose_node;
848 /* Argh ! Please forgive me for that hack, but that's the
849 * simplest way to get existing XFree to not lockup on some
850 * G5 machines... So when something asks for bus 0 io base
851 * (bus 0 is HT root), we return the AGP one instead.
853 if (machine_is_compatible("MacRISC4"))
857 /* That syscall isn't quite compatible with PCI domains, but it's
858 * used on pre-domains setup. We return the first match
861 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
863 if (in_bus >= bus->number && in_bus <= bus->subordinate)
867 if (bus == NULL || bus->sysdata == NULL)
870 hose_node = (struct device_node *)bus->sysdata;
871 hose = PCI_DN(hose_node)->phb;
874 case IOBASE_BRIDGE_NUMBER:
875 return (long)hose->first_busno;
877 return (long)hose->pci_mem_offset;
879 return (long)hose->io_base_phys;
881 return (long)isa_io_base;
890 int pcibus_to_node(struct pci_bus *bus)
892 struct pci_controller *phb = pci_bus_to_host(bus);
895 EXPORT_SYMBOL(pcibus_to_node);