2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource *res, struct pci_dev *dev);
55 static void do_bus_setup(struct pci_bus *bus);
56 static void phbs_remap_io(void);
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base; /* NULL if no ISA bus */
66 EXPORT_SYMBOL(isa_io_base);
67 unsigned long pci_io_base;
68 EXPORT_SYMBOL(pci_io_base);
70 void iSeries_pcibios_init(void);
74 struct dma_mapping_ops pci_dma_ops;
75 EXPORT_SYMBOL(pci_dma_ops);
77 int global_phb_number; /* Global phb counter */
79 /* Cached ISA bridge dev. */
80 struct pci_dev *ppc64_isabridge_dev = NULL;
82 static void fixup_broken_pcnet32(struct pci_dev* dev)
84 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
85 dev->vendor = PCI_VENDOR_ID_AMD;
86 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
89 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
91 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
94 unsigned long offset = 0;
95 struct pci_controller *hose = pci_bus_to_host(dev->bus);
100 if (res->flags & IORESOURCE_IO)
101 offset = (unsigned long)hose->io_base_virt - pci_io_base;
103 if (res->flags & IORESOURCE_MEM)
104 offset = hose->pci_mem_offset;
106 region->start = res->start - offset;
107 region->end = res->end - offset;
110 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
111 struct pci_bus_region *region)
113 unsigned long offset = 0;
114 struct pci_controller *hose = pci_bus_to_host(dev->bus);
119 if (res->flags & IORESOURCE_IO)
120 offset = (unsigned long)hose->io_base_virt - pci_io_base;
122 if (res->flags & IORESOURCE_MEM)
123 offset = hose->pci_mem_offset;
125 res->start = region->start + offset;
126 res->end = region->end + offset;
129 #ifdef CONFIG_HOTPLUG
130 EXPORT_SYMBOL(pcibios_resource_to_bus);
131 EXPORT_SYMBOL(pcibios_bus_to_resource);
135 * We need to avoid collisions with `mirrored' VGA ports
136 * and other strange ISA hardware, so we always want the
137 * addresses to be allocated in the 0x000-0x0ff region
140 * Why? Because some silly external IO cards only decode
141 * the low 10 bits of the IO address. The 0x00-0xff region
142 * is reserved for motherboard devices that decode all 16
143 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
144 * but we want to try to avoid allocating at 0x2900-0x2bff
145 * which might have be mirrored at 0x0100-0x03ff..
147 void pcibios_align_resource(void *data, struct resource *res,
148 unsigned long size, unsigned long align)
150 struct pci_dev *dev = data;
151 struct pci_controller *hose = pci_bus_to_host(dev->bus);
152 unsigned long start = res->start;
153 unsigned long alignto;
155 if (res->flags & IORESOURCE_IO) {
156 unsigned long offset = (unsigned long)hose->io_base_virt -
158 /* Make sure we start at our min on all hoses */
159 if (start - offset < PCIBIOS_MIN_IO)
160 start = PCIBIOS_MIN_IO + offset;
163 * Put everything into 0x00-0xff region modulo 0x400
166 start = (start + 0x3ff) & ~0x3ff;
168 } else if (res->flags & IORESOURCE_MEM) {
169 /* Make sure we start at our min on all hoses */
170 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
171 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
173 /* Align to multiple of size of minimum base. */
174 alignto = max(0x1000UL, align);
175 start = ALIGN(start, alignto);
181 static DEFINE_SPINLOCK(hose_spinlock);
184 * pci_controller(phb) initialized common variables.
186 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
188 memset(hose, 0, sizeof(struct pci_controller));
190 spin_lock(&hose_spinlock);
191 hose->global_number = global_phb_number++;
192 list_add_tail(&hose->list_node, &hose_list);
193 spin_unlock(&hose_spinlock);
196 static void add_linux_pci_domain(struct device_node *dev,
197 struct pci_controller *phb)
199 struct property *of_prop;
202 of_prop = (struct property *)
203 get_property(dev, "linux,pci-domain", &size);
206 WARN_ON(of_prop && size < sizeof(int));
207 if (of_prop && size < sizeof(int))
209 size = sizeof(struct property) + sizeof(int);
210 if (of_prop == NULL) {
212 of_prop = kmalloc(size, GFP_KERNEL);
214 of_prop = alloc_bootmem(size);
216 memset(of_prop, 0, sizeof(struct property));
217 of_prop->name = "linux,pci-domain";
218 of_prop->length = sizeof(int);
219 of_prop->value = (unsigned char *)&of_prop[1];
220 *((int *)of_prop->value) = phb->global_number;
221 prom_add_property(dev, of_prop);
224 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
226 struct pci_controller *phb;
229 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
231 phb = alloc_bootmem(sizeof (struct pci_controller));
234 pci_setup_pci_controller(phb);
235 phb->arch_data = dev;
236 phb->is_dynamic = mem_init_done;
238 add_linux_pci_domain(dev, phb);
242 void pcibios_free_controller(struct pci_controller *phb)
244 if (phb->arch_data) {
245 struct device_node *np = phb->arch_data;
246 int *domain = (int *)get_property(np,
247 "linux,pci-domain", NULL);
255 #ifndef CONFIG_PPC_ISERIES
256 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
259 struct pci_bus *child_bus;
261 list_for_each_entry(dev, &b->devices, bus_list) {
264 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
265 struct resource *r = &dev->resource[i];
267 if (r->parent || !r->start || !r->flags)
269 pci_claim_resource(dev, i);
273 list_for_each_entry(child_bus, &b->children, node)
274 pcibios_claim_one_bus(child_bus);
276 #ifdef CONFIG_HOTPLUG
277 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
280 static void __init pcibios_claim_of_setup(void)
284 list_for_each_entry(b, &pci_root_buses, node)
285 pcibios_claim_one_bus(b);
289 #ifdef CONFIG_PPC_MULTIPLATFORM
290 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
295 prop = (u32 *) get_property(np, name, &len);
296 if (prop && len >= 4)
301 static unsigned int pci_parse_of_flags(u32 addr0)
303 unsigned int flags = 0;
305 if (addr0 & 0x02000000) {
306 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
307 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
308 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
309 if (addr0 & 0x40000000)
310 flags |= IORESOURCE_PREFETCH
311 | PCI_BASE_ADDRESS_MEM_PREFETCH;
312 } else if (addr0 & 0x01000000)
313 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
317 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
319 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
323 struct resource *res;
327 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
330 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
331 for (; proplen >= 20; proplen -= 20, addrs += 5) {
332 flags = pci_parse_of_flags(addrs[0]);
335 base = GET_64BIT(addrs, 1);
336 size = GET_64BIT(addrs, 3);
340 DBG(" base: %llx, size: %llx, i: %x\n",
341 (unsigned long long)base, (unsigned long long)size, i);
343 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
344 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
345 } else if (i == dev->rom_base_reg) {
346 res = &dev->resource[PCI_ROM_RESOURCE];
347 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
349 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
353 res->end = base + size - 1;
355 res->name = pci_name(dev);
356 fixup_resource(res, dev);
360 struct pci_dev *of_create_pci_dev(struct device_node *node,
361 struct pci_bus *bus, int devfn)
366 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
369 type = get_property(node, "device_type", NULL);
373 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
375 memset(dev, 0, sizeof(struct pci_dev));
378 dev->dev.parent = bus->bridge;
379 dev->dev.bus = &pci_bus_type;
381 dev->multifunction = 0; /* maybe a lie? */
383 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
384 dev->device = get_int_prop(node, "device-id", 0xffff);
385 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
386 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
388 dev->cfg_size = pci_cfg_space_size(dev);
390 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
391 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
392 dev->class = get_int_prop(node, "class-code", 0);
394 DBG(" class: 0x%x\n", dev->class);
396 dev->current_state = 4; /* unknown power state */
398 if (!strcmp(type, "pci")) {
399 /* a PCI-PCI bridge */
400 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
401 dev->rom_base_reg = PCI_ROM_ADDRESS1;
402 } else if (!strcmp(type, "cardbus")) {
403 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
405 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
406 dev->rom_base_reg = PCI_ROM_ADDRESS;
408 if (node->n_intrs > 0) {
409 dev->irq = node->intrs[0].line;
410 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
415 pci_parse_of_addrs(node, dev);
417 DBG(" adding to system ...\n");
419 pci_device_add(dev, bus);
421 /* XXX pci_scan_msi_device(dev); */
425 EXPORT_SYMBOL(of_create_pci_dev);
427 void __devinit of_scan_bus(struct device_node *node,
430 struct device_node *child = NULL;
435 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
437 while ((child = of_get_next_child(node, child)) != NULL) {
438 DBG(" * %s\n", child->full_name);
439 reg = (u32 *) get_property(child, "reg", ®len);
440 if (reg == NULL || reglen < 20)
442 devfn = (reg[0] >> 8) & 0xff;
444 /* create a new pci_dev for this device */
445 dev = of_create_pci_dev(child, bus, devfn);
448 DBG("dev header type: %x\n", dev->hdr_type);
450 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
451 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
452 of_scan_pci_bridge(child, dev);
457 EXPORT_SYMBOL(of_scan_bus);
459 void __devinit of_scan_pci_bridge(struct device_node *node,
463 u32 *busrange, *ranges;
465 struct resource *res;
469 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
471 /* parse bus-range property */
472 busrange = (u32 *) get_property(node, "bus-range", &len);
473 if (busrange == NULL || len != 8) {
474 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
478 ranges = (u32 *) get_property(node, "ranges", &len);
479 if (ranges == NULL) {
480 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
485 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
487 printk(KERN_ERR "Failed to create pci bus for %s\n",
492 bus->primary = dev->bus->number;
493 bus->subordinate = busrange[1];
497 /* parse ranges property */
498 /* PCI #address-cells == 3 and #size-cells == 2 always */
499 res = &dev->resource[PCI_BRIDGE_RESOURCES];
500 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
502 bus->resource[i] = res;
506 for (; len >= 32; len -= 32, ranges += 8) {
507 flags = pci_parse_of_flags(ranges[0]);
508 size = GET_64BIT(ranges, 6);
509 if (flags == 0 || size == 0)
511 if (flags & IORESOURCE_IO) {
512 res = bus->resource[0];
514 printk(KERN_ERR "PCI: ignoring extra I/O range"
515 " for bridge %s\n", node->full_name);
519 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
520 printk(KERN_ERR "PCI: too many memory ranges"
521 " for bridge %s\n", node->full_name);
524 res = bus->resource[i];
527 res->start = GET_64BIT(ranges, 1);
528 res->end = res->start + size - 1;
530 fixup_resource(res, dev);
532 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
534 DBG(" bus name: %s\n", bus->name);
536 mode = PCI_PROBE_NORMAL;
537 if (ppc_md.pci_probe_mode)
538 mode = ppc_md.pci_probe_mode(bus);
539 DBG(" probe mode: %d\n", mode);
541 if (mode == PCI_PROBE_DEVTREE)
542 of_scan_bus(node, bus);
543 else if (mode == PCI_PROBE_NORMAL)
544 pci_scan_child_bus(bus);
546 EXPORT_SYMBOL(of_scan_pci_bridge);
547 #endif /* CONFIG_PPC_MULTIPLATFORM */
549 void __devinit scan_phb(struct pci_controller *hose)
552 struct device_node *node = hose->arch_data;
554 struct resource *res;
556 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
558 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
560 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
561 hose->global_number);
564 bus->secondary = hose->first_busno;
567 bus->resource[0] = res = &hose->io_resource;
568 if (res->flags && request_resource(&ioport_resource, res))
569 printk(KERN_ERR "Failed to request PCI IO region "
570 "on PCI domain %04x\n", hose->global_number);
572 for (i = 0; i < 3; ++i) {
573 res = &hose->mem_resources[i];
574 bus->resource[i+1] = res;
575 if (res->flags && request_resource(&iomem_resource, res))
576 printk(KERN_ERR "Failed to request PCI memory region "
577 "on PCI domain %04x\n", hose->global_number);
580 mode = PCI_PROBE_NORMAL;
581 #ifdef CONFIG_PPC_MULTIPLATFORM
582 if (node && ppc_md.pci_probe_mode)
583 mode = ppc_md.pci_probe_mode(bus);
584 DBG(" probe mode: %d\n", mode);
585 if (mode == PCI_PROBE_DEVTREE) {
586 bus->subordinate = hose->last_busno;
587 of_scan_bus(node, bus);
589 #endif /* CONFIG_PPC_MULTIPLATFORM */
590 if (mode == PCI_PROBE_NORMAL)
591 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
592 pci_bus_add_devices(bus);
595 static int __init pcibios_init(void)
597 struct pci_controller *hose, *tmp;
599 /* For now, override phys_mem_access_prot. If we need it,
600 * later, we may move that initialization to each ppc_md
602 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
604 #ifdef CONFIG_PPC_ISERIES
605 iSeries_pcibios_init();
608 printk("PCI: Probing PCI hardware\n");
610 /* Scan all of the recorded PCI controllers. */
611 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
614 #ifndef CONFIG_PPC_ISERIES
616 pcibios_claim_of_setup();
618 /* FIXME: `else' will be removed when
619 pci_assign_unassigned_resources() is able to work
620 correctly with [partially] allocated PCI tree. */
621 pci_assign_unassigned_resources();
622 #endif /* !CONFIG_PPC_ISERIES */
624 /* Call machine dependent final fixup */
625 if (ppc_md.pcibios_fixup)
626 ppc_md.pcibios_fixup();
628 /* Cache the location of the ISA bridge (if we have one) */
629 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
630 if (ppc64_isabridge_dev != NULL)
631 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
633 #ifdef CONFIG_PPC_MULTIPLATFORM
634 /* map in PCI I/O space */
638 printk("PCI: Probing PCI hardware done\n");
643 subsys_initcall(pcibios_init);
645 char __init *pcibios_setup(char *str)
650 int pcibios_enable_device(struct pci_dev *dev, int mask)
655 pci_read_config_word(dev, PCI_COMMAND, &cmd);
658 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
659 struct resource *res = &dev->resource[i];
661 /* Only set up the requested stuff */
662 if (!(mask & (1<<i)))
665 if (res->flags & IORESOURCE_IO)
666 cmd |= PCI_COMMAND_IO;
667 if (res->flags & IORESOURCE_MEM)
668 cmd |= PCI_COMMAND_MEMORY;
672 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
674 /* Enable the appropriate bits in the PCI command register. */
675 pci_write_config_word(dev, PCI_COMMAND, cmd);
681 * Return the domain number for this bus.
683 int pci_domain_nr(struct pci_bus *bus)
685 #ifdef CONFIG_PPC_ISERIES
688 struct pci_controller *hose = pci_bus_to_host(bus);
690 return hose->global_number;
694 EXPORT_SYMBOL(pci_domain_nr);
696 /* Decide whether to display the domain number in /proc */
697 int pci_proc_domain(struct pci_bus *bus)
699 #ifdef CONFIG_PPC_ISERIES
702 struct pci_controller *hose = pci_bus_to_host(bus);
708 * Platform support for /proc/bus/pci/X/Y mmap()s,
709 * modelled on the sparc64 implementation by Dave Miller.
714 * Adjust vm_pgoff of VMA such that it is the physical page offset
715 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
717 * Basically, the user finds the base address for his device which he wishes
718 * to mmap. They read the 32-bit value from the config space base register,
719 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
720 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
722 * Returns negative error code on failure, zero on success.
724 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
725 unsigned long *offset,
726 enum pci_mmap_state mmap_state)
728 struct pci_controller *hose = pci_bus_to_host(dev->bus);
729 unsigned long io_offset = 0;
733 return NULL; /* should never happen */
735 /* If memory, add on the PCI bridge address offset */
736 if (mmap_state == pci_mmap_mem) {
737 *offset += hose->pci_mem_offset;
738 res_bit = IORESOURCE_MEM;
740 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
741 *offset += io_offset;
742 res_bit = IORESOURCE_IO;
746 * Check that the offset requested corresponds to one of the
747 * resources of the device.
749 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
750 struct resource *rp = &dev->resource[i];
751 int flags = rp->flags;
753 /* treat ROM as memory (should be already) */
754 if (i == PCI_ROM_RESOURCE)
755 flags |= IORESOURCE_MEM;
757 /* Active and same type? */
758 if ((flags & res_bit) == 0)
761 /* In the range of this resource? */
762 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
765 /* found it! construct the final physical address */
766 if (mmap_state == pci_mmap_io)
767 *offset += hose->io_base_phys - io_offset;
775 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
778 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
780 enum pci_mmap_state mmap_state,
783 unsigned long prot = pgprot_val(protection);
785 /* Write combine is always 0 on non-memory space mappings. On
786 * memory space, if the user didn't pass 1, we check for a
787 * "prefetchable" resource. This is a bit hackish, but we use
788 * this to workaround the inability of /sysfs to provide a write
791 if (mmap_state != pci_mmap_mem)
793 else if (write_combine == 0) {
794 if (rp->flags & IORESOURCE_PREFETCH)
798 /* XXX would be nice to have a way to ask for write-through */
799 prot |= _PAGE_NO_CACHE;
801 prot &= ~_PAGE_GUARDED;
803 prot |= _PAGE_GUARDED;
805 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
808 return __pgprot(prot);
812 * This one is used by /dev/mem and fbdev who have no clue about the
813 * PCI device, it tries to find the PCI device first and calls the
816 pgprot_t pci_phys_mem_access_prot(struct file *file,
821 struct pci_dev *pdev = NULL;
822 struct resource *found = NULL;
823 unsigned long prot = pgprot_val(protection);
824 unsigned long offset = pfn << PAGE_SHIFT;
827 if (page_is_ram(pfn))
828 return __pgprot(prot);
830 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
832 for_each_pci_dev(pdev) {
833 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
834 struct resource *rp = &pdev->resource[i];
835 int flags = rp->flags;
837 /* Active and same type? */
838 if ((flags & IORESOURCE_MEM) == 0)
840 /* In the range of this resource? */
841 if (offset < (rp->start & PAGE_MASK) ||
851 if (found->flags & IORESOURCE_PREFETCH)
852 prot &= ~_PAGE_GUARDED;
856 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
858 return __pgprot(prot);
863 * Perform the actual remap of the pages for a PCI device mapping, as
864 * appropriate for this architecture. The region in the process to map
865 * is described by vm_start and vm_end members of VMA, the base physical
866 * address is found in vm_pgoff.
867 * The pci device structure is provided so that architectures may make mapping
868 * decisions on a per-device or per-bus basis.
870 * Returns a negative error code on failure, zero on success.
872 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
873 enum pci_mmap_state mmap_state, int write_combine)
875 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
879 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
883 vma->vm_pgoff = offset >> PAGE_SHIFT;
884 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
885 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
887 mmap_state, write_combine);
889 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
890 vma->vm_end - vma->vm_start, vma->vm_page_prot);
895 #ifdef CONFIG_PPC_MULTIPLATFORM
896 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
898 struct pci_dev *pdev;
899 struct device_node *np;
901 pdev = to_pci_dev (dev);
902 np = pci_device_to_OF_node(pdev);
903 if (np == NULL || np->full_name == NULL)
905 return sprintf(buf, "%s", np->full_name);
907 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
908 #endif /* CONFIG_PPC_MULTIPLATFORM */
910 void pcibios_add_platform_entries(struct pci_dev *pdev)
912 #ifdef CONFIG_PPC_MULTIPLATFORM
913 device_create_file(&pdev->dev, &dev_attr_devspec);
914 #endif /* CONFIG_PPC_MULTIPLATFORM */
917 #ifdef CONFIG_PPC_MULTIPLATFORM
919 #define ISA_SPACE_MASK 0x1
920 #define ISA_SPACE_IO 0x1
922 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
923 unsigned long phb_io_base_phys,
924 void __iomem * phb_io_base_virt)
926 /* Remove these asap */
940 struct isa_address isa_addr;
941 struct pci_address pci_addr;
945 struct isa_range *range;
946 unsigned long pci_addr;
947 unsigned int isa_addr;
951 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
952 if (range == NULL || (rlen < sizeof(struct isa_range))) {
953 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
955 __ioremap_explicit(phb_io_base_phys,
956 (unsigned long)phb_io_base_virt,
957 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
961 /* From "ISA Binding to 1275"
962 * The ranges property is laid out as an array of elements,
963 * each of which comprises:
964 * cells 0 - 1: an ISA address
965 * cells 2 - 4: a PCI address
966 * (size depending on dev->n_addr_cells)
967 * cell 5: the size of the range
969 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
970 isa_addr = range->isa_addr.a_lo;
971 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
972 range->pci_addr.a_lo;
974 /* Assume these are both zero */
975 if ((pci_addr != 0) || (isa_addr != 0)) {
976 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
981 size = PAGE_ALIGN(range->size);
983 __ioremap_explicit(phb_io_base_phys,
984 (unsigned long) phb_io_base_virt,
985 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
989 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
990 struct device_node *dev, int prim)
992 unsigned int *ranges, pci_space;
996 struct resource *res;
997 int np, na = prom_n_addr_cells(dev);
998 unsigned long pci_addr, cpu_phys_addr;
1002 /* From "PCI Binding to 1275"
1003 * The ranges property is laid out as an array of elements,
1004 * each of which comprises:
1005 * cells 0 - 2: a PCI address
1006 * cells 3 or 3+4: a CPU physical address
1007 * (size depending on dev->n_addr_cells)
1008 * cells 4+5 or 5+6: the size of the range
1010 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
1013 hose->io_base_phys = 0;
1014 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
1016 pci_space = ranges[0];
1017 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1019 cpu_phys_addr = ranges[3];
1021 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1023 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
1028 /* Now consume following elements while they are contiguous */
1029 while (rlen >= np * sizeof(unsigned int)) {
1030 unsigned long addr, phys;
1032 if (ranges[0] != pci_space)
1034 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1037 phys = (phys << 32) | ranges[4];
1038 if (addr != pci_addr + size ||
1039 phys != cpu_phys_addr + size)
1042 size += ((unsigned long)ranges[na+3] << 32)
1045 rlen -= np * sizeof(unsigned int);
1048 switch ((pci_space >> 24) & 0x3) {
1049 case 1: /* I/O space */
1050 hose->io_base_phys = cpu_phys_addr;
1051 hose->pci_io_size = size;
1053 res = &hose->io_resource;
1054 res->flags = IORESOURCE_IO;
1055 res->start = pci_addr;
1056 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1057 res->start, res->start + size - 1);
1059 case 2: /* memory space */
1061 while (memno < 3 && hose->mem_resources[memno].flags)
1065 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1067 res = &hose->mem_resources[memno];
1068 res->flags = IORESOURCE_MEM;
1069 res->start = cpu_phys_addr;
1070 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1071 res->start, res->start + size - 1);
1076 res->name = dev->full_name;
1077 res->end = res->start + size - 1;
1079 res->sibling = NULL;
1085 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1087 unsigned long size = hose->pci_io_size;
1088 unsigned long io_virt_offset;
1089 struct resource *res;
1090 struct device_node *isa_dn;
1092 hose->io_base_virt = reserve_phb_iospace(size);
1093 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1094 hose->global_number, hose->io_base_phys,
1095 (unsigned long) hose->io_base_virt);
1098 pci_io_base = (unsigned long)hose->io_base_virt;
1099 isa_dn = of_find_node_by_type(NULL, "isa");
1101 isa_io_base = pci_io_base;
1102 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1103 hose->io_base_virt);
1104 of_node_put(isa_dn);
1110 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1111 res = &hose->io_resource;
1112 res->start += io_virt_offset;
1113 res->end += io_virt_offset;
1116 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1119 unsigned long size = hose->pci_io_size;
1120 unsigned long io_virt_offset;
1121 struct resource *res;
1123 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1124 _PAGE_NO_CACHE | _PAGE_GUARDED);
1125 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1126 hose->global_number, hose->io_base_phys,
1127 (unsigned long) hose->io_base_virt);
1130 pci_io_base = (unsigned long)hose->io_base_virt;
1132 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1133 res = &hose->io_resource;
1134 res->start += io_virt_offset;
1135 res->end += io_virt_offset;
1139 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1140 unsigned long *start_virt, unsigned long *size)
1142 struct pci_controller *hose = pci_bus_to_host(bus);
1143 struct pci_bus_region region;
1144 struct resource *res;
1147 res = bus->resource[0];
1148 pcibios_resource_to_bus(bus->self, ®ion, res);
1149 *start_phys = hose->io_base_phys + region.start;
1150 *start_virt = (unsigned long) hose->io_base_virt +
1152 if (region.end > region.start)
1153 *size = region.end - region.start + 1;
1155 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1156 __FUNCTION__, region.start, region.end);
1162 res = &hose->io_resource;
1163 *start_phys = hose->io_base_phys;
1164 *start_virt = (unsigned long) hose->io_base_virt;
1165 if (res->end > res->start)
1166 *size = res->end - res->start + 1;
1168 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1169 __FUNCTION__, res->start, res->end);
1177 int unmap_bus_range(struct pci_bus *bus)
1179 unsigned long start_phys;
1180 unsigned long start_virt;
1184 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1188 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1190 if (iounmap_explicit((void __iomem *) start_virt, size))
1195 EXPORT_SYMBOL(unmap_bus_range);
1197 int remap_bus_range(struct pci_bus *bus)
1199 unsigned long start_phys;
1200 unsigned long start_virt;
1204 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1209 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1211 if (start_phys == 0)
1213 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1214 if (__ioremap_explicit(start_phys, start_virt, size,
1215 _PAGE_NO_CACHE | _PAGE_GUARDED))
1220 EXPORT_SYMBOL(remap_bus_range);
1222 static void phbs_remap_io(void)
1224 struct pci_controller *hose, *tmp;
1226 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1227 remap_bus_range(hose->bus);
1230 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1232 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1233 unsigned long start, end, mask, offset;
1235 if (res->flags & IORESOURCE_IO) {
1236 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1238 start = res->start += offset;
1239 end = res->end += offset;
1241 /* Need to allow IO access to pages that are in the
1243 if (start < MAX_ISA_PORT) {
1244 if (end > MAX_ISA_PORT)
1247 start >>= PAGE_SHIFT;
1250 /* get the range of pages for the map */
1251 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1252 io_page_mask |= mask;
1254 } else if (res->flags & IORESOURCE_MEM) {
1255 res->start += hose->pci_mem_offset;
1256 res->end += hose->pci_mem_offset;
1260 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1261 struct pci_bus *bus)
1263 /* Update device resources. */
1266 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1267 if (dev->resource[i].flags)
1268 fixup_resource(&dev->resource[i], dev);
1270 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1273 static void __devinit do_bus_setup(struct pci_bus *bus)
1275 struct pci_dev *dev;
1277 ppc_md.iommu_bus_setup(bus);
1279 list_for_each_entry(dev, &bus->devices, bus_list)
1280 ppc_md.iommu_dev_setup(dev);
1282 if (ppc_md.irq_bus_setup)
1283 ppc_md.irq_bus_setup(bus);
1286 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1288 struct pci_dev *dev = bus->self;
1290 if (dev && pci_probe_only &&
1291 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1292 /* This is a subordinate bridge */
1294 pci_read_bridge_bases(bus);
1295 pcibios_fixup_device_resources(dev, bus);
1300 if (!pci_probe_only)
1303 list_for_each_entry(dev, &bus->devices, bus_list)
1304 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1305 pcibios_fixup_device_resources(dev, bus);
1307 EXPORT_SYMBOL(pcibios_fixup_bus);
1310 * Reads the interrupt pin to determine if interrupt is use by card.
1311 * If the interrupt is used, then gets the interrupt line from the
1312 * openfirmware and sets it in the pci_dev and pci_config line.
1314 int pci_read_irq_line(struct pci_dev *pci_dev)
1317 struct device_node *node;
1319 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1323 node = pci_device_to_OF_node(pci_dev);
1327 if (node->n_intrs == 0)
1330 pci_dev->irq = node->intrs[0].line;
1332 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1336 EXPORT_SYMBOL(pci_read_irq_line);
1338 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1339 const struct resource *rsrc,
1340 u64 *start, u64 *end)
1342 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1343 unsigned long offset = 0;
1348 if (rsrc->flags & IORESOURCE_IO)
1349 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1352 *start = rsrc->start + offset;
1353 *end = rsrc->end + offset;
1356 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1361 struct pci_controller *hose, *tmp;
1362 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1363 if (hose->arch_data == node)
1365 node = node->parent;
1370 #endif /* CONFIG_PPC_MULTIPLATFORM */
1372 unsigned long pci_address_to_pio(phys_addr_t address)
1374 struct pci_controller *hose, *tmp;
1376 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1377 if (address >= hose->io_base_phys &&
1378 address < (hose->io_base_phys + hose->pci_io_size)) {
1379 unsigned long base =
1380 (unsigned long)hose->io_base_virt - pci_io_base;
1381 return base + (address - hose->io_base_phys);
1384 return (unsigned int)-1;
1386 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1389 #define IOBASE_BRIDGE_NUMBER 0
1390 #define IOBASE_MEMORY 1
1392 #define IOBASE_ISA_IO 3
1393 #define IOBASE_ISA_MEM 4
1395 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1396 unsigned long in_devfn)
1398 struct pci_controller* hose;
1399 struct list_head *ln;
1400 struct pci_bus *bus = NULL;
1401 struct device_node *hose_node;
1403 /* Argh ! Please forgive me for that hack, but that's the
1404 * simplest way to get existing XFree to not lockup on some
1405 * G5 machines... So when something asks for bus 0 io base
1406 * (bus 0 is HT root), we return the AGP one instead.
1408 if (machine_is_compatible("MacRISC4"))
1412 /* That syscall isn't quite compatible with PCI domains, but it's
1413 * used on pre-domains setup. We return the first match
1416 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1417 bus = pci_bus_b(ln);
1418 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1422 if (bus == NULL || bus->sysdata == NULL)
1425 hose_node = (struct device_node *)bus->sysdata;
1426 hose = PCI_DN(hose_node)->phb;
1429 case IOBASE_BRIDGE_NUMBER:
1430 return (long)hose->first_busno;
1432 return (long)hose->pci_mem_offset;
1434 return (long)hose->io_base_phys;
1436 return (long)isa_io_base;
1437 case IOBASE_ISA_MEM: