2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
35 #include <asm/processor.h>
36 #include <asm/pgtable.h>
38 #include <asm/mmu_context.h>
40 #include <asm/types.h>
41 #include <asm/system.h>
42 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
45 #include <asm/abs_addr.h>
46 #include <asm/tlbflush.h>
50 #include <asm/cacheflush.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #define DBG_LOW(fmt...)
72 * Note: pte --> Linux PTE
73 * HPTE --> PowerPC Hashed Page Table Entry
76 * htab_initialize is called with the MMU off (of course), but
77 * the kernel has been copied down to zero so it can directly
78 * reference global data. At this point it is very difficult
79 * to print debug info.
84 extern unsigned long dart_tablebase;
85 #endif /* CONFIG_U3_DART */
87 static unsigned long _SDR1;
88 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
90 struct hash_pte *htab_address;
91 unsigned long htab_size_bytes;
92 unsigned long htab_hash_mask;
93 int mmu_linear_psize = MMU_PAGE_4K;
94 int mmu_virtual_psize = MMU_PAGE_4K;
95 int mmu_vmalloc_psize = MMU_PAGE_4K;
96 int mmu_io_psize = MMU_PAGE_4K;
97 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
98 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
99 u16 mmu_slb_size = 64;
100 #ifdef CONFIG_HUGETLB_PAGE
101 int mmu_huge_psize = MMU_PAGE_16M;
102 unsigned int HPAGE_SHIFT;
104 #ifdef CONFIG_PPC_64K_PAGES
105 int mmu_ci_restrictions;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 static u8 *linear_map_hash_slots;
109 static unsigned long linear_map_hash_count;
110 static DEFINE_SPINLOCK(linear_map_hash_lock);
111 #endif /* CONFIG_DEBUG_PAGEALLOC */
113 /* There are definitions of page sizes arrays to be used when none
114 * is provided by the firmware.
117 /* Pre-POWER4 CPUs (4k pages only)
119 struct mmu_psize_def mmu_psize_defaults_old[] = {
129 /* POWER4, GPUL, POWER5
131 * Support for 16Mb large pages
133 struct mmu_psize_def mmu_psize_defaults_gp[] = {
151 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
152 unsigned long pstart, unsigned long mode,
153 int psize, int ssize)
155 unsigned long vaddr, paddr;
156 unsigned int step, shift;
157 unsigned long tmp_mode;
160 shift = mmu_psize_defs[psize].shift;
163 for (vaddr = vstart, paddr = pstart; vaddr < vend;
164 vaddr += step, paddr += step) {
165 unsigned long hash, hpteg;
166 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
167 unsigned long va = hpt_va(vaddr, vsid, ssize);
171 /* Make non-kernel text non-executable */
172 if (!in_kernel_text(vaddr))
173 tmp_mode = mode | HPTE_R_N;
175 hash = hpt_hash(va, shift, ssize);
176 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
178 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
180 BUG_ON(!ppc_md.hpte_insert);
181 ret = ppc_md.hpte_insert(hpteg, va, paddr,
182 tmp_mode, HPTE_V_BOLTED, psize, ssize);
186 #ifdef CONFIG_DEBUG_PAGEALLOC
187 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
188 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
189 #endif /* CONFIG_DEBUG_PAGEALLOC */
191 return ret < 0 ? ret : 0;
194 static int __init htab_dt_scan_seg_sizes(unsigned long node,
195 const char *uname, int depth,
198 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
200 unsigned long size = 0;
202 /* We are scanning "cpu" nodes only */
203 if (type == NULL || strcmp(type, "cpu") != 0)
206 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
210 for (; size >= 4; size -= 4, ++prop) {
212 DBG("1T segment support detected\n");
213 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
217 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
221 static void __init htab_init_seg_sizes(void)
223 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
226 static int __init htab_dt_scan_page_sizes(unsigned long node,
227 const char *uname, int depth,
230 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
232 unsigned long size = 0;
234 /* We are scanning "cpu" nodes only */
235 if (type == NULL || strcmp(type, "cpu") != 0)
238 prop = (u32 *)of_get_flat_dt_prop(node,
239 "ibm,segment-page-sizes", &size);
241 DBG("Page sizes from device-tree:\n");
243 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
245 unsigned int shift = prop[0];
246 unsigned int slbenc = prop[1];
247 unsigned int lpnum = prop[2];
248 unsigned int lpenc = 0;
249 struct mmu_psize_def *def;
252 size -= 3; prop += 3;
253 while(size > 0 && lpnum) {
254 if (prop[0] == shift)
256 prop += 2; size -= 2;
271 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
279 def = &mmu_psize_defs[idx];
284 def->avpnm = (1 << (shift - 23)) - 1;
287 /* We don't know for sure what's up with tlbiel, so
288 * for now we only set it for 4K and 64K pages
290 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
295 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
296 "tlbiel=%d, penc=%d\n",
297 idx, shift, def->sllp, def->avpnm, def->tlbiel,
305 static void __init htab_init_page_sizes(void)
309 /* Default to 4K pages only */
310 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
311 sizeof(mmu_psize_defaults_old));
314 * Try to find the available page sizes in the device-tree
316 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
317 if (rc != 0) /* Found */
321 * Not in the device-tree, let's fallback on known size
322 * list for 16M capable GP & GR
324 if (cpu_has_feature(CPU_FTR_16M_PAGE))
325 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
326 sizeof(mmu_psize_defaults_gp));
328 #ifndef CONFIG_DEBUG_PAGEALLOC
330 * Pick a size for the linear mapping. Currently, we only support
331 * 16M, 1M and 4K which is the default
333 if (mmu_psize_defs[MMU_PAGE_16M].shift)
334 mmu_linear_psize = MMU_PAGE_16M;
335 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
336 mmu_linear_psize = MMU_PAGE_1M;
337 #endif /* CONFIG_DEBUG_PAGEALLOC */
339 #ifdef CONFIG_PPC_64K_PAGES
341 * Pick a size for the ordinary pages. Default is 4K, we support
342 * 64K for user mappings and vmalloc if supported by the processor.
343 * We only use 64k for ioremap if the processor
344 * (and firmware) support cache-inhibited large pages.
345 * If not, we use 4k and set mmu_ci_restrictions so that
346 * hash_page knows to switch processes that use cache-inhibited
347 * mappings to 4k pages.
349 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
350 mmu_virtual_psize = MMU_PAGE_64K;
351 mmu_vmalloc_psize = MMU_PAGE_64K;
352 if (mmu_linear_psize == MMU_PAGE_4K)
353 mmu_linear_psize = MMU_PAGE_64K;
354 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
355 mmu_io_psize = MMU_PAGE_64K;
357 mmu_ci_restrictions = 1;
359 #endif /* CONFIG_PPC_64K_PAGES */
361 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
362 "virtual = %d, io = %d\n",
363 mmu_psize_defs[mmu_linear_psize].shift,
364 mmu_psize_defs[mmu_virtual_psize].shift,
365 mmu_psize_defs[mmu_io_psize].shift);
367 #ifdef CONFIG_HUGETLB_PAGE
368 /* Init large page size. Currently, we pick 16M or 1M depending
369 * on what is available
371 if (mmu_psize_defs[MMU_PAGE_16M].shift)
372 mmu_huge_psize = MMU_PAGE_16M;
373 /* With 4k/4level pagetables, we can't (for now) cope with a
374 * huge page size < PMD_SIZE */
375 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
376 mmu_huge_psize = MMU_PAGE_1M;
378 /* Calculate HPAGE_SHIFT and sanity check it */
379 if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT &&
380 mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT)
381 HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift;
383 HPAGE_SHIFT = 0; /* No huge pages dude ! */
384 #endif /* CONFIG_HUGETLB_PAGE */
387 static int __init htab_dt_scan_pftsize(unsigned long node,
388 const char *uname, int depth,
391 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
394 /* We are scanning "cpu" nodes only */
395 if (type == NULL || strcmp(type, "cpu") != 0)
398 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
400 /* pft_size[0] is the NUMA CEC cookie */
401 ppc64_pft_size = prop[1];
407 static unsigned long __init htab_get_table_size(void)
409 unsigned long mem_size, rnd_mem_size, pteg_count;
411 /* If hash size isn't already provided by the platform, we try to
412 * retrieve it from the device-tree. If it's not there neither, we
413 * calculate it now based on the total RAM size
415 if (ppc64_pft_size == 0)
416 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
418 return 1UL << ppc64_pft_size;
420 /* round mem_size up to next power of 2 */
421 mem_size = lmb_phys_mem_size();
422 rnd_mem_size = 1UL << __ilog2(mem_size);
423 if (rnd_mem_size < mem_size)
427 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
429 return pteg_count << 7;
432 #ifdef CONFIG_MEMORY_HOTPLUG
433 void create_section_mapping(unsigned long start, unsigned long end)
435 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
436 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
437 mmu_linear_psize, mmu_kernel_ssize));
439 #endif /* CONFIG_MEMORY_HOTPLUG */
441 static inline void make_bl(unsigned int *insn_addr, void *func)
443 unsigned long funcp = *((unsigned long *)func);
444 int offset = funcp - (unsigned long)insn_addr;
446 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
447 flush_icache_range((unsigned long)insn_addr, 4+
448 (unsigned long)insn_addr);
451 static void __init htab_finish_init(void)
453 extern unsigned int *htab_call_hpte_insert1;
454 extern unsigned int *htab_call_hpte_insert2;
455 extern unsigned int *htab_call_hpte_remove;
456 extern unsigned int *htab_call_hpte_updatepp;
458 #ifdef CONFIG_PPC_HAS_HASH_64K
459 extern unsigned int *ht64_call_hpte_insert1;
460 extern unsigned int *ht64_call_hpte_insert2;
461 extern unsigned int *ht64_call_hpte_remove;
462 extern unsigned int *ht64_call_hpte_updatepp;
464 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
465 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
466 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
467 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
468 #endif /* CONFIG_PPC_HAS_HASH_64K */
470 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
471 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
472 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
473 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
476 void __init htab_initialize(void)
479 unsigned long pteg_count;
480 unsigned long mode_rw;
481 unsigned long base = 0, size = 0;
484 extern unsigned long tce_alloc_start, tce_alloc_end;
486 DBG(" -> htab_initialize()\n");
488 /* Initialize segment sizes */
489 htab_init_seg_sizes();
491 /* Initialize page sizes */
492 htab_init_page_sizes();
494 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
495 mmu_kernel_ssize = MMU_SEGSIZE_1T;
496 mmu_highuser_ssize = MMU_SEGSIZE_1T;
497 printk(KERN_INFO "Using 1TB segments\n");
501 * Calculate the required size of the htab. We want the number of
502 * PTEGs to equal one half the number of real pages.
504 htab_size_bytes = htab_get_table_size();
505 pteg_count = htab_size_bytes >> 7;
507 htab_hash_mask = pteg_count - 1;
509 if (firmware_has_feature(FW_FEATURE_LPAR)) {
510 /* Using a hypervisor which owns the htab */
514 /* Find storage for the HPT. Must be contiguous in
515 * the absolute address space.
517 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
519 DBG("Hash table allocated at %lx, size: %lx\n", table,
522 htab_address = abs_to_virt(table);
524 /* htab absolute addr + encoded htabsize */
525 _SDR1 = table + __ilog2(pteg_count) - 11;
527 /* Initialize the HPT with no entries */
528 memset((void *)table, 0, htab_size_bytes);
531 mtspr(SPRN_SDR1, _SDR1);
534 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
536 #ifdef CONFIG_DEBUG_PAGEALLOC
537 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
538 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
540 memset(linear_map_hash_slots, 0, linear_map_hash_count);
541 #endif /* CONFIG_DEBUG_PAGEALLOC */
543 /* On U3 based machines, we need to reserve the DART area and
544 * _NOT_ map it to avoid cache paradoxes as it's remapped non
548 /* create bolted the linear mapping in the hash table */
549 for (i=0; i < lmb.memory.cnt; i++) {
550 base = (unsigned long)__va(lmb.memory.region[i].base);
551 size = lmb.memory.region[i].size;
553 DBG("creating mapping for region: %lx : %lx\n", base, size);
555 #ifdef CONFIG_U3_DART
556 /* Do not map the DART space. Fortunately, it will be aligned
557 * in such a way that it will not cross two lmb regions and
558 * will fit within a single 16Mb page.
559 * The DART space is assumed to be a full 16Mb region even if
560 * we only use 2Mb of that space. We will use more of it later
561 * for AGP GART. We have to use a full 16Mb large page.
563 DBG("DART base: %lx\n", dart_tablebase);
565 if (dart_tablebase != 0 && dart_tablebase >= base
566 && dart_tablebase < (base + size)) {
567 unsigned long dart_table_end = dart_tablebase + 16 * MB;
568 if (base != dart_tablebase)
569 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
573 if ((base + size) > dart_table_end)
574 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
576 __pa(dart_table_end),
582 #endif /* CONFIG_U3_DART */
583 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
584 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
588 * If we have a memory_limit and we've allocated TCEs then we need to
589 * explicitly map the TCE area at the top of RAM. We also cope with the
590 * case that the TCEs start below memory_limit.
591 * tce_alloc_start/end are 16MB aligned so the mapping should work
592 * for either 4K or 16MB pages.
594 if (tce_alloc_start) {
595 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
596 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
598 if (base + size >= tce_alloc_start)
599 tce_alloc_start = base + size + 1;
601 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
602 __pa(tce_alloc_start), mode_rw,
603 mmu_linear_psize, mmu_kernel_ssize));
608 DBG(" <- htab_initialize()\n");
613 void htab_initialize_secondary(void)
615 if (!firmware_has_feature(FW_FEATURE_LPAR))
616 mtspr(SPRN_SDR1, _SDR1);
620 * Called by asm hashtable.S for doing lazy icache flush
622 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
626 if (!pfn_valid(pte_pfn(pte)))
629 page = pte_page(pte);
632 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
634 __flush_dcache_icache(page_address(page));
635 set_bit(PG_arch_1, &page->flags);
643 * Demote a segment to using 4k pages.
644 * For now this makes the whole process use 4k pages.
646 #ifdef CONFIG_PPC_64K_PAGES
647 static void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
649 if (mm->context.user_psize == MMU_PAGE_4K)
651 slice_set_user_psize(mm, MMU_PAGE_4K);
652 #ifdef CONFIG_SPU_BASE
653 spu_flush_all_slbs(mm);
656 #endif /* CONFIG_PPC_64K_PAGES */
660 * 1 - normal page fault
661 * -1 - critical hash insertion error
663 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
667 struct mm_struct *mm;
670 int rc, user_region = 0, local = 0;
673 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
676 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
677 DBG_LOW(" out of pgtable range !\n");
681 /* Get region & vsid */
682 switch (REGION_ID(ea)) {
687 DBG_LOW(" user region with no mm !\n");
690 #ifdef CONFIG_PPC_MM_SLICES
691 psize = get_slice_psize(mm, ea);
693 psize = mm->context.user_psize;
695 ssize = user_segment_size(ea);
696 vsid = get_vsid(mm->context.id, ea, ssize);
698 case VMALLOC_REGION_ID:
700 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
701 if (ea < VMALLOC_END)
702 psize = mmu_vmalloc_psize;
704 psize = mmu_io_psize;
705 ssize = mmu_kernel_ssize;
709 * Send the problem up to do_page_fault
713 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
720 /* Check CPU locality */
721 tmp = cpumask_of_cpu(smp_processor_id());
722 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
725 #ifdef CONFIG_HUGETLB_PAGE
726 /* Handle hugepage regions */
727 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
728 DBG_LOW(" -> huge page !\n");
729 return hash_huge_page(mm, access, ea, vsid, local, trap);
731 #endif /* CONFIG_HUGETLB_PAGE */
733 #ifndef CONFIG_PPC_64K_PAGES
734 /* If we use 4K pages and our psize is not 4K, then we are hitting
735 * a special driver mapping, we need to align the address before
738 if (psize != MMU_PAGE_4K)
739 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
740 #endif /* CONFIG_PPC_64K_PAGES */
742 /* Get PTE and page size from page tables */
743 ptep = find_linux_pte(pgdir, ea);
744 if (ptep == NULL || !pte_present(*ptep)) {
745 DBG_LOW(" no PTE !\n");
749 #ifndef CONFIG_PPC_64K_PAGES
750 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
752 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
753 pte_val(*(ptep + PTRS_PER_PTE)));
755 /* Pre-check access permissions (will be re-checked atomically
756 * in __hash_page_XX but this pre-check is a fast path
758 if (access & ~pte_val(*ptep)) {
759 DBG_LOW(" no access !\n");
763 /* Do actual hashing */
764 #ifdef CONFIG_PPC_64K_PAGES
765 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
766 if (pte_val(*ptep) & _PAGE_4K_PFN) {
767 demote_segment_4k(mm, ea);
771 /* If this PTE is non-cacheable and we have restrictions on
772 * using non cacheable large pages, then we switch to 4k
774 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
775 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
777 demote_segment_4k(mm, ea);
779 } else if (ea < VMALLOC_END) {
781 * some driver did a non-cacheable mapping
782 * in vmalloc space, so switch vmalloc
785 printk(KERN_ALERT "Reducing vmalloc segment "
786 "to 4kB pages because of "
787 "non-cacheable mapping\n");
788 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
789 #ifdef CONFIG_SPU_BASE
790 spu_flush_all_slbs(mm);
795 if (psize != get_paca()->context.user_psize) {
796 get_paca()->context = mm->context;
797 slb_flush_and_rebolt();
799 } else if (get_paca()->vmalloc_sllp !=
800 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
801 get_paca()->vmalloc_sllp =
802 mmu_psize_defs[mmu_vmalloc_psize].sllp;
803 slb_vmalloc_update();
805 #endif /* CONFIG_PPC_64K_PAGES */
807 #ifdef CONFIG_PPC_HAS_HASH_64K
808 if (psize == MMU_PAGE_64K)
809 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
811 #endif /* CONFIG_PPC_HAS_HASH_64K */
812 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
814 #ifndef CONFIG_PPC_64K_PAGES
815 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
817 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
818 pte_val(*(ptep + PTRS_PER_PTE)));
820 DBG_LOW(" -> rc=%d\n", rc);
823 EXPORT_SYMBOL_GPL(hash_page);
825 void hash_preload(struct mm_struct *mm, unsigned long ea,
826 unsigned long access, unsigned long trap)
836 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
838 #ifdef CONFIG_PPC_MM_SLICES
839 /* We only prefault standard pages for now */
840 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
844 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
845 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
847 /* Get Linux PTE if available */
851 ptep = find_linux_pte(pgdir, ea);
855 #ifdef CONFIG_PPC_64K_PAGES
856 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
857 * a 64K kernel), then we don't preload, hash_page() will take
858 * care of it once we actually try to access the page.
859 * That way we don't have to duplicate all of the logic for segment
860 * page size demotion here
862 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
864 #endif /* CONFIG_PPC_64K_PAGES */
867 ssize = user_segment_size(ea);
868 vsid = get_vsid(mm->context.id, ea, ssize);
870 /* Hash doesn't like irqs */
871 local_irq_save(flags);
873 /* Is that local to this CPU ? */
874 mask = cpumask_of_cpu(smp_processor_id());
875 if (cpus_equal(mm->cpu_vm_mask, mask))
879 #ifdef CONFIG_PPC_HAS_HASH_64K
880 if (mm->context.user_psize == MMU_PAGE_64K)
881 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
883 #endif /* CONFIG_PPC_HAS_HASH_64K */
884 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
886 local_irq_restore(flags);
889 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
890 * do not forget to update the assembly call site !
892 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
895 unsigned long hash, index, shift, hidx, slot;
897 DBG_LOW("flush_hash_page(va=%016x)\n", va);
898 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
899 hash = hpt_hash(va, shift, ssize);
900 hidx = __rpte_to_hidx(pte, index);
901 if (hidx & _PTEIDX_SECONDARY)
903 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
904 slot += hidx & _PTEIDX_GROUP_IX;
905 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
906 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
907 } pte_iterate_hashed_end();
910 void flush_hash_range(unsigned long number, int local)
912 if (ppc_md.flush_hash_range)
913 ppc_md.flush_hash_range(number, local);
916 struct ppc64_tlb_batch *batch =
917 &__get_cpu_var(ppc64_tlb_batch);
919 for (i = 0; i < number; i++)
920 flush_hash_page(batch->vaddr[i], batch->pte[i],
921 batch->psize, batch->ssize, local);
926 * low_hash_fault is called when we the low level hash code failed
927 * to instert a PTE due to an hypervisor error
929 void low_hash_fault(struct pt_regs *regs, unsigned long address)
931 if (user_mode(regs)) {
934 info.si_signo = SIGBUS;
936 info.si_code = BUS_ADRERR;
937 info.si_addr = (void __user *)address;
938 force_sig_info(SIGBUS, &info, current);
941 bad_page_fault(regs, address, SIGBUS);
944 #ifdef CONFIG_DEBUG_PAGEALLOC
945 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
947 unsigned long hash, hpteg;
948 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
949 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
950 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
951 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
954 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
955 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
957 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
959 mmu_linear_psize, mmu_kernel_ssize);
961 spin_lock(&linear_map_hash_lock);
962 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
963 linear_map_hash_slots[lmi] = ret | 0x80;
964 spin_unlock(&linear_map_hash_lock);
967 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
969 unsigned long hash, hidx, slot;
970 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
971 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
973 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
974 spin_lock(&linear_map_hash_lock);
975 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
976 hidx = linear_map_hash_slots[lmi] & 0x7f;
977 linear_map_hash_slots[lmi] = 0;
978 spin_unlock(&linear_map_hash_lock);
979 if (hidx & _PTEIDX_SECONDARY)
981 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
982 slot += hidx & _PTEIDX_GROUP_IX;
983 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
986 void kernel_map_pages(struct page *page, int numpages, int enable)
988 unsigned long flags, vaddr, lmi;
991 local_irq_save(flags);
992 for (i = 0; i < numpages; i++, page++) {
993 vaddr = (unsigned long)page_address(page);
994 lmi = __pa(vaddr) >> PAGE_SHIFT;
995 if (lmi >= linear_map_hash_count)
998 kernel_map_linear_page(vaddr, lmi);
1000 kernel_unmap_linear_page(vaddr, lmi);
1002 local_irq_restore(flags);
1004 #endif /* CONFIG_DEBUG_PAGEALLOC */