2 * MPC82xx_ads setup and early boot code plus other random bits.
4 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
5 * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright (c) 2006 MontaVista Software, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/kdev_t.h>
25 #include <linux/major.h>
26 #include <linux/console.h>
27 #include <linux/delay.h>
28 #include <linux/seq_file.h>
29 #include <linux/root_dev.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/fs_uart_pd.h>
35 #include <asm/system.h>
36 #include <asm/pgtable.h>
38 #include <asm/atomic.h>
41 #include <asm/machdep.h>
42 #include <asm/bootinfo.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/mpc8260.h>
46 #include <mm/mmu_decl.h>
50 #include <asm/i8259.h>
51 #include <linux/fs_enet_pd.h>
53 #include <sysdev/fsl_soc.h>
54 #include <../sysdev/cpm2_pic.h>
56 #include "pq2ads_pd.h"
59 static uint pci_clk_frq;
61 unsigned long *pci_int_stat_reg;
62 unsigned long *pci_int_mask_reg;
65 static unsigned long pci_int_base;
66 static struct irq_host *pci_pic_host;
67 static struct device_node *pci_pic_node;
70 static void __init mpc82xx_ads_pic_init(void)
72 struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
77 printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
80 if (of_address_to_resource(np, 0, &r)) {
81 printk(KERN_ERR "PIC init: invalid resource\n");
88 /* Initialize the default interrupt mapping priorities,
89 * in case the boot rom changed something on us.
91 cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
92 cpm_reg->im_intctl.ic_siprr = 0x05309770;
95 /* Initialize stuff for the 82xx CPLD IC and install demux */
100 static void init_fcc1_ioports(struct fs_platform_info *fpi)
104 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
105 struct device_node *np;
109 np = of_find_node_by_type(NULL, "memory");
111 printk(KERN_INFO "No memory node in device tree\n");
114 if (of_address_to_resource(np, 1, &r)) {
115 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
119 bcsr = ioremap(r.start + 4, sizeof(u32));
120 io = &immap->im_ioport;
123 clrbits32(bcsr, BCSR1_FETHIEN);
124 setbits32(bcsr, BCSR1_FETH_RST);
126 /* FCC1 pins are on port A/C. */
127 /* Configure port A and C pins for FCC1 Ethernet. */
129 tempval = in_be32(&io->iop_pdira);
130 tempval &= ~PA1_DIRA0;
131 tempval |= PA1_DIRA1;
132 out_be32(&io->iop_pdira, tempval);
134 tempval = in_be32(&io->iop_psora);
135 tempval &= ~PA1_PSORA0;
136 tempval |= PA1_PSORA1;
137 out_be32(&io->iop_psora, tempval);
139 setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
142 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
144 clrbits32(&io->iop_psorc, tempval);
145 clrbits32(&io->iop_pdirc, tempval);
146 setbits32(&io->iop_pparc, tempval);
148 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
149 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
155 static void init_fcc2_ioports(struct fs_platform_info *fpi)
157 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
158 struct device_node *np;
165 np = of_find_node_by_type(NULL, "memory");
167 printk(KERN_INFO "No memory node in device tree\n");
170 if (of_address_to_resource(np, 1, &r)) {
171 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
175 io = &immap->im_ioport;
176 bcsr = ioremap(r.start + 12, sizeof(u32));
179 clrbits32(bcsr, BCSR3_FETHIEN2);
180 setbits32(bcsr, BCSR3_FETH2_RST);
182 /* FCC2 are port B/C. */
183 /* Configure port A and C pins for FCC2 Ethernet. */
185 tempval = in_be32(&io->iop_pdirb);
186 tempval &= ~PB2_DIRB0;
187 tempval |= PB2_DIRB1;
188 out_be32(&io->iop_pdirb, tempval);
190 tempval = in_be32(&io->iop_psorb);
191 tempval &= ~PB2_PSORB0;
192 tempval |= PB2_PSORB1;
193 out_be32(&io->iop_psorb, tempval);
195 setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
197 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
200 clrbits32(&io->iop_psorc, tempval);
201 clrbits32(&io->iop_pdirc, tempval);
202 setbits32(&io->iop_pparc, tempval);
204 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
205 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
211 void init_fcc_ioports(struct fs_platform_info *fpi)
213 int fcc_no = fs_get_fcc_index(fpi->fs_no);
217 init_fcc1_ioports(fpi);
220 init_fcc2_ioports(fpi);
223 printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
228 static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
230 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
232 /* SCC1 is only on port D */
233 setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
234 clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
235 setbits32(&immap->im_ioport.iop_psord, 0x00000002);
236 clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
237 setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
239 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
240 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
241 setbits32(&immap->im_cpmux.cmx_scr,
242 ((data->clk_tx - 1) << (4 - data->clk_tx)));
243 setbits32(&immap->im_cpmux.cmx_scr,
244 ((data->clk_rx - 1) << (4 - data->clk_rx)));
249 static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
251 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
253 setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
254 clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
255 clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
256 setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
258 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
259 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
260 setbits32(&immap->im_cpmux.cmx_scr,
261 ((data->clk_tx - 1) << (4 - data->clk_tx)));
262 setbits32(&immap->im_cpmux.cmx_scr,
263 ((data->clk_rx - 1) << (4 - data->clk_rx)));
268 void init_scc_ioports(struct fs_uart_platform_info *data)
270 int scc_no = fs_get_scc_index(data->fs_no);
274 init_scc1_uart_ioports(data);
275 data->brg = data->clk_rx;
278 init_scc4_uart_ioports(data);
279 data->brg = data->clk_rx;
282 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
287 void __init m82xx_board_setup(void)
289 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
290 struct device_node *np;
294 np = of_find_node_by_type(NULL, "memory");
296 printk(KERN_INFO "No memory node in device tree\n");
299 if (of_address_to_resource(np, 1, &r)) {
300 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
304 bcsr = ioremap(r.start + 4, sizeof(u32));
305 /* Enable the 2nd UART port */
306 clrbits32(bcsr, BCSR1_RS232_EN2);
308 #ifdef CONFIG_SERIAL_CPM_SCC1
309 clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
310 UART_SCCM_TX | UART_SCCM_RX);
311 clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
312 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
315 #ifdef CONFIG_SERIAL_CPM_SCC2
316 clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
317 UART_SCCM_TX | UART_SCCM_RX);
318 clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
319 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
322 #ifdef CONFIG_SERIAL_CPM_SCC3
323 clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
324 UART_SCCM_TX | UART_SCCM_RX);
325 clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
326 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
329 #ifdef CONFIG_SERIAL_CPM_SCC4
330 clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
331 UART_SCCM_TX | UART_SCCM_RX);
332 clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
333 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
341 static void m82xx_pci_mask_irq(unsigned int irq)
343 int bit = irq - pci_int_base;
345 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
349 static void m82xx_pci_unmask_irq(unsigned int irq)
351 int bit = irq - pci_int_base;
353 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
357 static void m82xx_pci_mask_and_ack(unsigned int irq)
359 int bit = irq - pci_int_base;
361 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
365 static void m82xx_pci_end_irq(unsigned int irq)
367 int bit = irq - pci_int_base;
369 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
373 struct hw_interrupt_type m82xx_pci_ic = {
374 .typename = "MPC82xx ADS PCI",
375 .name = "MPC82xx ADS PCI",
376 .enable = m82xx_pci_unmask_irq,
377 .disable = m82xx_pci_mask_irq,
378 .ack = m82xx_pci_mask_and_ack,
379 .end = m82xx_pci_end_irq,
380 .mask = m82xx_pci_mask_irq,
381 .mask_ack = m82xx_pci_mask_and_ack,
382 .unmask = m82xx_pci_unmask_irq,
383 .eoi = m82xx_pci_end_irq,
387 m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
389 unsigned long stat, mask, pend;
393 stat = *pci_regs.pci_int_stat_reg;
394 mask = *pci_regs.pci_int_mask_reg;
395 pend = stat & ~mask & 0xf0000000;
398 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
399 if (pend & 0x80000000)
400 __do_IRQ(pci_int_base + bit);
405 static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
407 return node == pci_pic_node;
410 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
413 get_irq_desc(virq)->status |= IRQ_LEVEL;
414 set_irq_chip(virq, &m82xx_pci_ic);
418 static void pci_host_unmap(struct irq_host *h, unsigned int virq)
420 /* remove chip and handler */
421 set_irq_chip(virq, NULL);
424 static struct irq_host_ops pci_pic_host_ops = {
425 .match = pci_pic_host_match,
426 .map = pci_pic_host_map,
427 .unmap = pci_host_unmap,
430 void m82xx_pci_init_irq(void)
434 struct device_node *np;
440 unsigned int irq_max, irq_min;
442 if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
443 printk(KERN_INFO "No SOC node in device tree\n");
446 memset(&r, 0, sizeof(r));
447 if (of_address_to_resource(np, 0, &r)) {
448 printk(KERN_INFO "No SOC reg property in device tree\n");
451 immap = ioremap(r.start, sizeof(*immap));
454 /* install the demultiplexer for the PCI cascade interrupt */
455 np = of_find_node_by_type(NULL, "pci");
457 printk(KERN_INFO "No pci node on device tree\n");
461 irq_map = get_property(np, "interrupt-map", &size);
462 if ((!irq_map) || (size <= 7)) {
463 printk(KERN_INFO "No interrupt-map property of pci node\n");
467 size /= sizeof(irq_map[0]);
468 for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
469 if (irq_map[5] < irq_min)
470 irq_min = irq_map[5];
471 if (irq_map[5] > irq_max)
472 irq_max = irq_map[5];
474 pci_int_base = irq_min;
475 irq = irq_of_parse_and_map(np, 0);
476 set_irq_chained_handler(irq, m82xx_pci_irq_demux);
478 np = of_find_node_by_type(NULL, "pci-pic");
480 printk(KERN_INFO "No pci pic node on device tree\n");
484 pci_pic_node = of_node_get(np);
485 /* PCI interrupt controller registers: status and mask */
486 regs = get_property(np, "reg", &size);
487 if ((!regs) || (size <= 2)) {
488 printk(KERN_INFO "No reg property in pci pic node\n");
492 pci_regs.pci_int_stat_reg =
493 ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
494 pci_regs.pci_int_mask_reg =
495 ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
497 /* configure chip select for PCI interrupt controller */
498 immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
499 immap->im_memctl.memc_or3 = 0xffff8010;
500 /* make PCI IRQ level sensitive */
501 immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
503 /* mask all PCI interrupts */
504 *pci_regs.pci_int_mask_reg |= 0xfff00000;
507 irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
508 &pci_pic_host_ops, irq_max + 1);
512 static int m82xx_pci_exclude_device(u_char bus, u_char devfn)
514 if (bus == 0 && PCI_SLOT(devfn) == 0)
515 return PCIBIOS_DEVICE_NOT_FOUND;
517 return PCIBIOS_SUCCESSFUL;
521 __init mpc82xx_pcibios_fixup(void)
523 struct pci_dev *dev = NULL;
525 for_each_pci_dev(dev) {
526 pci_read_irq_line(dev);
530 void __init add_bridge(struct device_node *np)
533 struct pci_controller *hose;
535 const int *bus_range;
538 memset(&r, 0, sizeof(r));
539 if (of_address_to_resource(np, 0, &r)) {
540 printk(KERN_INFO "No PCI reg property in device tree\n");
543 if (!(ptr = get_property(np, "clock-frequency", NULL))) {
544 printk(KERN_INFO "No clock-frequency property in PCI node");
547 pci_clk_frq = *(uint *) ptr;
549 bus_range = get_property(np, "bus-range", &len);
550 if (bus_range == NULL || len < 2 * sizeof(int)) {
551 printk(KERN_WARNING "Can't get bus-range for %s, assume"
552 " bus 0\n", np->full_name);
555 pci_assign_all_buses = 1;
557 hose = pcibios_alloc_controller();
562 hose->arch_data = np;
563 hose->set_cfg_type = 1;
565 hose->first_busno = bus_range ? bus_range[0] : 0;
566 hose->last_busno = bus_range ? bus_range[1] : 0xff;
567 hose->bus_offset = 0;
569 hose->set_cfg_type = 1;
571 setup_indirect_pci(hose,
572 r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
573 r.start + offsetof(pci_cpm2_t, pci_cfg_data));
575 pci_process_bridge_OF_ranges(hose, np, 1);
580 * Setup the architecture
582 static void __init mpc82xx_ads_setup_arch(void)
585 struct device_node *np;
589 ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
592 /* Map I/O region to a 256MB BAT */
597 ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
598 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
602 ppc_md.pci_map_irq = NULL;
603 ppc_md.pcibios_fixup = mpc82xx_pcibios_fixup;
604 ppc_md.pcibios_fixup_bus = NULL;
607 #ifdef CONFIG_ROOT_NFS
610 ROOT_DEV = Root_HDA1;
614 ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
618 * Called very early, device-tree isn't unflattened
620 static int __init mpc82xx_ads_probe(void)
622 /* We always match for now, eventually we should look at
623 * the flat dev tree to ensure this is the board we are
629 #define RMR_CSRE 0x00000001
630 static void m82xx_restart(char *cmd)
632 __volatile__ unsigned char dummy;
635 ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
637 /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
638 mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
639 dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
640 printk("Restart failed\n");
644 static void m82xx_halt(void)
650 define_machine(mpc82xx_ads)
652 .name = "MPC82xx ADS",
653 .probe = mpc82xx_ads_probe,
654 .setup_arch = mpc82xx_ads_setup_arch,
655 .init_IRQ = mpc82xx_ads_pic_init,
656 .show_cpuinfo = mpc82xx_ads_show_cpuinfo,
657 .get_irq = cpm2_get_irq,
658 .calibrate_decr = m82xx_calibrate_decr,
659 .restart = m82xx_restart,.halt = m82xx_halt,