arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/sched.h>
  38 #include <linux/kernel.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/smp.h>
  42 #include <linux/stddef.h>
  43 #include <linux/unistd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/spu.h>
  47 #include <asm/spu_priv1.h>
  48 #include <asm/spu_csa.h>
  49 #include <asm/mmu_context.h>
  50
  51 #include "spu_save_dump.h"
  52 #include "spu_restore_dump.h"
  53
  54 #if 0
  55 #define POLL_WHILE_TRUE(_c) {                           \
  56     do {                                                \
  57     } while (_c);                                       \
  58   }
  59 #else
  60 #define RELAX_SPIN_COUNT                                1000
  61 #define POLL_WHILE_TRUE(_c) {                           \
  62     do {                                                \
  63         int _i;                                         \
  64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  65             cpu_relax();                                \
  66         }                                               \
  67         if (unlikely(_c)) yield();                      \
  68         else break;                                     \
  69     } while (_c);                                       \
  70   }
  71 #endif                          /* debug */
  72
  73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  74
  75 static inline void acquire_spu_lock(struct spu *spu)
  76 {
  77         /* Save, Step 1:
  78          * Restore, Step 1:
  79          *    Acquire SPU-specific mutual exclusion lock.
  80          *    TBD.
  81          */
  82 }
  83
  84 static inline void release_spu_lock(struct spu *spu)
  85 {
  86         /* Restore, Step 76:
  87          *    Release SPU-specific mutual exclusion lock.
  88          *    TBD.
  89          */
  90 }
  91
  92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  93 {
  94         struct spu_problem __iomem *prob = spu->problem;
  95         u32 isolate_state;
  96
  97         /* Save, Step 2:
  98          * Save, Step 6:
  99          *     If SPU_Status[E,L,IS] any field is '1', this
 100          *     SPU is in isolate state and cannot be context
 101          *     saved at this time.
 102          */
 103         isolate_state = SPU_STATUS_ISOLATED_STATE |
 104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 106 }
 107
 108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 109 {
 110         /* Save, Step 3:
 111          * Restore, Step 2:
 112          *     Save INT_Mask_class0 in CSA.
 113          *     Write INT_MASK_class0 with value of 0.
 114          *     Save INT_Mask_class1 in CSA.
 115          *     Write INT_MASK_class1 with value of 0.
 116          *     Save INT_Mask_class2 in CSA.
 117          *     Write INT_MASK_class2 with value of 0.
 118          */
 119         spin_lock_irq(&spu->register_lock);
 120         if (csa) {
 121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 124         }
 125         spu_int_mask_set(spu, 0, 0ul);
 126         spu_int_mask_set(spu, 1, 0ul);
 127         spu_int_mask_set(spu, 2, 0ul);
 128         eieio();
 129         spin_unlock_irq(&spu->register_lock);
 130 }
 131
 132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 133 {
 134         /* Save, Step 4:
 135          * Restore, Step 25.
 136          *    Set a software watchdog timer, which specifies the
 137          *    maximum allowable time for a context save sequence.
 138          *
 139          *    For present, this implementation will not set a global
 140          *    watchdog timer, as virtualization & variable system load
 141          *    may cause unpredictable execution times.
 142          */
 143 }
 144
 145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 146 {
 147         /* Save, Step 5:
 148          * Restore, Step 3:
 149          *     Inhibit user-space access (if provided) to this
 150          *     SPU by unmapping the virtual pages assigned to
 151          *     the SPU memory-mapped I/O (MMIO) for problem
 152          *     state. TBD.
 153          */
 154 }
 155
 156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 157 {
 158         /* Save, Step 7:
 159          * Restore, Step 5:
 160          *     Set a software context switch pending flag.
 161          */
 162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 163         mb();
 164 }
 165
 166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 167 {
 168         struct spu_priv2 __iomem *priv2 = spu->priv2;
 169
 170         /* Save, Step 8:
 171          *     Suspend DMA and save MFC_CNTL.
 172          */
 173         switch (in_be64(&priv2->mfc_control_RW) &
 174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 178                                  MFC_CNTL_SUSPEND_COMPLETE);
 179                 /* fall through */
 180         case MFC_CNTL_SUSPEND_COMPLETE:
 181                 if (csa) {
 182                         csa->priv2.mfc_control_RW =
 183                                 in_be64(&priv2->mfc_control_RW) |
 184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 185                 }
 186                 break;
 187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 191                                  MFC_CNTL_SUSPEND_COMPLETE);
 192                 if (csa) {
 193                         csa->priv2.mfc_control_RW =
 194                                 in_be64(&priv2->mfc_control_RW) &
 195                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
 196                 }
 197                 break;
 198         }
 199 }
 200
 201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 202 {
 203         struct spu_problem __iomem *prob = spu->problem;
 204
 205         /* Save, Step 9:
 206          *     Save SPU_Runcntl in the CSA.  This value contains
 207          *     the "Application Desired State".
 208          */
 209         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 210 }
 211
 212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 213 {
 214         /* Save, Step 10:
 215          *     Save MFC_SR1 in the CSA.
 216          */
 217         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 218 }
 219
 220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 221 {
 222         struct spu_problem __iomem *prob = spu->problem;
 223
 224         /* Save, Step 11:
 225          *     Read SPU_Status[R], and save to CSA.
 226          */
 227         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 228                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 229         } else {
 230                 u32 stopped;
 231
 232                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 233                 eieio();
 234                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 235                                 SPU_STATUS_RUNNING);
 236                 stopped =
 237                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 238                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 239                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 240                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 241                 else
 242                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 243         }
 244 }
 245
 246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 247 {
 248         struct spu_priv2 __iomem *priv2 = spu->priv2;
 249
 250         /* Save, Step 12:
 251          *     Read MFC_CNTL[Ds].  Update saved copy of
 252          *     CSA.MFC_CNTL[Ds].
 253          */
 254         if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
 255                 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
 256                 csa->suspend_time = get_cycles();
 257                 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
 258                 eieio();
 259                 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
 260                 eieio();
 261         } else {
 262                 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
 263         }
 264 }
 265
 266 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 267 {
 268         struct spu_priv2 __iomem *priv2 = spu->priv2;
 269
 270         /* Save, Step 13:
 271          *     Write MFC_CNTL[Dh] set to a '1' to halt
 272          *     the decrementer.
 273          */
 274         out_be64(&priv2->mfc_control_RW, MFC_CNTL_DECREMENTER_HALTED);
 275         eieio();
 276 }
 277
 278 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 279 {
 280         /* Save, Step 14:
 281          *    Read PPE Timebase High and Timebase low registers
 282          *    and save in CSA.  TBD.
 283          */
 284         csa->suspend_time = get_cycles();
 285 }
 286
 287 static inline void remove_other_spu_access(struct spu_state *csa,
 288                                            struct spu *spu)
 289 {
 290         /* Save, Step 15:
 291          *     Remove other SPU access to this SPU by unmapping
 292          *     this SPU's pages from their address space.  TBD.
 293          */
 294 }
 295
 296 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 297 {
 298         struct spu_problem __iomem *prob = spu->problem;
 299
 300         /* Save, Step 16:
 301          * Restore, Step 11.
 302          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 303          *     for a value of 0.
 304          */
 305         out_be64(&prob->spc_mssync_RW, 1UL);
 306         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 307 }
 308
 309 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 310 {
 311         /* Save, Step 17:
 312          * Restore, Step 12.
 313          * Restore, Step 48.
 314          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 315          *     Then issue a PPE sync instruction.
 316          */
 317         spu_tlb_invalidate(spu);
 318         mb();
 319 }
 320
 321 static inline void handle_pending_interrupts(struct spu_state *csa,
 322                                              struct spu *spu)
 323 {
 324         /* Save, Step 18:
 325          *     Handle any pending interrupts from this SPU
 326          *     here.  This is OS or hypervisor specific.  One
 327          *     option is to re-enable interrupts to handle any
 328          *     pending interrupts, with the interrupt handlers
 329          *     recognizing the software Context Switch Pending
 330          *     flag, to ensure the SPU execution or MFC command
 331          *     queue is not restarted.  TBD.
 332          */
 333 }
 334
 335 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 336 {
 337         struct spu_priv2 __iomem *priv2 = spu->priv2;
 338         int i;
 339
 340         /* Save, Step 19:
 341          *     If MFC_Cntl[Se]=0 then save
 342          *     MFC command queues.
 343          */
 344         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 345                 for (i = 0; i < 8; i++) {
 346                         csa->priv2.puq[i].mfc_cq_data0_RW =
 347                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 348                         csa->priv2.puq[i].mfc_cq_data1_RW =
 349                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 350                         csa->priv2.puq[i].mfc_cq_data2_RW =
 351                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 352                         csa->priv2.puq[i].mfc_cq_data3_RW =
 353                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 354                 }
 355                 for (i = 0; i < 16; i++) {
 356                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 357                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 358                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 359                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 360                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 361                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 362                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 363                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 364                 }
 365         }
 366 }
 367
 368 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 369 {
 370         struct spu_problem __iomem *prob = spu->problem;
 371
 372         /* Save, Step 20:
 373          *     Save the PPU_QueryMask register
 374          *     in the CSA.
 375          */
 376         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 377 }
 378
 379 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 380 {
 381         struct spu_problem __iomem *prob = spu->problem;
 382
 383         /* Save, Step 21:
 384          *     Save the PPU_QueryType register
 385          *     in the CSA.
 386          */
 387         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 388 }
 389
 390 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 391 {
 392         struct spu_problem __iomem *prob = spu->problem;
 393
 394         /* Save the Prxy_TagStatus register in the CSA.
 395          *
 396          * It is unnecessary to restore dma_tagstatus_R, however,
 397          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 398          * we must save it.
 399          */
 400         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 401 }
 402
 403 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 404 {
 405         struct spu_priv2 __iomem *priv2 = spu->priv2;
 406
 407         /* Save, Step 22:
 408          *     Save the MFC_CSR_TSQ register
 409          *     in the LSCSA.
 410          */
 411         csa->priv2.spu_tag_status_query_RW =
 412             in_be64(&priv2->spu_tag_status_query_RW);
 413 }
 414
 415 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 416 {
 417         struct spu_priv2 __iomem *priv2 = spu->priv2;
 418
 419         /* Save, Step 23:
 420          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 421          *     registers in the CSA.
 422          */
 423         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 424         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 425 }
 426
 427 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 428 {
 429         struct spu_priv2 __iomem *priv2 = spu->priv2;
 430
 431         /* Save, Step 24:
 432          *     Save the MFC_CSR_ATO register in
 433          *     the CSA.
 434          */
 435         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 436 }
 437
 438 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 439 {
 440         /* Save, Step 25:
 441          *     Save the MFC_TCLASS_ID register in
 442          *     the CSA.
 443          */
 444         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 445 }
 446
 447 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 448 {
 449         /* Save, Step 26:
 450          * Restore, Step 23.
 451          *     Write the MFC_TCLASS_ID register with
 452          *     the value 0x10000000.
 453          */
 454         spu_mfc_tclass_id_set(spu, 0x10000000);
 455         eieio();
 456 }
 457
 458 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 459 {
 460         struct spu_priv2 __iomem *priv2 = spu->priv2;
 461
 462         /* Save, Step 27:
 463          * Restore, Step 14.
 464          *     Write MFC_CNTL[Pc]=1 (purge queue).
 465          */
 466         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
 467         eieio();
 468 }
 469
 470 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 471 {
 472         struct spu_priv2 __iomem *priv2 = spu->priv2;
 473
 474         /* Save, Step 28:
 475          *     Poll MFC_CNTL[Ps] until value '11' is read
 476          *     (purge complete).
 477          */
 478         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 479                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 480                          MFC_CNTL_PURGE_DMA_COMPLETE);
 481 }
 482
 483 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 484 {
 485         /* Save, Step 30:
 486          * Restore, Step 18:
 487          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 488          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 489          *     OS specific environment.
 490          *
 491          *     Implementation note: The SPU-side code
 492          *     for save/restore is privileged, so the
 493          *     MFC_SR1[Pr] bit is not set.
 494          *
 495          */
 496         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 497                               MFC_STATE1_RELOCATE_MASK |
 498                               MFC_STATE1_BUS_TLBIE_MASK));
 499 }
 500
 501 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 502 {
 503         struct spu_problem __iomem *prob = spu->problem;
 504
 505         /* Save, Step 31:
 506          *     Save SPU_NPC in the CSA.
 507          */
 508         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 509 }
 510
 511 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 512 {
 513         struct spu_priv2 __iomem *priv2 = spu->priv2;
 514
 515         /* Save, Step 32:
 516          *     Save SPU_PrivCntl in the CSA.
 517          */
 518         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 519 }
 520
 521 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 522 {
 523         struct spu_priv2 __iomem *priv2 = spu->priv2;
 524
 525         /* Save, Step 33:
 526          * Restore, Step 16:
 527          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 528          */
 529         out_be64(&priv2->spu_privcntl_RW, 0UL);
 530         eieio();
 531 }
 532
 533 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 534 {
 535         struct spu_priv2 __iomem *priv2 = spu->priv2;
 536
 537         /* Save, Step 34:
 538          *     Save SPU_LSLR in the CSA.
 539          */
 540         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 541 }
 542
 543 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 544 {
 545         struct spu_priv2 __iomem *priv2 = spu->priv2;
 546
 547         /* Save, Step 35:
 548          * Restore, Step 17.
 549          *     Reset SPU_LSLR.
 550          */
 551         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 552         eieio();
 553 }
 554
 555 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 556 {
 557         struct spu_priv2 __iomem *priv2 = spu->priv2;
 558
 559         /* Save, Step 36:
 560          *     Save SPU_Cfg in the CSA.
 561          */
 562         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 563 }
 564
 565 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 566 {
 567         /* Save, Step 37:
 568          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 569          *     Not performed by this implementation.
 570          */
 571 }
 572
 573 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 574 {
 575         /* Save, Step 38:
 576          *     Save RA_GROUP_ID register and the
 577          *     RA_ENABLE reigster in the CSA.
 578          */
 579         csa->priv1.resource_allocation_groupID_RW =
 580                 spu_resource_allocation_groupID_get(spu);
 581         csa->priv1.resource_allocation_enable_RW =
 582                 spu_resource_allocation_enable_get(spu);
 583 }
 584
 585 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 586 {
 587         struct spu_problem __iomem *prob = spu->problem;
 588
 589         /* Save, Step 39:
 590          *     Save MB_Stat register in the CSA.
 591          */
 592         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 593 }
 594
 595 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 596 {
 597         struct spu_problem __iomem *prob = spu->problem;
 598
 599         /* Save, Step 40:
 600          *     Save the PPU_MB register in the CSA.
 601          */
 602         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 603 }
 604
 605 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 606 {
 607         struct spu_priv2 __iomem *priv2 = spu->priv2;
 608
 609         /* Save, Step 41:
 610          *     Save the PPUINT_MB register in the CSA.
 611          */
 612         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 613 }
 614
 615 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 616 {
 617         struct spu_priv2 __iomem *priv2 = spu->priv2;
 618         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 619         int i;
 620
 621         /* Save, Step 42:
 622          */
 623
 624         /* Save CH 1, without channel count */
 625         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 626         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 627
 628         /* Save the following CH: [0,3,4,24,25,27] */
 629         for (i = 0; i < 7; i++) {
 630                 idx = ch_indices[i];
 631                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 632                 eieio();
 633                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 634                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 635                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 636                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 637                 eieio();
 638         }
 639 }
 640
 641 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 642 {
 643         struct spu_priv2 __iomem *priv2 = spu->priv2;
 644         int i;
 645
 646         /* Save, Step 43:
 647          *     Save SPU Read Mailbox Channel.
 648          */
 649         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 650         eieio();
 651         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 652         for (i = 0; i < 4; i++) {
 653                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 654         }
 655         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 656         eieio();
 657 }
 658
 659 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 660 {
 661         struct spu_priv2 __iomem *priv2 = spu->priv2;
 662
 663         /* Save, Step 44:
 664          *     Save MFC_CMD Channel.
 665          */
 666         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 667         eieio();
 668         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 669         eieio();
 670 }
 671
 672 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 673 {
 674         struct spu_priv2 __iomem *priv2 = spu->priv2;
 675         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 676         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 677         u64 idx;
 678         int i;
 679
 680         /* Save, Step 45:
 681          *     Reset the following CH: [21, 23, 28, 30]
 682          */
 683         for (i = 0; i < 4; i++) {
 684                 idx = ch_indices[i];
 685                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 686                 eieio();
 687                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 688                 eieio();
 689         }
 690 }
 691
 692 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 693 {
 694         struct spu_priv2 __iomem *priv2 = spu->priv2;
 695
 696         /* Save, Step 46:
 697          * Restore, Step 25.
 698          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 699          */
 700         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 701 }
 702
 703 static inline void get_kernel_slb(u64 ea, u64 slb[2])
 704 {
 705         u64 llp;
 706
 707         if (REGION_ID(ea) == KERNEL_REGION_ID)
 708                 llp = mmu_psize_defs[mmu_linear_psize].sllp;
 709         else
 710                 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
 711         slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 712                 SLB_VSID_KERNEL | llp;
 713         slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
 714 }
 715
 716 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
 717 {
 718         struct spu_priv2 __iomem *priv2 = spu->priv2;
 719
 720         out_be64(&priv2->slb_index_W, slbe);
 721         eieio();
 722         out_be64(&priv2->slb_vsid_RW, slb[0]);
 723         out_be64(&priv2->slb_esid_RW, slb[1]);
 724         eieio();
 725 }
 726
 727 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
 728 {
 729         u64 code_slb[2];
 730         u64 lscsa_slb[2];
 731
 732         /* Save, Step 47:
 733          * Restore, Step 30.
 734          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 735          *     register, then initialize SLB_VSID and SLB_ESID
 736          *     to provide access to SPU context save code and
 737          *     LSCSA.
 738          *
 739          *     This implementation places both the context
 740          *     switch code and LSCSA in kernel address space.
 741          *
 742          *     Further this implementation assumes that the
 743          *     MFC_SR1[R]=1 (in other words, assume that
 744          *     translation is desired by OS environment).
 745          */
 746         spu_invalidate_slbs(spu);
 747         get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
 748         get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
 749         load_mfc_slb(spu, code_slb, 0);
 750         if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
 751                 load_mfc_slb(spu, lscsa_slb, 1);
 752 }
 753
 754 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 755 {
 756         /* Save, Step 48:
 757          * Restore, Step 23.
 758          *     Change the software context switch pending flag
 759          *     to context switch active.
 760          */
 761         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
 762         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 763         mb();
 764 }
 765
 766 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 767 {
 768         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 769             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 770
 771         /* Save, Step 49:
 772          * Restore, Step 22:
 773          *     Reset and then enable interrupts, as
 774          *     needed by OS.
 775          *
 776          *     This implementation enables only class1
 777          *     (translation) interrupts.
 778          */
 779         spin_lock_irq(&spu->register_lock);
 780         spu_int_stat_clear(spu, 0, ~0ul);
 781         spu_int_stat_clear(spu, 1, ~0ul);
 782         spu_int_stat_clear(spu, 2, ~0ul);
 783         spu_int_mask_set(spu, 0, 0ul);
 784         spu_int_mask_set(spu, 1, class1_mask);
 785         spu_int_mask_set(spu, 2, 0ul);
 786         spin_unlock_irq(&spu->register_lock);
 787 }
 788
 789 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 790                                unsigned int ls_offset, unsigned int size,
 791                                unsigned int tag, unsigned int rclass,
 792                                unsigned int cmd)
 793 {
 794         struct spu_problem __iomem *prob = spu->problem;
 795         union mfc_tag_size_class_cmd command;
 796         unsigned int transfer_size;
 797         volatile unsigned int status = 0x0;
 798
 799         while (size > 0) {
 800                 transfer_size =
 801                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 802                 command.u.mfc_size = transfer_size;
 803                 command.u.mfc_tag = tag;
 804                 command.u.mfc_rclassid = rclass;
 805                 command.u.mfc_cmd = cmd;
 806                 do {
 807                         out_be32(&prob->mfc_lsa_W, ls_offset);
 808                         out_be64(&prob->mfc_ea_W, ea);
 809                         out_be64(&prob->mfc_union_W.all64, command.all64);
 810                         status =
 811                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 812                         if (unlikely(status & 0x2)) {
 813                                 cpu_relax();
 814                         }
 815                 } while (status & 0x3);
 816                 size -= transfer_size;
 817                 ea += transfer_size;
 818                 ls_offset += transfer_size;
 819         }
 820         return 0;
 821 }
 822
 823 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 824 {
 825         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 826         unsigned int ls_offset = 0x0;
 827         unsigned int size = 16384;
 828         unsigned int tag = 0;
 829         unsigned int rclass = 0;
 830         unsigned int cmd = MFC_PUT_CMD;
 831
 832         /* Save, Step 50:
 833          *     Issue a DMA command to copy the first 16K bytes
 834          *     of local storage to the CSA.
 835          */
 836         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 837 }
 838
 839 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 840 {
 841         struct spu_problem __iomem *prob = spu->problem;
 842
 843         /* Save, Step 51:
 844          * Restore, Step 31.
 845          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 846          *     point address of context save code in local
 847          *     storage.
 848          *
 849          *     This implementation uses SPU-side save/restore
 850          *     programs with entry points at LSA of 0.
 851          */
 852         out_be32(&prob->spu_npc_RW, 0);
 853         eieio();
 854 }
 855
 856 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 857 {
 858         struct spu_problem __iomem *prob = spu->problem;
 859         union {
 860                 u64 ull;
 861                 u32 ui[2];
 862         } addr64;
 863
 864         /* Save, Step 52:
 865          * Restore, Step 32:
 866          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 867          *    of the CSA.LSCSA effective address.
 868          */
 869         addr64.ull = (u64) csa->lscsa;
 870         out_be32(&prob->signal_notify1, addr64.ui[0]);
 871         eieio();
 872 }
 873
 874 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 875 {
 876         struct spu_problem __iomem *prob = spu->problem;
 877         union {
 878                 u64 ull;
 879                 u32 ui[2];
 880         } addr64;
 881
 882         /* Save, Step 53:
 883          * Restore, Step 33:
 884          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 885          *    of the CSA.LSCSA effective address.
 886          */
 887         addr64.ull = (u64) csa->lscsa;
 888         out_be32(&prob->signal_notify2, addr64.ui[1]);
 889         eieio();
 890 }
 891
 892 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 893 {
 894         unsigned long addr = (unsigned long)&spu_save_code[0];
 895         unsigned int ls_offset = 0x0;
 896         unsigned int size = sizeof(spu_save_code);
 897         unsigned int tag = 0;
 898         unsigned int rclass = 0;
 899         unsigned int cmd = MFC_GETFS_CMD;
 900
 901         /* Save, Step 54:
 902          *     Issue a DMA command to copy context save code
 903          *     to local storage and start SPU.
 904          */
 905         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 906 }
 907
 908 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 909 {
 910         struct spu_problem __iomem *prob = spu->problem;
 911
 912         /* Save, Step 55:
 913          * Restore, Step 38.
 914          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 915          *     and issue eieio instruction.
 916          */
 917         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 918         eieio();
 919 }
 920
 921 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 922 {
 923         struct spu_problem __iomem *prob = spu->problem;
 924         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 925         unsigned long flags;
 926
 927         /* Save, Step 56:
 928          * Restore, Step 39.
 929          * Restore, Step 39.
 930          * Restore, Step 46.
 931          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 932          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 933          *     Complete Interrupt.  Write INT_Stat_Class0 or
 934          *     INT_Stat_Class2 with value of 'handled'.
 935          */
 936         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 937
 938         local_irq_save(flags);
 939         spu_int_stat_clear(spu, 0, ~(0ul));
 940         spu_int_stat_clear(spu, 2, ~(0ul));
 941         local_irq_restore(flags);
 942 }
 943
 944 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 945 {
 946         struct spu_problem __iomem *prob = spu->problem;
 947         unsigned long flags;
 948
 949         /* Save, Step 57:
 950          * Restore, Step 40.
 951          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 952          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 953          *     or INT_Stat_class2 with value of handled.
 954          */
 955         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 956
 957         local_irq_save(flags);
 958         spu_int_stat_clear(spu, 0, ~(0ul));
 959         spu_int_stat_clear(spu, 2, ~(0ul));
 960         local_irq_restore(flags);
 961 }
 962
 963 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 964 {
 965         struct spu_problem __iomem *prob = spu->problem;
 966         u32 complete;
 967
 968         /* Save, Step 54:
 969          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 970          *     context save succeeded, otherwise context save
 971          *     failed.
 972          */
 973         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 974                     SPU_STATUS_STOPPED_BY_STOP);
 975         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 976 }
 977
 978 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 979 {
 980         /* Restore, Step 4:
 981          *    If required, notify the "using application" that
 982          *    the SPU task has been terminated.  TBD.
 983          */
 984 }
 985
 986 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
 987 {
 988         struct spu_priv2 __iomem *priv2 = spu->priv2;
 989
 990         /* Restore, Step 7:
 991          * Restore, Step 47.
 992          *     Write MFC_Cntl[Dh,Sc]='1','1' to suspend
 993          *     the queue and halt the decrementer.
 994          */
 995         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 996                  MFC_CNTL_DECREMENTER_HALTED);
 997         eieio();
 998 }
 999
1000 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
1001                                              struct spu *spu)
1002 {
1003         struct spu_priv2 __iomem *priv2 = spu->priv2;
1004
1005         /* Restore, Step 8:
1006          * Restore, Step 47.
1007          *     Poll MFC_CNTL[Ss] until 11 is returned.
1008          */
1009         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1010                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
1011                          MFC_CNTL_SUSPEND_COMPLETE);
1012 }
1013
1014 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1015 {
1016         struct spu_problem __iomem *prob = spu->problem;
1017
1018         /* Restore, Step 9:
1019          *    If SPU_Status[R]=1, stop SPU execution
1020          *    and wait for stop to complete.
1021          *
1022          *    Returns       1 if SPU_Status[R]=1 on entry.
1023          *                  0 otherwise
1024          */
1025         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1026                 if (in_be32(&prob->spu_status_R) &
1027                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1028                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1029                                         SPU_STATUS_RUNNING);
1030                 }
1031                 if ((in_be32(&prob->spu_status_R) &
1032                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1033                     || (in_be32(&prob->spu_status_R) &
1034                         SPU_STATUS_ISOLATED_STATE)) {
1035                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1036                         eieio();
1037                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1038                                         SPU_STATUS_RUNNING);
1039                         out_be32(&prob->spu_runcntl_RW, 0x2);
1040                         eieio();
1041                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1042                                         SPU_STATUS_RUNNING);
1043                 }
1044                 if (in_be32(&prob->spu_status_R) &
1045                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1046                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1047                         eieio();
1048                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1049                                         SPU_STATUS_RUNNING);
1050                 }
1051                 return 1;
1052         }
1053         return 0;
1054 }
1055
1056 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1057 {
1058         struct spu_problem __iomem *prob = spu->problem;
1059
1060         /* Restore, Step 10:
1061          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1062          *    release SPU from isolate state.
1063          */
1064         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1065                 if (in_be32(&prob->spu_status_R) &
1066                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1067                         spu_mfc_sr1_set(spu,
1068                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1069                         eieio();
1070                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1071                         eieio();
1072                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1073                                         SPU_STATUS_RUNNING);
1074                 }
1075                 if ((in_be32(&prob->spu_status_R) &
1076                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1077                     || (in_be32(&prob->spu_status_R) &
1078                         SPU_STATUS_ISOLATED_STATE)) {
1079                         spu_mfc_sr1_set(spu,
1080                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1081                         eieio();
1082                         out_be32(&prob->spu_runcntl_RW, 0x2);
1083                         eieio();
1084                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1085                                         SPU_STATUS_RUNNING);
1086                 }
1087         }
1088 }
1089
1090 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1091 {
1092         struct spu_priv2 __iomem *priv2 = spu->priv2;
1093         u64 ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1094         u64 idx;
1095         int i;
1096
1097         /* Restore, Step 20:
1098          */
1099
1100         /* Reset CH 1 */
1101         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1102         out_be64(&priv2->spu_chnldata_RW, 0UL);
1103
1104         /* Reset the following CH: [0,3,4,24,25,27] */
1105         for (i = 0; i < 7; i++) {
1106                 idx = ch_indices[i];
1107                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1108                 eieio();
1109                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1110                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1111                 eieio();
1112         }
1113 }
1114
1115 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1116 {
1117         struct spu_priv2 __iomem *priv2 = spu->priv2;
1118         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1119         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1120         u64 idx;
1121         int i;
1122
1123         /* Restore, Step 21:
1124          *     Reset the following CH: [21, 23, 28, 29, 30]
1125          */
1126         for (i = 0; i < 5; i++) {
1127                 idx = ch_indices[i];
1128                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1129                 eieio();
1130                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1131                 eieio();
1132         }
1133 }
1134
1135 static inline void setup_spu_status_part1(struct spu_state *csa,
1136                                           struct spu *spu)
1137 {
1138         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1139         u32 status_I = SPU_STATUS_INVALID_INSTR;
1140         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1141         u32 status_S = SPU_STATUS_SINGLE_STEP;
1142         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1143         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1144         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1145         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1146         u32 status_code;
1147
1148         /* Restore, Step 27:
1149          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1150          *     instruction sequence to the end of the SPU based restore
1151          *     code (after the "context restored" stop and signal) to
1152          *     restore the correct SPU status.
1153          *
1154          *     NOTE: Rather than modifying the SPU executable, we
1155          *     instead add a new 'stopped_status' field to the
1156          *     LSCSA.  The SPU-side restore reads this field and
1157          *     takes the appropriate action when exiting.
1158          */
1159
1160         status_code =
1161             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1162         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1163
1164                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1165                  * by Stop and Signal instruction, followed by 'br -4'.
1166                  *
1167                  */
1168                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1169                 csa->lscsa->stopped_status.slot[1] = status_code;
1170
1171         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1172
1173                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1174                  * by Stop and Signal instruction, followed by
1175                  * 'br -4'.
1176                  */
1177                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1178                 csa->lscsa->stopped_status.slot[1] = status_code;
1179
1180         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1181
1182                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1183                  * followed by 'br -4'.
1184                  */
1185                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1186                 csa->lscsa->stopped_status.slot[1] = status_code;
1187
1188         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1189
1190                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1191                  * by 'br -4'.
1192                  */
1193                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1194                 csa->lscsa->stopped_status.slot[1] = status_code;
1195
1196         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1197
1198                 /* SPU_Status[P]=1 - Stop and Signal instruction
1199                  * followed by 'br -4'.
1200                  */
1201                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1202                 csa->lscsa->stopped_status.slot[1] = status_code;
1203
1204         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1205
1206                 /* SPU_Status[H]=1 - Halt Conditional, followed
1207                  * by 'br -4'.
1208                  */
1209                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1210
1211         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1212
1213                 /* SPU_Status[S]=1 - Two nop instructions.
1214                  */
1215                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1216
1217         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1218
1219                 /* SPU_Status[I]=1 - Illegal instruction followed
1220                  * by 'br -4'.
1221                  */
1222                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1223
1224         }
1225 }
1226
1227 static inline void setup_spu_status_part2(struct spu_state *csa,
1228                                           struct spu *spu)
1229 {
1230         u32 mask;
1231
1232         /* Restore, Step 28:
1233          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1234          *     add a 'br *' instruction to the end of
1235          *     the SPU based restore code.
1236          *
1237          *     NOTE: Rather than modifying the SPU executable, we
1238          *     instead add a new 'stopped_status' field to the
1239          *     LSCSA.  The SPU-side restore reads this field and
1240          *     takes the appropriate action when exiting.
1241          */
1242         mask = SPU_STATUS_INVALID_INSTR |
1243             SPU_STATUS_SINGLE_STEP |
1244             SPU_STATUS_STOPPED_BY_HALT |
1245             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1246         if (!(csa->prob.spu_status_R & mask)) {
1247                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1248         }
1249 }
1250
1251 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1252 {
1253         /* Restore, Step 29:
1254          *     Restore RA_GROUP_ID register and the
1255          *     RA_ENABLE reigster from the CSA.
1256          */
1257         spu_resource_allocation_groupID_set(spu,
1258                         csa->priv1.resource_allocation_groupID_RW);
1259         spu_resource_allocation_enable_set(spu,
1260                         csa->priv1.resource_allocation_enable_RW);
1261 }
1262
1263 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1264 {
1265         unsigned long addr = (unsigned long)&spu_restore_code[0];
1266         unsigned int ls_offset = 0x0;
1267         unsigned int size = sizeof(spu_restore_code);
1268         unsigned int tag = 0;
1269         unsigned int rclass = 0;
1270         unsigned int cmd = MFC_GETFS_CMD;
1271
1272         /* Restore, Step 37:
1273          *     Issue MFC DMA command to copy context
1274          *     restore code to local storage.
1275          */
1276         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1277 }
1278
1279 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1280 {
1281         /* Restore, Step 34:
1282          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1283          *     running) then adjust decrementer, set
1284          *     decrementer running status in LSCSA,
1285          *     and set decrementer "wrapped" status
1286          *     in LSCSA.
1287          */
1288         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1289                 cycles_t resume_time = get_cycles();
1290                 cycles_t delta_time = resume_time - csa->suspend_time;
1291
1292                 csa->lscsa->decr.slot[0] -= delta_time;
1293         }
1294 }
1295
1296 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1297 {
1298         /* Restore, Step 35:
1299          *     Copy the CSA.PU_MB data into the LSCSA.
1300          */
1301         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1302 }
1303
1304 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1305 {
1306         /* Restore, Step 36:
1307          *     Copy the CSA.PUINT_MB data into the LSCSA.
1308          */
1309         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1310 }
1311
1312 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1313 {
1314         struct spu_problem __iomem *prob = spu->problem;
1315         u32 complete;
1316
1317         /* Restore, Step 40:
1318          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1319          *     context restore succeeded, otherwise context restore
1320          *     failed.
1321          */
1322         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1323                     SPU_STATUS_STOPPED_BY_STOP);
1324         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1325 }
1326
1327 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1328 {
1329         struct spu_priv2 __iomem *priv2 = spu->priv2;
1330
1331         /* Restore, Step 41:
1332          *     Restore SPU_PrivCntl from the CSA.
1333          */
1334         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1335         eieio();
1336 }
1337
1338 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1339 {
1340         struct spu_problem __iomem *prob = spu->problem;
1341         u32 mask;
1342
1343         /* Restore, Step 42:
1344          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1345          *     restore the error or single step state.
1346          */
1347         mask = SPU_STATUS_INVALID_INSTR |
1348             SPU_STATUS_SINGLE_STEP |
1349             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1350         if (csa->prob.spu_status_R & mask) {
1351                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1352                 eieio();
1353                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1354                                 SPU_STATUS_RUNNING);
1355         }
1356 }
1357
1358 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1359 {
1360         struct spu_problem __iomem *prob = spu->problem;
1361         u32 mask;
1362
1363         /* Restore, Step 43:
1364          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1365          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1366          *     then write '00' to SPU_RunCntl[R0R1] and wait
1367          *     for SPU_Status[R]=0.
1368          */
1369         mask = SPU_STATUS_INVALID_INSTR |
1370             SPU_STATUS_SINGLE_STEP |
1371             SPU_STATUS_STOPPED_BY_HALT |
1372             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1373         if (!(csa->prob.spu_status_R & mask)) {
1374                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1375                 eieio();
1376                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1377                                  SPU_STATUS_RUNNING);
1378                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1379                 eieio();
1380                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1381                                 SPU_STATUS_RUNNING);
1382         }
1383 }
1384
1385 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1386 {
1387         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1388         unsigned int ls_offset = 0x0;
1389         unsigned int size = 16384;
1390         unsigned int tag = 0;
1391         unsigned int rclass = 0;
1392         unsigned int cmd = MFC_GET_CMD;
1393
1394         /* Restore, Step 44:
1395          *     Issue a DMA command to restore the first
1396          *     16kb of local storage from CSA.
1397          */
1398         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1399 }
1400
1401 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1402 {
1403         /* Restore, Step 49:
1404          *     Write INT_MASK_class0 with value of 0.
1405          *     Write INT_MASK_class1 with value of 0.
1406          *     Write INT_MASK_class2 with value of 0.
1407          *     Write INT_STAT_class0 with value of -1.
1408          *     Write INT_STAT_class1 with value of -1.
1409          *     Write INT_STAT_class2 with value of -1.
1410          */
1411         spin_lock_irq(&spu->register_lock);
1412         spu_int_mask_set(spu, 0, 0ul);
1413         spu_int_mask_set(spu, 1, 0ul);
1414         spu_int_mask_set(spu, 2, 0ul);
1415         spu_int_stat_clear(spu, 0, ~0ul);
1416         spu_int_stat_clear(spu, 1, ~0ul);
1417         spu_int_stat_clear(spu, 2, ~0ul);
1418         spin_unlock_irq(&spu->register_lock);
1419 }
1420
1421 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1422 {
1423         struct spu_priv2 __iomem *priv2 = spu->priv2;
1424         int i;
1425
1426         /* Restore, Step 50:
1427          *     If MFC_Cntl[Se]!=0 then restore
1428          *     MFC command queues.
1429          */
1430         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1431                 for (i = 0; i < 8; i++) {
1432                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1433                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1434                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1435                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1436                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1437                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1438                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1439                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1440                 }
1441                 for (i = 0; i < 16; i++) {
1442                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1443                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1444                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1445                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1446                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1447                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1448                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1449                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1450                 }
1451         }
1452         eieio();
1453 }
1454
1455 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1456 {
1457         struct spu_problem __iomem *prob = spu->problem;
1458
1459         /* Restore, Step 51:
1460          *     Restore the PPU_QueryMask register from CSA.
1461          */
1462         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1463         eieio();
1464 }
1465
1466 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1467 {
1468         struct spu_problem __iomem *prob = spu->problem;
1469
1470         /* Restore, Step 52:
1471          *     Restore the PPU_QueryType register from CSA.
1472          */
1473         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1474         eieio();
1475 }
1476
1477 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1478 {
1479         struct spu_priv2 __iomem *priv2 = spu->priv2;
1480
1481         /* Restore, Step 53:
1482          *     Restore the MFC_CSR_TSQ register from CSA.
1483          */
1484         out_be64(&priv2->spu_tag_status_query_RW,
1485                  csa->priv2.spu_tag_status_query_RW);
1486         eieio();
1487 }
1488
1489 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1490 {
1491         struct spu_priv2 __iomem *priv2 = spu->priv2;
1492
1493         /* Restore, Step 54:
1494          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1495          *     registers from CSA.
1496          */
1497         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1498         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1499         eieio();
1500 }
1501
1502 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1503 {
1504         struct spu_priv2 __iomem *priv2 = spu->priv2;
1505
1506         /* Restore, Step 55:
1507          *     Restore the MFC_CSR_ATO register from CSA.
1508          */
1509         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1510 }
1511
1512 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1513 {
1514         /* Restore, Step 56:
1515          *     Restore the MFC_TCLASS_ID register from CSA.
1516          */
1517         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1518         eieio();
1519 }
1520
1521 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1522 {
1523         u64 ch0_cnt, ch0_data;
1524         u64 ch1_data;
1525
1526         /* Restore, Step 57:
1527          *    Set the Lock Line Reservation Lost Event by:
1528          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1529          *      2. If CSA.SPU_Channel_0_Count=0 and
1530          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1531          *         CSA.SPU_Event_Status[Lr]=0 then set
1532          *         CSA.SPU_Event_Status_Count=1.
1533          */
1534         ch0_cnt = csa->spu_chnlcnt_RW[0];
1535         ch0_data = csa->spu_chnldata_RW[0];
1536         ch1_data = csa->spu_chnldata_RW[1];
1537         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1538         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1539             (ch1_data & MFC_LLR_LOST_EVENT)) {
1540                 csa->spu_chnlcnt_RW[0] = 1;
1541         }
1542 }
1543
1544 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1545 {
1546         /* Restore, Step 58:
1547          *     If the status of the CSA software decrementer
1548          *     "wrapped" flag is set, OR in a '1' to
1549          *     CSA.SPU_Event_Status[Tm].
1550          */
1551         if (csa->lscsa->decr_status.slot[0] == 1) {
1552                 csa->spu_chnldata_RW[0] |= 0x20;
1553         }
1554         if ((csa->lscsa->decr_status.slot[0] == 1) &&
1555             (csa->spu_chnlcnt_RW[0] == 0 &&
1556              ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1557              ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1558                 csa->spu_chnlcnt_RW[0] = 1;
1559         }
1560 }
1561
1562 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1563 {
1564         struct spu_priv2 __iomem *priv2 = spu->priv2;
1565         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1566         int i;
1567
1568         /* Restore, Step 59:
1569          */
1570
1571         /* Restore CH 1 without count */
1572         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1573         out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1574
1575         /* Restore the following CH: [0,3,4,24,25,27] */
1576         for (i = 0; i < 7; i++) {
1577                 idx = ch_indices[i];
1578                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1579                 eieio();
1580                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1581                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1582                 eieio();
1583         }
1584 }
1585
1586 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1587 {
1588         struct spu_priv2 __iomem *priv2 = spu->priv2;
1589         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1590         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1591         u64 idx;
1592         int i;
1593
1594         /* Restore, Step 60:
1595          *     Restore the following CH: [9,21,23].
1596          */
1597         ch_counts[0] = 1UL;
1598         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1599         ch_counts[2] = 1UL;
1600         for (i = 0; i < 3; i++) {
1601                 idx = ch_indices[i];
1602                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1603                 eieio();
1604                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1605                 eieio();
1606         }
1607 }
1608
1609 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1610 {
1611         struct spu_priv2 __iomem *priv2 = spu->priv2;
1612
1613         /* Restore, Step 61:
1614          *     Restore the SPU_LSLR register from CSA.
1615          */
1616         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1617         eieio();
1618 }
1619
1620 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1621 {
1622         struct spu_priv2 __iomem *priv2 = spu->priv2;
1623
1624         /* Restore, Step 62:
1625          *     Restore the SPU_Cfg register from CSA.
1626          */
1627         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1628         eieio();
1629 }
1630
1631 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1632 {
1633         /* Restore, Step 63:
1634          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1635          *     Not performed by this implementation.
1636          */
1637 }
1638
1639 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1640 {
1641         struct spu_problem __iomem *prob = spu->problem;
1642
1643         /* Restore, Step 64:
1644          *     Restore SPU_NPC from CSA.
1645          */
1646         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1647         eieio();
1648 }
1649
1650 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1651 {
1652         struct spu_priv2 __iomem *priv2 = spu->priv2;
1653         int i;
1654
1655         /* Restore, Step 65:
1656          *     Restore MFC_RdSPU_MB from CSA.
1657          */
1658         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1659         eieio();
1660         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1661         for (i = 0; i < 4; i++) {
1662                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1663         }
1664         eieio();
1665 }
1666
1667 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1668 {
1669         struct spu_problem __iomem *prob = spu->problem;
1670         u32 dummy = 0;
1671
1672         /* Restore, Step 66:
1673          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1674          *     read from the PPU_MB register.
1675          */
1676         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1677                 dummy = in_be32(&prob->pu_mb_R);
1678                 eieio();
1679         }
1680 }
1681
1682 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1683 {
1684         struct spu_priv2 __iomem *priv2 = spu->priv2;
1685         u64 dummy = 0UL;
1686
1687         /* Restore, Step 66:
1688          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1689          *     read from the PPUINT_MB register.
1690          */
1691         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1692                 dummy = in_be64(&priv2->puint_mb_R);
1693                 eieio();
1694                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1695                 eieio();
1696         }
1697 }
1698
1699 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1700 {
1701         /* Restore, Step 69:
1702          *     Restore the MFC_SR1 register from CSA.
1703          */
1704         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1705         eieio();
1706 }
1707
1708 static inline void restore_other_spu_access(struct spu_state *csa,
1709                                             struct spu *spu)
1710 {
1711         /* Restore, Step 70:
1712          *     Restore other SPU mappings to this SPU. TBD.
1713          */
1714 }
1715
1716 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1717 {
1718         struct spu_problem __iomem *prob = spu->problem;
1719
1720         /* Restore, Step 71:
1721          *     If CSA.SPU_Status[R]=1 then write
1722          *     SPU_RunCntl[R0R1]='01'.
1723          */
1724         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1725                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1726                 eieio();
1727         }
1728 }
1729
1730 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1731 {
1732         struct spu_priv2 __iomem *priv2 = spu->priv2;
1733
1734         /* Restore, Step 72:
1735          *    Restore the MFC_CNTL register for the CSA.
1736          */
1737         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1738         eieio();
1739         /*
1740          * FIXME: this is to restart a DMA that we were processing
1741          *        before the save. better remember the fault information
1742          *        in the csa instead.
1743          */
1744         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1745                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1746                 eieio();
1747         }
1748 }
1749
1750 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1751 {
1752         /* Restore, Step 73:
1753          *     Enable user-space access (if provided) to this
1754          *     SPU by mapping the virtual pages assigned to
1755          *     the SPU memory-mapped I/O (MMIO) for problem
1756          *     state. TBD.
1757          */
1758 }
1759
1760 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1761 {
1762         /* Restore, Step 74:
1763          *     Reset the "context switch active" flag.
1764          */
1765         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1766         mb();
1767 }
1768
1769 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1770 {
1771         /* Restore, Step 75:
1772          *     Re-enable SPU interrupts.
1773          */
1774         spin_lock_irq(&spu->register_lock);
1775         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1776         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1777         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1778         spin_unlock_irq(&spu->register_lock);
1779 }
1780
1781 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1782 {
1783         /*
1784          * Combined steps 2-18 of SPU context save sequence, which
1785          * quiesce the SPU state (disable SPU execution, MFC command
1786          * queues, decrementer, SPU interrupts, etc.).
1787          *
1788          * Returns      0 on success.
1789          *              2 if failed step 2.
1790          *              6 if failed step 6.
1791          */
1792
1793         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1794                 return 2;
1795         }
1796         disable_interrupts(prev, spu);          /* Step 3. */
1797         set_watchdog_timer(prev, spu);          /* Step 4. */
1798         inhibit_user_access(prev, spu);         /* Step 5. */
1799         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1800                 return 6;
1801         }
1802         set_switch_pending(prev, spu);          /* Step 7. */
1803         save_mfc_cntl(prev, spu);               /* Step 8. */
1804         save_spu_runcntl(prev, spu);            /* Step 9. */
1805         save_mfc_sr1(prev, spu);                /* Step 10. */
1806         save_spu_status(prev, spu);             /* Step 11. */
1807         save_mfc_decr(prev, spu);               /* Step 12. */
1808         halt_mfc_decr(prev, spu);               /* Step 13. */
1809         save_timebase(prev, spu);               /* Step 14. */
1810         remove_other_spu_access(prev, spu);     /* Step 15. */
1811         do_mfc_mssync(prev, spu);               /* Step 16. */
1812         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1813         handle_pending_interrupts(prev, spu);   /* Step 18. */
1814
1815         return 0;
1816 }
1817
1818 static void save_csa(struct spu_state *prev, struct spu *spu)
1819 {
1820         /*
1821          * Combine steps 19-44 of SPU context save sequence, which
1822          * save regions of the privileged & problem state areas.
1823          */
1824
1825         save_mfc_queues(prev, spu);     /* Step 19. */
1826         save_ppu_querymask(prev, spu);  /* Step 20. */
1827         save_ppu_querytype(prev, spu);  /* Step 21. */
1828         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1829         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1830         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1831         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1832         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1833         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1834         purge_mfc_queue(prev, spu);     /* Step 27. */
1835         wait_purge_complete(prev, spu); /* Step 28. */
1836         setup_mfc_sr1(prev, spu);       /* Step 30. */
1837         save_spu_npc(prev, spu);        /* Step 31. */
1838         save_spu_privcntl(prev, spu);   /* Step 32. */
1839         reset_spu_privcntl(prev, spu);  /* Step 33. */
1840         save_spu_lslr(prev, spu);       /* Step 34. */
1841         reset_spu_lslr(prev, spu);      /* Step 35. */
1842         save_spu_cfg(prev, spu);        /* Step 36. */
1843         save_pm_trace(prev, spu);       /* Step 37. */
1844         save_mfc_rag(prev, spu);        /* Step 38. */
1845         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1846         save_ppu_mb(prev, spu);         /* Step 40. */
1847         save_ppuint_mb(prev, spu);      /* Step 41. */
1848         save_ch_part1(prev, spu);       /* Step 42. */
1849         save_spu_mb(prev, spu);         /* Step 43. */
1850         save_mfc_cmd(prev, spu);        /* Step 44. */
1851         reset_ch(prev, spu);            /* Step 45. */
1852 }
1853
1854 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1855 {
1856         /*
1857          * Perform steps 46-57 of SPU context save sequence,
1858          * which save regions of the local store and register
1859          * file.
1860          */
1861
1862         resume_mfc_queue(prev, spu);    /* Step 46. */
1863         setup_mfc_slbs(prev, spu);      /* Step 47. */
1864         set_switch_active(prev, spu);   /* Step 48. */
1865         enable_interrupts(prev, spu);   /* Step 49. */
1866         save_ls_16kb(prev, spu);        /* Step 50. */
1867         set_spu_npc(prev, spu);         /* Step 51. */
1868         set_signot1(prev, spu);         /* Step 52. */
1869         set_signot2(prev, spu);         /* Step 53. */
1870         send_save_code(prev, spu);      /* Step 54. */
1871         set_ppu_querymask(prev, spu);   /* Step 55. */
1872         wait_tag_complete(prev, spu);   /* Step 56. */
1873         wait_spu_stopped(prev, spu);    /* Step 57. */
1874 }
1875
1876 static void force_spu_isolate_exit(struct spu *spu)
1877 {
1878         struct spu_problem __iomem *prob = spu->problem;
1879         struct spu_priv2 __iomem *priv2 = spu->priv2;
1880
1881         /* Stop SPE execution and wait for completion. */
1882         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1883         iobarrier_rw();
1884         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1885
1886         /* Restart SPE master runcntl. */
1887         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1888         iobarrier_w();
1889
1890         /* Initiate isolate exit request and wait for completion. */
1891         out_be64(&priv2->spu_privcntl_RW, 4LL);
1892         iobarrier_w();
1893         out_be32(&prob->spu_runcntl_RW, 2);
1894         iobarrier_rw();
1895         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1896                                 & SPU_STATUS_STOPPED_BY_STOP));
1897
1898         /* Reset load request to normal. */
1899         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1900         iobarrier_w();
1901 }
1902
1903 /**
1904  * stop_spu_isolate
1905  *      Check SPU run-control state and force isolated
1906  *      exit function as necessary.
1907  */
1908 static void stop_spu_isolate(struct spu *spu)
1909 {
1910         struct spu_problem __iomem *prob = spu->problem;
1911
1912         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1913                 /* The SPU is in isolated state; the only way
1914                  * to get it out is to perform an isolated
1915                  * exit (clean) operation.
1916                  */
1917                 force_spu_isolate_exit(spu);
1918         }
1919 }
1920
1921 static void harvest(struct spu_state *prev, struct spu *spu)
1922 {
1923         /*
1924          * Perform steps 2-25 of SPU context restore sequence,
1925          * which resets an SPU either after a failed save, or
1926          * when using SPU for first time.
1927          */
1928
1929         disable_interrupts(prev, spu);          /* Step 2.  */
1930         inhibit_user_access(prev, spu);         /* Step 3.  */
1931         terminate_spu_app(prev, spu);           /* Step 4.  */
1932         set_switch_pending(prev, spu);          /* Step 5.  */
1933         stop_spu_isolate(spu);                  /* NEW.     */
1934         remove_other_spu_access(prev, spu);     /* Step 6.  */
1935         suspend_mfc(prev, spu);                 /* Step 7.  */
1936         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1937         if (!suspend_spe(prev, spu))            /* Step 9.  */
1938                 clear_spu_status(prev, spu);    /* Step 10. */
1939         do_mfc_mssync(prev, spu);               /* Step 11. */
1940         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1941         handle_pending_interrupts(prev, spu);   /* Step 13. */
1942         purge_mfc_queue(prev, spu);             /* Step 14. */
1943         wait_purge_complete(prev, spu);         /* Step 15. */
1944         reset_spu_privcntl(prev, spu);          /* Step 16. */
1945         reset_spu_lslr(prev, spu);              /* Step 17. */
1946         setup_mfc_sr1(prev, spu);               /* Step 18. */
1947         spu_invalidate_slbs(spu);               /* Step 19. */
1948         reset_ch_part1(prev, spu);              /* Step 20. */
1949         reset_ch_part2(prev, spu);              /* Step 21. */
1950         enable_interrupts(prev, spu);           /* Step 22. */
1951         set_switch_active(prev, spu);           /* Step 23. */
1952         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1953         resume_mfc_queue(prev, spu);            /* Step 25. */
1954 }
1955
1956 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1957 {
1958         /*
1959          * Perform steps 26-40 of SPU context restore sequence,
1960          * which restores regions of the local store and register
1961          * file.
1962          */
1963
1964         set_watchdog_timer(next, spu);          /* Step 26. */
1965         setup_spu_status_part1(next, spu);      /* Step 27. */
1966         setup_spu_status_part2(next, spu);      /* Step 28. */
1967         restore_mfc_rag(next, spu);             /* Step 29. */
1968         setup_mfc_slbs(next, spu);              /* Step 30. */
1969         set_spu_npc(next, spu);                 /* Step 31. */
1970         set_signot1(next, spu);                 /* Step 32. */
1971         set_signot2(next, spu);                 /* Step 33. */
1972         setup_decr(next, spu);                  /* Step 34. */
1973         setup_ppu_mb(next, spu);                /* Step 35. */
1974         setup_ppuint_mb(next, spu);             /* Step 36. */
1975         send_restore_code(next, spu);           /* Step 37. */
1976         set_ppu_querymask(next, spu);           /* Step 38. */
1977         wait_tag_complete(next, spu);           /* Step 39. */
1978         wait_spu_stopped(next, spu);            /* Step 40. */
1979 }
1980
1981 static void restore_csa(struct spu_state *next, struct spu *spu)
1982 {
1983         /*
1984          * Combine steps 41-76 of SPU context restore sequence, which
1985          * restore regions of the privileged & problem state areas.
1986          */
1987
1988         restore_spu_privcntl(next, spu);        /* Step 41. */
1989         restore_status_part1(next, spu);        /* Step 42. */
1990         restore_status_part2(next, spu);        /* Step 43. */
1991         restore_ls_16kb(next, spu);             /* Step 44. */
1992         wait_tag_complete(next, spu);           /* Step 45. */
1993         suspend_mfc(next, spu);                 /* Step 46. */
1994         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1995         issue_mfc_tlbie(next, spu);             /* Step 48. */
1996         clear_interrupts(next, spu);            /* Step 49. */
1997         restore_mfc_queues(next, spu);          /* Step 50. */
1998         restore_ppu_querymask(next, spu);       /* Step 51. */
1999         restore_ppu_querytype(next, spu);       /* Step 52. */
2000         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
2001         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
2002         restore_mfc_csr_ato(next, spu);         /* Step 55. */
2003         restore_mfc_tclass_id(next, spu);       /* Step 56. */
2004         set_llr_event(next, spu);               /* Step 57. */
2005         restore_decr_wrapped(next, spu);        /* Step 58. */
2006         restore_ch_part1(next, spu);            /* Step 59. */
2007         restore_ch_part2(next, spu);            /* Step 60. */
2008         restore_spu_lslr(next, spu);            /* Step 61. */
2009         restore_spu_cfg(next, spu);             /* Step 62. */
2010         restore_pm_trace(next, spu);            /* Step 63. */
2011         restore_spu_npc(next, spu);             /* Step 64. */
2012         restore_spu_mb(next, spu);              /* Step 65. */
2013         check_ppu_mb_stat(next, spu);           /* Step 66. */
2014         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2015         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2016         restore_mfc_sr1(next, spu);             /* Step 69. */
2017         restore_other_spu_access(next, spu);    /* Step 70. */
2018         restore_spu_runcntl(next, spu);         /* Step 71. */
2019         restore_mfc_cntl(next, spu);            /* Step 72. */
2020         enable_user_access(next, spu);          /* Step 73. */
2021         reset_switch_active(next, spu);         /* Step 74. */
2022         reenable_interrupts(next, spu);         /* Step 75. */
2023 }
2024
2025 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2026 {
2027         int rc;
2028
2029         /*
2030          * SPU context save can be broken into three phases:
2031          *
2032          *     (a) quiesce [steps 2-16].
2033          *     (b) save of CSA, performed by PPE [steps 17-42]
2034          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2035          *
2036          * Returns      0 on success.
2037          *              2,6 if failed to quiece SPU
2038          *              53 if SPU-side of save failed.
2039          */
2040
2041         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2042         switch (rc) {
2043         default:
2044         case 2:
2045         case 6:
2046                 harvest(prev, spu);
2047                 return rc;
2048                 break;
2049         case 0:
2050                 break;
2051         }
2052         save_csa(prev, spu);                    /* Steps 17-43. */
2053         save_lscsa(prev, spu);                  /* Steps 44-53. */
2054         return check_save_status(prev, spu);    /* Step 54.     */
2055 }
2056
2057 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2058 {
2059         int rc;
2060
2061         /*
2062          * SPU context restore can be broken into three phases:
2063          *
2064          *    (a) harvest (or reset) SPU [steps 2-24].
2065          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2066          *    (c) restore CSA [steps 41-76], performed by PPE.
2067          *
2068          * The 'harvest' step is not performed here, but rather
2069          * as needed below.
2070          */
2071
2072         restore_lscsa(next, spu);               /* Steps 24-39. */
2073         rc = check_restore_status(next, spu);   /* Step 40.     */
2074         switch (rc) {
2075         default:
2076                 /* Failed. Return now. */
2077                 return rc;
2078                 break;
2079         case 0:
2080                 /* Fall through to next step. */
2081                 break;
2082         }
2083         restore_csa(next, spu);
2084
2085         return 0;
2086 }
2087
2088 /**
2089  * spu_save - SPU context save, with locking.
2090  * @prev: pointer to SPU context save area, to be saved.
2091  * @spu: pointer to SPU iomem structure.
2092  *
2093  * Acquire locks, perform the save operation then return.
2094  */
2095 int spu_save(struct spu_state *prev, struct spu *spu)
2096 {
2097         int rc;
2098
2099         acquire_spu_lock(spu);          /* Step 1.     */
2100         prev->dar = spu->dar;
2101         prev->dsisr = spu->dsisr;
2102         spu->dar = 0;
2103         spu->dsisr = 0;
2104         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2105         release_spu_lock(spu);
2106         if (rc != 0 && rc != 2 && rc != 6) {
2107                 panic("%s failed on SPU[%d], rc=%d.\n",
2108                       __func__, spu->number, rc);
2109         }
2110         return 0;
2111 }
2112 EXPORT_SYMBOL_GPL(spu_save);
2113
2114 /**
2115  * spu_restore - SPU context restore, with harvest and locking.
2116  * @new: pointer to SPU context save area, to be restored.
2117  * @spu: pointer to SPU iomem structure.
2118  *
2119  * Perform harvest + restore, as we may not be coming
2120  * from a previous successful save operation, and the
2121  * hardware state is unknown.
2122  */
2123 int spu_restore(struct spu_state *new, struct spu *spu)
2124 {
2125         int rc;
2126
2127         acquire_spu_lock(spu);
2128         harvest(NULL, spu);
2129         spu->slb_replace = 0;
2130         new->dar = 0;
2131         new->dsisr = 0;
2132         spu->class_0_pending = 0;
2133         rc = __do_spu_restore(new, spu);
2134         release_spu_lock(spu);
2135         if (rc) {
2136                 panic("%s failed on SPU[%d] rc=%d.\n",
2137                        __func__, spu->number, rc);
2138         }
2139         return rc;
2140 }
2141 EXPORT_SYMBOL_GPL(spu_restore);
2142
2143 /**
2144  * spu_harvest - SPU harvest (reset) operation
2145  * @spu: pointer to SPU iomem structure.
2146  *
2147  * Perform SPU harvest (reset) operation.
2148  */
2149 void spu_harvest(struct spu *spu)
2150 {
2151         acquire_spu_lock(spu);
2152         harvest(NULL, spu);
2153         release_spu_lock(spu);
2154 }
2155
2156 static void init_prob(struct spu_state *csa)
2157 {
2158         csa->spu_chnlcnt_RW[9] = 1;
2159         csa->spu_chnlcnt_RW[21] = 16;
2160         csa->spu_chnlcnt_RW[23] = 1;
2161         csa->spu_chnlcnt_RW[28] = 1;
2162         csa->spu_chnlcnt_RW[30] = 1;
2163         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2164         csa->prob.mb_stat_R = 0x000400;
2165 }
2166
2167 static void init_priv1(struct spu_state *csa)
2168 {
2169         /* Enable decode, relocate, tlbie response, master runcntl. */
2170         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2171             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2172             MFC_STATE1_PROBLEM_STATE_MASK |
2173             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2174
2175         /* Enable OS-specific set of interrupts. */
2176         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2177             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2178             CLASS0_ENABLE_SPU_ERROR_INTR;
2179         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2180             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2181         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2182             CLASS2_ENABLE_SPU_HALT_INTR |
2183             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2184 }
2185
2186 static void init_priv2(struct spu_state *csa)
2187 {
2188         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2189         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2190             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2191             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2192 }
2193
2194 /**
2195  * spu_alloc_csa - allocate and initialize an SPU context save area.
2196  *
2197  * Allocate and initialize the contents of an SPU context save area.
2198  * This includes enabling address translation, interrupt masks, etc.,
2199  * as appropriate for the given OS environment.
2200  *
2201  * Note that storage for the 'lscsa' is allocated separately,
2202  * as it is by far the largest of the context save regions,
2203  * and may need to be pinned or otherwise specially aligned.
2204  */
2205 int spu_init_csa(struct spu_state *csa)
2206 {
2207         int rc;
2208
2209         if (!csa)
2210                 return -EINVAL;
2211         memset(csa, 0, sizeof(struct spu_state));
2212
2213         rc = spu_alloc_lscsa(csa);
2214         if (rc)
2215                 return rc;
2216
2217         spin_lock_init(&csa->register_lock);
2218
2219         init_prob(csa);
2220         init_priv1(csa);
2221         init_priv2(csa);
2222
2223         return 0;
2224 }
2225 EXPORT_SYMBOL_GPL(spu_init_csa);
2226
2227 void spu_fini_csa(struct spu_state *csa)
2228 {
2229         spu_free_lscsa(csa);
2230 }
2231 EXPORT_SYMBOL_GPL(spu_fini_csa);