2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <linux/types.h>
14 #include <linux/threads.h>
15 #include <linux/kernel.h>
16 #include <linux/irq.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/signal.h>
20 #include <linux/init.h>
21 #include <linux/gfp.h>
22 #include <linux/radix-tree.h>
23 #include <linux/cpu.h>
25 #include <asm/firmware.h>
28 #include <asm/pgtable.h>
31 #include <asm/hvcall.h>
32 #include <asm/machdep.h>
33 #include <asm/i8259.h>
36 #include "plpar_wrappers.h"
39 #define XICS_IRQ_SPURIOUS 0
41 /* Want a priority other than 0. Various HW issues require this. */
42 #define DEFAULT_PRIORITY 5
45 * Mark IPIs as higher priority so we can take them inside interrupts that
46 * arent marked IRQF_DISABLED
48 #define IPI_PRIORITY 4
66 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
68 static unsigned int default_server = 0xFF;
69 static unsigned int default_distrib_server = 0;
70 static unsigned int interrupt_server_size = 8;
72 static struct irq_host *xics_host;
75 * XICS only has a single IPI, so encode the messages per CPU
77 struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
79 /* RTAS service tokens */
80 static int ibm_get_xive;
81 static int ibm_set_xive;
82 static int ibm_int_on;
83 static int ibm_int_off;
86 /* Direct HW low level accessors */
89 static inline unsigned int direct_xirr_info_get(void)
91 int cpu = smp_processor_id();
93 return in_be32(&xics_per_cpu[cpu]->xirr.word);
96 static inline void direct_xirr_info_set(int value)
98 int cpu = smp_processor_id();
100 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
103 static inline void direct_cppr_info(u8 value)
105 int cpu = smp_processor_id();
107 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
110 static inline void direct_qirr_info(int n_cpu, u8 value)
112 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
116 /* LPAR low level accessors */
119 static inline unsigned int lpar_xirr_info_get(void)
121 unsigned long lpar_rc;
122 unsigned long return_value;
124 lpar_rc = plpar_xirr(&return_value);
125 if (lpar_rc != H_SUCCESS)
126 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
127 return (unsigned int)return_value;
130 static inline void lpar_xirr_info_set(int value)
132 unsigned long lpar_rc;
133 unsigned long val64 = value & 0xffffffff;
135 lpar_rc = plpar_eoi(val64);
136 if (lpar_rc != H_SUCCESS)
137 panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
141 static inline void lpar_cppr_info(u8 value)
143 unsigned long lpar_rc;
145 lpar_rc = plpar_cppr(value);
146 if (lpar_rc != H_SUCCESS)
147 panic("bad return code cppr - rc = %lx\n", lpar_rc);
150 static inline void lpar_qirr_info(int n_cpu , u8 value)
152 unsigned long lpar_rc;
154 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
155 if (lpar_rc != H_SUCCESS)
156 panic("bad return code qirr - rc = %lx\n", lpar_rc);
160 /* High level handlers and init code */
162 static void xics_update_irq_servers(void)
165 struct device_node *np;
167 const u32 *ireg, *isize;
170 /* Find the server numbers for the boot cpu. */
171 np = of_get_cpu_node(boot_cpuid, NULL);
174 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
180 i = ilen / sizeof(int);
181 hcpuid = get_hard_smp_processor_id(boot_cpuid);
183 /* Global interrupt distribution server is specified in the last
184 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
185 * entry fom this property for current boot cpu id and use it as
186 * default distribution server
188 for (j = 0; j < i; j += 2) {
189 if (ireg[j] == hcpuid) {
190 default_server = hcpuid;
191 default_distrib_server = ireg[j+1];
193 isize = of_get_property(np,
194 "ibm,interrupt-server#-size", NULL);
196 interrupt_server_size = *isize;
204 static int get_irq_server(unsigned int virq, unsigned int strict_check)
207 /* For the moment only implement delivery to all cpus or one cpu */
208 cpumask_t cpumask = irq_desc[virq].affinity;
209 cpumask_t tmp = CPU_MASK_NONE;
211 if (! cpu_isset(default_server, cpu_online_map))
212 xics_update_irq_servers();
214 if (!distribute_irqs)
215 return default_server;
217 if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
218 cpus_and(tmp, cpu_online_map, cpumask);
220 server = first_cpu(tmp);
222 if (server < NR_CPUS)
223 return get_hard_smp_processor_id(server);
229 if (cpus_equal(cpu_online_map, cpu_present_map))
230 return default_distrib_server;
232 return default_server;
235 static int get_irq_server(unsigned int virq, unsigned int strict_check)
237 return default_server;
242 static void xics_unmask_irq(unsigned int virq)
248 pr_debug("xics: unmask virq %d\n", virq);
250 irq = (unsigned int)irq_map[virq].hwirq;
251 pr_debug(" -> map to hwirq 0x%x\n", irq);
252 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
255 server = get_irq_server(virq, 0);
257 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
259 if (call_status != 0) {
260 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
261 "returned %d\n", irq, call_status);
262 printk("set_xive %x, server %x\n", ibm_set_xive, server);
266 /* Now unmask the interrupt (often a no-op) */
267 call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
268 if (call_status != 0) {
269 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
270 "returned %d\n", irq, call_status);
275 static void xics_mask_real_irq(unsigned int irq)
282 call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
283 if (call_status != 0) {
284 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
285 "ibm_int_off returned %d\n", irq, call_status);
289 /* Have to set XIVE to 0xff to be able to remove a slot */
290 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
291 default_server, 0xff);
292 if (call_status != 0) {
293 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
294 " returned %d\n", irq, call_status);
299 static void xics_mask_irq(unsigned int virq)
303 pr_debug("xics: mask virq %d\n", virq);
305 irq = (unsigned int)irq_map[virq].hwirq;
306 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
308 xics_mask_real_irq(irq);
311 static unsigned int xics_startup(unsigned int virq)
314 xics_unmask_irq(virq);
318 static void xics_eoi_direct(unsigned int virq)
320 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
323 direct_xirr_info_set((0xff << 24) | irq);
327 static void xics_eoi_lpar(unsigned int virq)
329 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
332 lpar_xirr_info_set((0xff << 24) | irq);
335 static inline unsigned int xics_remap_irq(unsigned int vec)
341 if (vec == XICS_IRQ_SPURIOUS)
343 irq = irq_radix_revmap_lookup(xics_host, vec);
344 if (likely(irq != NO_IRQ))
347 printk(KERN_ERR "Interrupt %u (real) is invalid,"
348 " disabling it.\n", vec);
349 xics_mask_real_irq(vec);
353 static unsigned int xics_get_irq_direct(void)
355 return xics_remap_irq(direct_xirr_info_get());
358 static unsigned int xics_get_irq_lpar(void)
360 return xics_remap_irq(lpar_xirr_info_get());
365 static irqreturn_t xics_ipi_dispatch(int cpu)
367 WARN_ON(cpu_is_offline(cpu));
369 while (xics_ipi_message[cpu].value) {
370 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
371 &xics_ipi_message[cpu].value)) {
373 smp_message_recv(PPC_MSG_CALL_FUNCTION);
375 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
376 &xics_ipi_message[cpu].value)) {
378 smp_message_recv(PPC_MSG_RESCHEDULE);
380 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
381 &xics_ipi_message[cpu].value)) {
383 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
385 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
386 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
387 &xics_ipi_message[cpu].value)) {
389 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
396 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
398 int cpu = smp_processor_id();
400 direct_qirr_info(cpu, 0xff);
402 return xics_ipi_dispatch(cpu);
405 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
407 int cpu = smp_processor_id();
409 lpar_qirr_info(cpu, 0xff);
411 return xics_ipi_dispatch(cpu);
414 void xics_cause_IPI(int cpu)
416 if (firmware_has_feature(FW_FEATURE_LPAR))
417 lpar_qirr_info(cpu, IPI_PRIORITY);
419 direct_qirr_info(cpu, IPI_PRIORITY);
422 #endif /* CONFIG_SMP */
424 static void xics_set_cpu_priority(unsigned char cppr)
426 if (firmware_has_feature(FW_FEATURE_LPAR))
427 lpar_cppr_info(cppr);
429 direct_cppr_info(cppr);
433 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
440 irq = (unsigned int)irq_map[virq].hwirq;
441 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
444 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
447 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
448 "returns %d\n", irq, status);
453 * For the moment only implement delivery to all cpus or one cpu.
454 * Get current irq_server for the given irq
456 irq_server = get_irq_server(virq, 1);
457 if (irq_server == -1) {
459 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
460 printk(KERN_WARNING "xics_set_affinity: No online cpus in "
461 "the mask %s for irq %d\n", cpulist, virq);
465 status = rtas_call(ibm_set_xive, 3, 1, NULL,
466 irq, irq_server, xics_status[1]);
469 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
470 "returns %d\n", irq, status);
475 void xics_setup_cpu(void)
477 xics_set_cpu_priority(0xff);
480 * Put the calling processor into the GIQ. This is really only
481 * necessary from a secondary thread as the OF start-cpu interface
482 * performs this function for us on primary threads.
484 * XXX: undo of teardown on kexec needs this too, as may hotplug
486 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
487 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
491 static struct irq_chip xics_pic_direct = {
492 .typename = " XICS ",
493 .startup = xics_startup,
494 .mask = xics_mask_irq,
495 .unmask = xics_unmask_irq,
496 .eoi = xics_eoi_direct,
497 .set_affinity = xics_set_affinity
501 static struct irq_chip xics_pic_lpar = {
502 .typename = " XICS ",
503 .startup = xics_startup,
504 .mask = xics_mask_irq,
505 .unmask = xics_unmask_irq,
506 .eoi = xics_eoi_lpar,
507 .set_affinity = xics_set_affinity
510 /* Points to the irq_chip we're actually using */
511 static struct irq_chip *xics_irq_chip;
513 static int xics_host_match(struct irq_host *h, struct device_node *node)
515 /* IBM machines have interrupt parents of various funky types for things
516 * like vdevices, events, etc... The trick we use here is to match
517 * everything here except the legacy 8259 which is compatible "chrp,iic"
519 return !of_device_is_compatible(node, "chrp,iic");
522 static int xics_host_map(struct irq_host *h, unsigned int virq,
525 pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
527 /* Insert the interrupt mapping into the radix tree for fast lookup */
528 irq_radix_revmap_insert(xics_host, virq, hw);
530 get_irq_desc(virq)->status |= IRQ_LEVEL;
531 set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
535 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
536 u32 *intspec, unsigned int intsize,
537 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
540 /* Current xics implementation translates everything
541 * to level. It is not technically right for MSIs but this
542 * is irrelevant at this point. We might get smarter in the future
544 *out_hwirq = intspec[0];
545 *out_flags = IRQ_TYPE_LEVEL_LOW;
550 static struct irq_host_ops xics_host_ops = {
551 .match = xics_host_match,
552 .map = xics_host_map,
553 .xlate = xics_host_xlate,
556 static void __init xics_init_host(void)
558 if (firmware_has_feature(FW_FEATURE_LPAR))
559 xics_irq_chip = &xics_pic_lpar;
561 xics_irq_chip = &xics_pic_direct;
563 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
565 BUG_ON(xics_host == NULL);
566 irq_set_default_host(xics_host);
569 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
575 /* This may look gross but it's good enough for now, we don't quite
576 * have a hard -> linux processor id matching.
578 for_each_possible_cpu(i) {
581 if (hw_id == get_hard_smp_processor_id(i)) {
582 xics_per_cpu[i] = ioremap(addr, size);
589 xics_per_cpu[0] = ioremap(addr, size);
590 #endif /* CONFIG_SMP */
593 static void __init xics_init_one_node(struct device_node *np,
599 /* This code does the theorically broken assumption that the interrupt
600 * server numbers are the same as the hard CPU numbers.
601 * This happens to be the case so far but we are playing with fire...
602 * should be fixed one of these days. -BenH.
604 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
606 /* Do that ever happen ? we'll know soon enough... but even good'old
607 * f80 does have that property ..
609 WARN_ON(ireg == NULL);
612 * set node starting index for this node
616 ireg = of_get_property(np, "reg", &ilen);
618 panic("xics_init_IRQ: can't find interrupt reg property");
620 while (ilen >= (4 * sizeof(u32))) {
621 unsigned long addr, size;
623 /* XXX Use proper OF parsing code here !!! */
624 addr = (unsigned long)*ireg++ << 32;
628 size = (unsigned long)*ireg++ << 32;
632 xics_map_one_cpu(*indx, addr, size);
637 void __init xics_init_IRQ(void)
639 struct device_node *np;
643 ppc64_boot_msg(0x20, "XICS Init");
645 ibm_get_xive = rtas_token("ibm,get-xive");
646 ibm_set_xive = rtas_token("ibm,set-xive");
647 ibm_int_on = rtas_token("ibm,int-on");
648 ibm_int_off = rtas_token("ibm,int-off");
650 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
652 if (firmware_has_feature(FW_FEATURE_LPAR))
654 xics_init_one_node(np, &indx);
660 xics_update_irq_servers();
662 if (firmware_has_feature(FW_FEATURE_LPAR))
663 ppc_md.get_irq = xics_get_irq_lpar;
665 ppc_md.get_irq = xics_get_irq_direct;
669 ppc64_boot_msg(0x21, "XICS Done");
674 void xics_request_IPIs(void)
679 ipi = irq_create_mapping(xics_host, XICS_IPI);
680 BUG_ON(ipi == NO_IRQ);
683 * IPIs are marked IRQF_DISABLED as they must run with irqs
686 set_irq_handler(ipi, handle_percpu_irq);
687 if (firmware_has_feature(FW_FEATURE_LPAR))
688 rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
691 rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
695 #endif /* CONFIG_SMP */
697 void xics_teardown_cpu(void)
699 int cpu = smp_processor_id();
701 xics_set_cpu_priority(0);
706 if (firmware_has_feature(FW_FEATURE_LPAR))
707 lpar_qirr_info(cpu, 0xff);
709 direct_qirr_info(cpu, 0xff);
712 void xics_kexec_teardown_cpu(int secondary)
715 struct irq_desc *desc;
720 * we need to EOI the IPI
722 * probably need to check all the other interrupts too
723 * should we be flagging idle loop instead?
724 * or creating some task to be scheduled?
727 ipi = irq_find_mapping(xics_host, XICS_IPI);
728 if (ipi == XICS_IRQ_SPURIOUS)
730 desc = get_irq_desc(ipi);
731 if (desc->chip && desc->chip->eoi)
732 desc->chip->eoi(ipi);
735 * Some machines need to have at least one cpu in the GIQ,
736 * so leave the master cpu in the group.
739 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
740 (1UL << interrupt_server_size) - 1 -
741 default_distrib_server, 0);
744 #ifdef CONFIG_HOTPLUG_CPU
746 /* Interrupts are disabled. */
747 void xics_migrate_irqs_away(void)
750 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
751 unsigned int irq, virq;
753 /* Reject any interrupt that was queued to us... */
754 xics_set_cpu_priority(0);
756 /* remove ourselves from the global interrupt queue */
757 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
758 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
761 /* Allow IPIs again... */
762 xics_set_cpu_priority(DEFAULT_PRIORITY);
765 struct irq_desc *desc;
769 /* We cant set affinity on ISA interrupts */
770 if (virq < NUM_ISA_INTERRUPTS)
772 if (irq_map[virq].host != xics_host)
774 irq = (unsigned int)irq_map[virq].hwirq;
775 /* We need to get IPIs still. */
776 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
778 desc = get_irq_desc(virq);
780 /* We only need to migrate enabled IRQS */
781 if (desc == NULL || desc->chip == NULL
782 || desc->action == NULL
783 || desc->chip->set_affinity == NULL)
786 spin_lock_irqsave(&desc->lock, flags);
788 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
790 printk(KERN_ERR "migrate_irqs_away: irq=%u "
791 "ibm,get-xive returns %d\n",
797 * We only support delivery to all cpus or to one cpu.
798 * The irq has to be migrated only in the single cpu
801 if (xics_status[0] != hw_cpu)
804 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
807 /* Reset affinity to all cpus */
808 irq_desc[virq].affinity = CPU_MASK_ALL;
809 desc->chip->set_affinity(virq, CPU_MASK_ALL);
811 spin_unlock_irqrestore(&desc->lock, flags);