2 * General Purpose functions for the global management of the
3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
5 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
8 * 2006 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
19 * In addition to the individual control of the communication
20 * channels, there are a few functions that globally affect the
21 * communication processor.
23 * Buffer descriptors must be allocated from the dual ported memory
24 * space. The allocator for that is here. When the communication
25 * process is reset, we reclaim the memory available. There is
26 * currently no deallocator for this memory.
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/kernel.h>
31 #include <linux/param.h>
32 #include <linux/string.h>
34 #include <linux/interrupt.h>
35 #include <linux/module.h>
40 #include <asm/mpc8260.h>
42 #include <asm/pgtable.h>
44 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
47 #include <sysdev/fsl_soc.h>
49 static void cpm2_dpinit(void);
50 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
52 /* We allocate this here because it is used almost exclusively for
53 * the communication processor devices.
55 cpm2_map_t __iomem *cpm2_immr;
57 #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
58 of space for CPM as it is larger
64 #ifdef CONFIG_PPC_85xx
65 cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
67 cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
70 /* Reclaim the DP memory for our use.
74 /* Tell everyone where the comm processor resides.
76 cpmp = &cpm2_immr->im_cpm;
79 /* Set a baud rate generator. This needs lots of work. There are
80 * eight BRGs, which can be connected to the CPM channels or output
81 * as clocks. The BRGs are in two different block of internal
82 * memory mapped space.
83 * The baud rate clock is the system clock divided by something.
84 * It was set up long ago during the initial boot phase and is
86 * Baud rate clocks are zero-based in the driver code (as that maps
87 * to port numbers). Documentation uses 1-based numbering.
89 #define BRG_INT_CLK (get_brgfreq())
90 #define BRG_UART_CLK (BRG_INT_CLK/16)
92 /* This function is used by UARTS, or anything else that uses a 16x
96 cpm_setbrg(uint brg, uint rate)
100 /* This is good enough to get SMCs running.....
103 bp = cpm2_map_size(im_brgc1, 16);
105 bp = cpm2_map_size(im_brgc5, 16);
109 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
114 /* This function is used to set high speed synchronous baud rate
118 cpm2_fastbrg(uint brg, uint rate, int div16)
124 bp = cpm2_map_size(im_brgc1, 16);
127 bp = cpm2_map_size(im_brgc5, 16);
131 val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
133 val |= CPM_BRG_DIV16;
139 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
144 cpmux_t __iomem *im_cpmux;
147 u8 clk_map [24][3] = {
148 {CPM_CLK_FCC1, CPM_BRG5, 0},
149 {CPM_CLK_FCC1, CPM_BRG6, 1},
150 {CPM_CLK_FCC1, CPM_BRG7, 2},
151 {CPM_CLK_FCC1, CPM_BRG8, 3},
152 {CPM_CLK_FCC1, CPM_CLK9, 4},
153 {CPM_CLK_FCC1, CPM_CLK10, 5},
154 {CPM_CLK_FCC1, CPM_CLK11, 6},
155 {CPM_CLK_FCC1, CPM_CLK12, 7},
156 {CPM_CLK_FCC2, CPM_BRG5, 0},
157 {CPM_CLK_FCC2, CPM_BRG6, 1},
158 {CPM_CLK_FCC2, CPM_BRG7, 2},
159 {CPM_CLK_FCC2, CPM_BRG8, 3},
160 {CPM_CLK_FCC2, CPM_CLK13, 4},
161 {CPM_CLK_FCC2, CPM_CLK14, 5},
162 {CPM_CLK_FCC2, CPM_CLK15, 6},
163 {CPM_CLK_FCC2, CPM_CLK16, 7},
164 {CPM_CLK_FCC3, CPM_BRG5, 0},
165 {CPM_CLK_FCC3, CPM_BRG6, 1},
166 {CPM_CLK_FCC3, CPM_BRG7, 2},
167 {CPM_CLK_FCC3, CPM_BRG8, 3},
168 {CPM_CLK_FCC3, CPM_CLK13, 4},
169 {CPM_CLK_FCC3, CPM_CLK14, 5},
170 {CPM_CLK_FCC3, CPM_CLK15, 6},
171 {CPM_CLK_FCC3, CPM_CLK16, 7}
174 im_cpmux = cpm2_map(im_cpmux);
178 reg = &im_cpmux->cmx_scr;
181 reg = &im_cpmux->cmx_scr;
185 reg = &im_cpmux->cmx_scr;
189 reg = &im_cpmux->cmx_scr;
193 reg = &im_cpmux->cmx_fcr;
197 reg = &im_cpmux->cmx_fcr;
201 reg = &im_cpmux->cmx_fcr;
205 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
209 if (mode == CPM_CLK_RX)
212 for (i=0; i<24; i++) {
213 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
214 bits = clk_map[i][2];
218 if (i == sizeof(clk_map)/3)
223 out_be32(reg, (in_be32(reg) & ~mask) | bits);
225 cpm2_unmap(im_cpmux);
230 * dpalloc / dpfree bits.
232 static spinlock_t cpm_dpmem_lock;
233 /* 16 blocks should be enough to satisfy all requests
234 * until the memory subsystem goes up... */
235 static rh_block_t cpm_boot_dpmem_rh_block[16];
236 static rh_info_t cpm_dpmem_info;
237 static u8 __iomem *im_dprambase;
239 static void cpm2_dpinit(void)
243 #ifdef CONFIG_PPC_CPM_NEW_BINDING
244 struct device_node *np;
246 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
248 panic("Cannot find CPM2 node");
250 if (of_address_to_resource(np, 1, &r))
251 panic("Cannot get CPM2 resource 1");
255 r.start = CPM_MAP_ADDR;
256 r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1;
259 im_dprambase = ioremap(r.start, r.end - r.start + 1);
261 panic("Cannot map DPRAM");
263 spin_lock_init(&cpm_dpmem_lock);
265 /* initialize the info header */
266 rh_init(&cpm_dpmem_info, 1,
267 sizeof(cpm_boot_dpmem_rh_block) /
268 sizeof(cpm_boot_dpmem_rh_block[0]),
269 cpm_boot_dpmem_rh_block);
271 /* Attach the usable dpmem area */
272 /* XXX: This is actually crap. CPM_DATAONLY_BASE and
273 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
274 * varies with the processor and the microcode patches activated.
275 * But the following should be at least safe.
277 rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1);
280 /* This function returns an index into the DPRAM area.
282 unsigned long cpm_dpalloc(uint size, uint align)
287 spin_lock_irqsave(&cpm_dpmem_lock, flags);
288 cpm_dpmem_info.alignment = align;
289 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
290 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
294 EXPORT_SYMBOL(cpm_dpalloc);
296 int cpm_dpfree(unsigned long offset)
301 spin_lock_irqsave(&cpm_dpmem_lock, flags);
302 ret = rh_free(&cpm_dpmem_info, offset);
303 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
307 EXPORT_SYMBOL(cpm_dpfree);
309 /* not sure if this is ever needed */
310 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
315 spin_lock_irqsave(&cpm_dpmem_lock, flags);
316 cpm_dpmem_info.alignment = align;
317 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
318 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
322 EXPORT_SYMBOL(cpm_dpalloc_fixed);
324 void cpm_dpdump(void)
326 rh_dump(&cpm_dpmem_info);
328 EXPORT_SYMBOL(cpm_dpdump);
330 void *cpm_dpram_addr(unsigned long offset)
332 return (void *)(im_dprambase + offset);
334 EXPORT_SYMBOL(cpm_dpram_addr);