arch/powerpc/sysdev/cpm2_common.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * 8260 Communication Processor Module.
   4  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
   5  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
   6  *      2.3.99 Updates
   7  *
   8  * 2006 (c) MontaVista Software, Inc.
   9  * Vitaly Bordug <vbordug@ru.mvista.com>
  10  *      Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /*
  18  *
  19  * In addition to the individual control of the communication
  20  * channels, there are a few functions that globally affect the
  21  * communication processor.
  22  *
  23  * Buffer descriptors must be allocated from the dual ported memory
  24  * space.  The allocator for that is here.  When the communication
  25  * process is reset, we reclaim the memory available.  There is
  26  * currently no deallocator for this memory.
  27  */
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/kernel.h>
  31 #include <linux/param.h>
  32 #include <linux/string.h>
  33 #include <linux/mm.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/module.h>
  36 #include <linux/of.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/mpc8260.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/cpm2.h>
  44 #include <asm/rheap.h>
  45 #include <asm/fs_pd.h>
  46
  47 #include <sysdev/fsl_soc.h>
  48
  49 static void cpm2_dpinit(void);
  50 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
  51
  52 /* We allocate this here because it is used almost exclusively for
  53  * the communication processor devices.
  54  */
  55 cpm2_map_t __iomem *cpm2_immr;
  56
  57 #define CPM_MAP_SIZE    (0x40000)       /* 256k - the PQ3 reserve this amount
  58                                            of space for CPM as it is larger
  59                                            than on PQ2 */
  60
  61 void
  62 cpm2_reset(void)
  63 {
  64 #ifdef CONFIG_PPC_85xx
  65         cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
  66 #else
  67         cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
  68 #endif
  69
  70         /* Reclaim the DP memory for our use.
  71          */
  72         cpm2_dpinit();
  73
  74         /* Tell everyone where the comm processor resides.
  75          */
  76         cpmp = &cpm2_immr->im_cpm;
  77 }
  78
  79 /* Set a baud rate generator.  This needs lots of work.  There are
  80  * eight BRGs, which can be connected to the CPM channels or output
  81  * as clocks.  The BRGs are in two different block of internal
  82  * memory mapped space.
  83  * The baud rate clock is the system clock divided by something.
  84  * It was set up long ago during the initial boot phase and is
  85  * is given to us.
  86  * Baud rate clocks are zero-based in the driver code (as that maps
  87  * to port numbers).  Documentation uses 1-based numbering.
  88  */
  89 #define BRG_INT_CLK     (get_brgfreq())
  90 #define BRG_UART_CLK    (BRG_INT_CLK/16)
  91
  92 /* This function is used by UARTS, or anything else that uses a 16x
  93  * oversampled clock.
  94  */
  95 void
  96 cpm_setbrg(uint brg, uint rate)
  97 {
  98         u32 __iomem *bp;
  99
 100         /* This is good enough to get SMCs running.....
 101         */
 102         if (brg < 4) {
 103                 bp = cpm2_map_size(im_brgc1, 16);
 104         } else {
 105                 bp = cpm2_map_size(im_brgc5, 16);
 106                 brg -= 4;
 107         }
 108         bp += brg;
 109         out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 110
 111         cpm2_unmap(bp);
 112 }
 113
 114 /* This function is used to set high speed synchronous baud rate
 115  * clocks.
 116  */
 117 void
 118 cpm2_fastbrg(uint brg, uint rate, int div16)
 119 {
 120         u32 __iomem *bp;
 121         u32 val;
 122
 123         if (brg < 4) {
 124                 bp = cpm2_map_size(im_brgc1, 16);
 125         }
 126         else {
 127                 bp = cpm2_map_size(im_brgc5, 16);
 128                 brg -= 4;
 129         }
 130         bp += brg;
 131         val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
 132         if (div16)
 133                 val |= CPM_BRG_DIV16;
 134
 135         out_be32(bp, val);
 136         cpm2_unmap(bp);
 137 }
 138
 139 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 140 {
 141         int ret = 0;
 142         int shift;
 143         int i, bits = 0;
 144         cpmux_t __iomem *im_cpmux;
 145         u32 __iomem *reg;
 146         u32 mask = 7;
 147
 148         u8 clk_map[][3] = {
 149                 {CPM_CLK_FCC1, CPM_BRG5, 0},
 150                 {CPM_CLK_FCC1, CPM_BRG6, 1},
 151                 {CPM_CLK_FCC1, CPM_BRG7, 2},
 152                 {CPM_CLK_FCC1, CPM_BRG8, 3},
 153                 {CPM_CLK_FCC1, CPM_CLK9, 4},
 154                 {CPM_CLK_FCC1, CPM_CLK10, 5},
 155                 {CPM_CLK_FCC1, CPM_CLK11, 6},
 156                 {CPM_CLK_FCC1, CPM_CLK12, 7},
 157                 {CPM_CLK_FCC2, CPM_BRG5, 0},
 158                 {CPM_CLK_FCC2, CPM_BRG6, 1},
 159                 {CPM_CLK_FCC2, CPM_BRG7, 2},
 160                 {CPM_CLK_FCC2, CPM_BRG8, 3},
 161                 {CPM_CLK_FCC2, CPM_CLK13, 4},
 162                 {CPM_CLK_FCC2, CPM_CLK14, 5},
 163                 {CPM_CLK_FCC2, CPM_CLK15, 6},
 164                 {CPM_CLK_FCC2, CPM_CLK16, 7},
 165                 {CPM_CLK_FCC3, CPM_BRG5, 0},
 166                 {CPM_CLK_FCC3, CPM_BRG6, 1},
 167                 {CPM_CLK_FCC3, CPM_BRG7, 2},
 168                 {CPM_CLK_FCC3, CPM_BRG8, 3},
 169                 {CPM_CLK_FCC3, CPM_CLK13, 4},
 170                 {CPM_CLK_FCC3, CPM_CLK14, 5},
 171                 {CPM_CLK_FCC3, CPM_CLK15, 6},
 172                 {CPM_CLK_FCC3, CPM_CLK16, 7},
 173                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 174                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 175                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 176                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 177                 {CPM_CLK_SCC1, CPM_CLK11, 4},
 178                 {CPM_CLK_SCC1, CPM_CLK12, 5},
 179                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 180                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 181                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 182                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 183                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 184                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 185                 {CPM_CLK_SCC2, CPM_CLK11, 4},
 186                 {CPM_CLK_SCC2, CPM_CLK12, 5},
 187                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 188                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 189                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 190                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 191                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 192                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 193                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 194                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 195                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 196                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 197                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 198                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 199                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 200                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 201                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 202                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 203                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 204                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 205         };
 206
 207         im_cpmux = cpm2_map(im_cpmux);
 208
 209         switch (target) {
 210         case CPM_CLK_SCC1:
 211                 reg = &im_cpmux->cmx_scr;
 212                 shift = 24;
 213         case CPM_CLK_SCC2:
 214                 reg = &im_cpmux->cmx_scr;
 215                 shift = 16;
 216                 break;
 217         case CPM_CLK_SCC3:
 218                 reg = &im_cpmux->cmx_scr;
 219                 shift = 8;
 220                 break;
 221         case CPM_CLK_SCC4:
 222                 reg = &im_cpmux->cmx_scr;
 223                 shift = 0;
 224                 break;
 225         case CPM_CLK_FCC1:
 226                 reg = &im_cpmux->cmx_fcr;
 227                 shift = 24;
 228                 break;
 229         case CPM_CLK_FCC2:
 230                 reg = &im_cpmux->cmx_fcr;
 231                 shift = 16;
 232                 break;
 233         case CPM_CLK_FCC3:
 234                 reg = &im_cpmux->cmx_fcr;
 235                 shift = 8;
 236                 break;
 237         default:
 238                 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
 239                 return -EINVAL;
 240         }
 241
 242         if (mode == CPM_CLK_RX)
 243                 shift += 3;
 244
 245         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 246                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 247                         bits = clk_map[i][2];
 248                         break;
 249                 }
 250         }
 251         if (i == ARRAY_SIZE(clk_map))
 252             ret = -EINVAL;
 253
 254         bits <<= shift;
 255         mask <<= shift;
 256
 257         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 258
 259         cpm2_unmap(im_cpmux);
 260         return ret;
 261 }
 262
 263 int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
 264 {
 265         int ret = 0;
 266         int shift;
 267         int i, bits = 0;
 268         cpmux_t __iomem *im_cpmux;
 269         u8 __iomem *reg;
 270         u8 mask = 3;
 271
 272         u8 clk_map[][3] = {
 273                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 274                 {CPM_CLK_SMC1, CPM_BRG7, 1},
 275                 {CPM_CLK_SMC1, CPM_CLK7, 2},
 276                 {CPM_CLK_SMC1, CPM_CLK9, 3},
 277                 {CPM_CLK_SMC2, CPM_BRG2, 0},
 278                 {CPM_CLK_SMC2, CPM_BRG8, 1},
 279                 {CPM_CLK_SMC2, CPM_CLK4, 2},
 280                 {CPM_CLK_SMC2, CPM_CLK15, 3},
 281         };
 282
 283         im_cpmux = cpm2_map(im_cpmux);
 284
 285         switch (target) {
 286         case CPM_CLK_SMC1:
 287                 reg = &im_cpmux->cmx_smr;
 288                 mask = 3;
 289                 shift = 4;
 290                 break;
 291         case CPM_CLK_SMC2:
 292                 reg = &im_cpmux->cmx_smr;
 293                 mask = 3;
 294                 shift = 0;
 295                 break;
 296         default:
 297                 printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
 298                 return -EINVAL;
 299         }
 300
 301         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 302                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 303                         bits = clk_map[i][2];
 304                         break;
 305                 }
 306         }
 307         if (i == ARRAY_SIZE(clk_map))
 308             ret = -EINVAL;
 309
 310         bits <<= shift;
 311         mask <<= shift;
 312
 313         out_8(reg, (in_8(reg) & ~mask) | bits);
 314
 315         cpm2_unmap(im_cpmux);
 316         return ret;
 317 }
 318
 319 /*
 320  * dpalloc / dpfree bits.
 321  */
 322 static spinlock_t cpm_dpmem_lock;
 323 /* 16 blocks should be enough to satisfy all requests
 324  * until the memory subsystem goes up... */
 325 static rh_block_t cpm_boot_dpmem_rh_block[16];
 326 static rh_info_t cpm_dpmem_info;
 327 static u8 __iomem *im_dprambase;
 328
 329 static void cpm2_dpinit(void)
 330 {
 331         struct resource r;
 332
 333 #ifdef CONFIG_PPC_CPM_NEW_BINDING
 334         struct device_node *np;
 335
 336         np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
 337         if (!np)
 338                 panic("Cannot find CPM2 node");
 339
 340         if (of_address_to_resource(np, 1, &r))
 341                 panic("Cannot get CPM2 resource 1");
 342
 343         of_node_put(np);
 344 #else
 345         r.start = CPM_MAP_ADDR;
 346         r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1;
 347 #endif
 348
 349         im_dprambase = ioremap(r.start, r.end - r.start + 1);
 350         if (!im_dprambase)
 351                 panic("Cannot map DPRAM");
 352
 353         spin_lock_init(&cpm_dpmem_lock);
 354
 355         /* initialize the info header */
 356         rh_init(&cpm_dpmem_info, 1,
 357                         sizeof(cpm_boot_dpmem_rh_block) /
 358                         sizeof(cpm_boot_dpmem_rh_block[0]),
 359                         cpm_boot_dpmem_rh_block);
 360
 361         /* Attach the usable dpmem area */
 362         /* XXX: This is actually crap. CPM_DATAONLY_BASE and
 363          * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
 364          * varies with the processor and the microcode patches activated.
 365          * But the following should be at least safe.
 366          */
 367         rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1);
 368 }
 369
 370 /* This function returns an index into the DPRAM area.
 371  */
 372 unsigned long cpm_dpalloc(uint size, uint align)
 373 {
 374         unsigned long start;
 375         unsigned long flags;
 376
 377         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 378         cpm_dpmem_info.alignment = align;
 379         start = rh_alloc(&cpm_dpmem_info, size, "commproc");
 380         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 381
 382         return (uint)start;
 383 }
 384 EXPORT_SYMBOL(cpm_dpalloc);
 385
 386 int cpm_dpfree(unsigned long offset)
 387 {
 388         int ret;
 389         unsigned long flags;
 390
 391         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 392         ret = rh_free(&cpm_dpmem_info, offset);
 393         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 394
 395         return ret;
 396 }
 397 EXPORT_SYMBOL(cpm_dpfree);
 398
 399 /* not sure if this is ever needed */
 400 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
 401 {
 402         unsigned long start;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 406         cpm_dpmem_info.alignment = align;
 407         start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
 408         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 409
 410         return start;
 411 }
 412 EXPORT_SYMBOL(cpm_dpalloc_fixed);
 413
 414 void cpm_dpdump(void)
 415 {
 416         rh_dump(&cpm_dpmem_info);
 417 }
 418 EXPORT_SYMBOL(cpm_dpdump);
 419
 420 void *cpm_dpram_addr(unsigned long offset)
 421 {
 422         return (void *)(im_dprambase + offset);
 423 }
 424 EXPORT_SYMBOL(cpm_dpram_addr);
 425
 426 struct cpm2_ioports {
 427         u32 dir, par, sor, odr, dat;
 428         u32 res[3];
 429 };
 430
 431 void cpm2_set_pin(int port, int pin, int flags)
 432 {
 433         struct cpm2_ioports __iomem *iop =
 434                 (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
 435
 436         pin = 1 << (31 - pin);
 437
 438         if (flags & CPM_PIN_OUTPUT)
 439                 setbits32(&iop[port].dir, pin);
 440         else
 441                 clrbits32(&iop[port].dir, pin);
 442
 443         if (!(flags & CPM_PIN_GPIO))
 444                 setbits32(&iop[port].par, pin);
 445         else
 446                 clrbits32(&iop[port].par, pin);
 447
 448         if (flags & CPM_PIN_SECONDARY)
 449                 setbits32(&iop[port].sor, pin);
 450         else
 451                 clrbits32(&iop[port].sor, pin);
 452
 453         if (flags & CPM_PIN_OPENDRAIN)
 454                 setbits32(&iop[port].odr, pin);
 455         else
 456                 clrbits32(&iop[port].odr, pin);
 457 }