2 * PCI / PCI-X / PCI-Express support for 4xx parts
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 * Some of that comes itself from a previous implementation for 440SPE only
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
35 #include "ppc4xx_pci.h"
37 static int dma_offset_set;
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42 #ifdef CONFIG_RESOURCES_64BIT
43 #define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
44 #define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
46 #define RES_TO_U32_LOW(val) (val)
47 #define RES_TO_U32_HIGH(val) (0)
50 static inline int ppc440spe_revA(void)
52 /* Catch both 440SPe variants, with and without RAID6 support */
53 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
59 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
61 struct pci_controller *hose;
64 if (dev->devfn != 0 || dev->bus->self != NULL)
67 hose = pci_bus_to_host(dev->bus);
71 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
72 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
73 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
76 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
77 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
78 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
81 /* Hide the PCI host BARs from the kernel as their content doesn't
82 * fit well in the resource management
84 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
85 dev->resource[i].start = dev->resource[i].end = 0;
86 dev->resource[i].flags = 0;
89 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
92 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
94 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
101 int pna = of_n_addr_cells(hose->dn);
108 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
110 /* Get dma-ranges property */
111 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
116 while ((rlen -= np * 4) >= 0) {
117 u32 pci_space = ranges[0];
118 u64 pci_addr = of_read_number(ranges + 1, 2);
119 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
120 size = of_read_number(ranges + pna + 3, 2);
122 if (cpu_addr == OF_BAD_ADDR || size == 0)
125 /* We only care about memory */
126 if ((pci_space & 0x03000000) != 0x02000000)
129 /* We currently only support memory at 0, and pci_addr
130 * within 32 bits space
132 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
133 printk(KERN_WARNING "%s: Ignored unsupported dma range"
134 " 0x%016llx...0x%016llx -> 0x%016llx\n",
136 pci_addr, pci_addr + size - 1, cpu_addr);
140 /* Check if not prefetchable */
141 if (!(pci_space & 0x40000000))
142 res->flags &= ~IORESOURCE_PREFETCH;
146 res->start = pci_addr;
147 #ifndef CONFIG_RESOURCES_64BIT
148 /* Beware of 32 bits resources */
149 if ((pci_addr + size) > 0x100000000ull)
150 res->end = 0xffffffff;
153 res->end = res->start + size - 1;
157 /* We only support one global DMA offset */
158 if (dma_offset_set && pci_dram_offset != res->start) {
159 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
160 hose->dn->full_name);
164 /* Check that we can fit all of memory as we don't support
167 if (size < total_memory) {
168 printk(KERN_ERR "%s: dma-ranges too small "
169 "(size=%llx total_memory=%llx)\n",
170 hose->dn->full_name, size, (u64)total_memory);
174 /* Check we are a power of 2 size and that base is a multiple of size*/
175 if ((size & (size - 1)) != 0 ||
176 (res->start & (size - 1)) != 0) {
177 printk(KERN_ERR "%s: dma-ranges unaligned\n",
178 hose->dn->full_name);
182 /* Check that we are fully contained within 32 bits space */
183 if (res->end > 0xffffffff) {
184 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
185 hose->dn->full_name);
190 pci_dram_offset = res->start;
192 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
201 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
204 u32 la, ma, pcila, pciha;
207 /* Setup outbound memory windows */
208 for (i = j = 0; i < 3; i++) {
209 struct resource *res = &hose->mem_resources[i];
211 /* we only care about memory windows */
212 if (!(res->flags & IORESOURCE_MEM))
215 printk(KERN_WARNING "%s: Too many ranges\n",
216 hose->dn->full_name);
220 /* Calculate register values */
222 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
223 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
225 ma = res->end + 1 - res->start;
226 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
227 printk(KERN_WARNING "%s: Resource out of range\n",
228 hose->dn->full_name);
231 ma = (0xffffffffu << ilog2(ma)) | 0x1;
232 if (res->flags & IORESOURCE_PREFETCH)
235 /* Program register values */
236 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
237 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
238 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
239 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
244 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
246 const struct resource *res)
248 resource_size_t size = res->end - res->start + 1;
251 /* Calculate window size */
252 sa = (0xffffffffu << ilog2(size)) | 1;
255 /* RAM is always at 0 local for now */
256 writel(0, reg + PCIL0_PTM1LA);
257 writel(sa, reg + PCIL0_PTM1MS);
259 /* Map on PCI side */
260 early_write_config_dword(hose, hose->first_busno, 0,
261 PCI_BASE_ADDRESS_1, res->start);
262 early_write_config_dword(hose, hose->first_busno, 0,
263 PCI_BASE_ADDRESS_2, 0x00000000);
264 early_write_config_word(hose, hose->first_busno, 0,
265 PCI_COMMAND, 0x0006);
268 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
271 struct resource rsrc_cfg;
272 struct resource rsrc_reg;
273 struct resource dma_window;
274 struct pci_controller *hose = NULL;
275 void __iomem *reg = NULL;
276 const int *bus_range;
279 /* Check if device is enabled */
280 if (!of_device_is_available(np)) {
281 printk(KERN_INFO "%s: Port disabled via device-tree\n",
286 /* Fetch config space registers address */
287 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
288 printk(KERN_ERR "%s: Can't get PCI config register base !",
292 /* Fetch host bridge internal registers address */
293 if (of_address_to_resource(np, 3, &rsrc_reg)) {
294 printk(KERN_ERR "%s: Can't get PCI internal register base !",
299 /* Check if primary bridge */
300 if (of_get_property(np, "primary", NULL))
303 /* Get bus range if any */
304 bus_range = of_get_property(np, "bus-range", NULL);
307 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
309 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
313 /* Allocate the host controller data structure */
314 hose = pcibios_alloc_controller(np);
318 hose->first_busno = bus_range ? bus_range[0] : 0x0;
319 hose->last_busno = bus_range ? bus_range[1] : 0xff;
321 /* Setup config space */
322 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
324 /* Disable all windows */
325 writel(0, reg + PCIL0_PMM0MA);
326 writel(0, reg + PCIL0_PMM1MA);
327 writel(0, reg + PCIL0_PMM2MA);
328 writel(0, reg + PCIL0_PTM1MS);
329 writel(0, reg + PCIL0_PTM2MS);
331 /* Parse outbound mapping resources */
332 pci_process_bridge_OF_ranges(hose, np, primary);
334 /* Parse inbound mapping resources */
335 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
338 /* Configure outbound ranges POMs */
339 ppc4xx_configure_pci_PMMs(hose, reg);
341 /* Configure inbound ranges PIMs */
342 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
344 /* We don't need the registers anymore */
350 pcibios_free_controller(hose);
359 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
362 u32 lah, lal, pciah, pcial, sa;
365 /* Setup outbound memory windows */
366 for (i = j = 0; i < 3; i++) {
367 struct resource *res = &hose->mem_resources[i];
369 /* we only care about memory windows */
370 if (!(res->flags & IORESOURCE_MEM))
373 printk(KERN_WARNING "%s: Too many ranges\n",
374 hose->dn->full_name);
378 /* Calculate register values */
379 lah = RES_TO_U32_HIGH(res->start);
380 lal = RES_TO_U32_LOW(res->start);
381 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
382 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
383 sa = res->end + 1 - res->start;
384 if (!is_power_of_2(sa) || sa < 0x100000 ||
386 printk(KERN_WARNING "%s: Resource out of range\n",
387 hose->dn->full_name);
390 sa = (0xffffffffu << ilog2(sa)) | 0x1;
392 /* Program register values */
394 writel(lah, reg + PCIX0_POM0LAH);
395 writel(lal, reg + PCIX0_POM0LAL);
396 writel(pciah, reg + PCIX0_POM0PCIAH);
397 writel(pcial, reg + PCIX0_POM0PCIAL);
398 writel(sa, reg + PCIX0_POM0SA);
400 writel(lah, reg + PCIX0_POM1LAH);
401 writel(lal, reg + PCIX0_POM1LAL);
402 writel(pciah, reg + PCIX0_POM1PCIAH);
403 writel(pcial, reg + PCIX0_POM1PCIAL);
404 writel(sa, reg + PCIX0_POM1SA);
410 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
412 const struct resource *res,
416 resource_size_t size = res->end - res->start + 1;
419 /* RAM is always at 0 */
420 writel(0x00000000, reg + PCIX0_PIM0LAH);
421 writel(0x00000000, reg + PCIX0_PIM0LAL);
423 /* Calculate window size */
424 sa = (0xffffffffu << ilog2(size)) | 1;
426 if (res->flags & IORESOURCE_PREFETCH)
430 writel(sa, reg + PCIX0_PIM0SA);
432 writel(0xffffffff, reg + PCIX0_PIM0SAH);
434 /* Map on PCI side */
435 writel(0x00000000, reg + PCIX0_BAR0H);
436 writel(res->start, reg + PCIX0_BAR0L);
437 writew(0x0006, reg + PCIX0_COMMAND);
440 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
442 struct resource rsrc_cfg;
443 struct resource rsrc_reg;
444 struct resource dma_window;
445 struct pci_controller *hose = NULL;
446 void __iomem *reg = NULL;
447 const int *bus_range;
448 int big_pim = 0, msi = 0, primary = 0;
450 /* Fetch config space registers address */
451 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
452 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
456 /* Fetch host bridge internal registers address */
457 if (of_address_to_resource(np, 3, &rsrc_reg)) {
458 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
463 /* Check if it supports large PIMs (440GX) */
464 if (of_get_property(np, "large-inbound-windows", NULL))
467 /* Check if we should enable MSIs inbound hole */
468 if (of_get_property(np, "enable-msi-hole", NULL))
471 /* Check if primary bridge */
472 if (of_get_property(np, "primary", NULL))
475 /* Get bus range if any */
476 bus_range = of_get_property(np, "bus-range", NULL);
479 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
481 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
485 /* Allocate the host controller data structure */
486 hose = pcibios_alloc_controller(np);
490 hose->first_busno = bus_range ? bus_range[0] : 0x0;
491 hose->last_busno = bus_range ? bus_range[1] : 0xff;
493 /* Setup config space */
494 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
496 /* Disable all windows */
497 writel(0, reg + PCIX0_POM0SA);
498 writel(0, reg + PCIX0_POM1SA);
499 writel(0, reg + PCIX0_POM2SA);
500 writel(0, reg + PCIX0_PIM0SA);
501 writel(0, reg + PCIX0_PIM1SA);
502 writel(0, reg + PCIX0_PIM2SA);
504 writel(0, reg + PCIX0_PIM0SAH);
505 writel(0, reg + PCIX0_PIM2SAH);
508 /* Parse outbound mapping resources */
509 pci_process_bridge_OF_ranges(hose, np, primary);
511 /* Parse inbound mapping resources */
512 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
515 /* Configure outbound ranges POMs */
516 ppc4xx_configure_pcix_POMs(hose, reg);
518 /* Configure inbound ranges PIMs */
519 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
521 /* We don't need the registers anymore */
527 pcibios_free_controller(hose);
532 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
535 * 4xx PCI-Express part
537 * We support 3 parts currently based on the compatible property:
539 * ibm,plb-pciex-440spe
540 * ibm,plb-pciex-405ex
541 * ibm,plb-pciex-460ex
543 * Anything else will be rejected for now as they are all subtly
544 * different unfortunately.
548 #define MAX_PCIE_BUS_MAPPED 0x40
550 struct ppc4xx_pciex_port
552 struct pci_controller *hose;
553 struct device_node *node;
558 unsigned int sdr_base;
560 struct resource cfg_space;
561 struct resource utl_regs;
562 void __iomem *utl_base;
565 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
566 static unsigned int ppc4xx_pciex_port_count;
568 struct ppc4xx_pciex_hwops
570 int (*core_init)(struct device_node *np);
571 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
572 int (*setup_utl)(struct ppc4xx_pciex_port *port);
575 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
579 /* Check various reset bits of the 440SPe PCIe core */
580 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
582 u32 valPE0, valPE1, valPE2;
585 /* SDR0_PEGPLLLCT1 reset */
586 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
588 * the PCIe core was probably already initialised
589 * by firmware - let's re-reset RCSSET regs
591 * -- Shouldn't we also re-reset the whole thing ? -- BenH
593 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
594 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
595 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
596 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
599 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
600 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
601 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
603 /* SDR0_PExRCSSET rstgu */
604 if (!(valPE0 & 0x01000000) ||
605 !(valPE1 & 0x01000000) ||
606 !(valPE2 & 0x01000000)) {
607 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
611 /* SDR0_PExRCSSET rstdl */
612 if (!(valPE0 & 0x00010000) ||
613 !(valPE1 & 0x00010000) ||
614 !(valPE2 & 0x00010000)) {
615 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
619 /* SDR0_PExRCSSET rstpyn */
620 if ((valPE0 & 0x00001000) ||
621 (valPE1 & 0x00001000) ||
622 (valPE2 & 0x00001000)) {
623 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
627 /* SDR0_PExRCSSET hldplb */
628 if ((valPE0 & 0x10000000) ||
629 (valPE1 & 0x10000000) ||
630 (valPE2 & 0x10000000)) {
631 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
635 /* SDR0_PExRCSSET rdy */
636 if ((valPE0 & 0x00100000) ||
637 (valPE1 & 0x00100000) ||
638 (valPE2 & 0x00100000)) {
639 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
643 /* SDR0_PExRCSSET shutdown */
644 if ((valPE0 & 0x00000100) ||
645 (valPE1 & 0x00000100) ||
646 (valPE2 & 0x00000100)) {
647 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
654 /* Global PCIe core initializations for 440SPe core */
655 static int __init ppc440spe_pciex_core_init(struct device_node *np)
659 /* Set PLL clock receiver to LVPECL */
660 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
662 /* Shouldn't we do all the calibration stuff etc... here ? */
663 if (ppc440spe_pciex_check_reset(np))
666 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
667 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
669 mfdcri(SDR0, PESDR0_PLLLCT2));
673 /* De-assert reset of PCIe PLL, wait for lock */
674 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
678 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
685 printk(KERN_INFO "PCIE: VCO output not locked\n");
689 pr_debug("PCIE initialization OK\n");
694 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
699 val = PTYPE_LEGACY_ENDPOINT << 20;
701 val = PTYPE_ROOT_PORT << 20;
703 if (port->index == 0)
704 val |= LNKW_X8 << 12;
706 val |= LNKW_X4 << 12;
708 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
709 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
710 if (ppc440spe_revA())
711 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
713 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
714 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
715 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
716 if (port->index == 0) {
717 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
719 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
721 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
723 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
726 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
727 (1 << 24) | (1 << 16), 1 << 12);
732 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
734 return ppc440spe_pciex_init_port_hw(port);
737 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
739 int rc = ppc440spe_pciex_init_port_hw(port);
746 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
748 /* XXX Check what that value means... I hate magic */
749 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
752 * Set buffer allocations and then assert VRB and TXE.
754 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
755 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
756 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
757 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
758 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
759 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
760 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
761 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
766 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
768 /* Report CRS to the operating system */
769 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
774 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
776 .core_init = ppc440spe_pciex_core_init,
777 .port_init_hw = ppc440speA_pciex_init_port_hw,
778 .setup_utl = ppc440speA_pciex_init_utl,
781 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
783 .core_init = ppc440spe_pciex_core_init,
784 .port_init_hw = ppc440speB_pciex_init_port_hw,
785 .setup_utl = ppc440speB_pciex_init_utl,
788 static int __init ppc460ex_pciex_core_init(struct device_node *np)
790 /* Nothing to do, return 2 ports */
794 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
800 val = PTYPE_LEGACY_ENDPOINT << 20;
802 val = PTYPE_ROOT_PORT << 20;
804 if (port->index == 0) {
805 val |= LNKW_X1 << 12;
806 utlset1 = 0x20000000;
808 val |= LNKW_X4 << 12;
809 utlset1 = 0x20101101;
812 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
813 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
814 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
816 switch (port->index) {
818 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
820 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
822 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
826 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
827 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
828 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
829 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
830 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
831 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
832 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
833 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
834 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
835 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
836 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
837 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
839 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
843 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
844 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
845 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
847 /* Poll for PHY reset */
848 /* XXX FIXME add timeout */
849 switch (port->index) {
851 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
855 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
860 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
861 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
862 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
863 PESDRx_RCSSET_RSTPYN);
870 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
872 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
875 * Set buffer allocations and then assert VRB and TXE.
877 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
878 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
879 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
880 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
881 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
882 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
883 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
884 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
885 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
890 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
892 .core_init = ppc460ex_pciex_core_init,
893 .port_init_hw = ppc460ex_pciex_init_port_hw,
894 .setup_utl = ppc460ex_pciex_init_utl,
897 #endif /* CONFIG_44x */
901 static int __init ppc405ex_pciex_core_init(struct device_node *np)
903 /* Nothing to do, return 2 ports */
907 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
909 /* Assert the PE0_PHY reset */
910 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
913 /* deassert the PE0_hotreset */
915 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
917 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
919 /* poll for phy !reset */
920 /* XXX FIXME add timeout */
921 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
924 /* deassert the PE0_gpl_utl_reset */
925 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
928 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
933 val = PTYPE_LEGACY_ENDPOINT;
935 val = PTYPE_ROOT_PORT;
937 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
938 1 << 24 | val << 20 | LNKW_X1 << 12);
940 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
941 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
942 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
943 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
946 * Only reset the PHY when no link is currently established.
947 * This is for the Atheros PCIe board which has problems to establish
948 * the link (again) after this PHY reset. All other currently tested
949 * PCIe boards don't show this problem.
950 * This has to be re-tested and fixed in a later release!
952 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
953 if (!(val & 0x00001000))
954 ppc405ex_pcie_phy_reset(port);
956 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
963 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
965 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
968 * Set buffer allocations and then assert VRB and TXE.
970 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
971 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
972 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
973 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
974 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
975 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
976 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
977 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
979 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
984 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
986 .core_init = ppc405ex_pciex_core_init,
987 .port_init_hw = ppc405ex_pciex_init_port_hw,
988 .setup_utl = ppc405ex_pciex_init_utl,
991 #endif /* CONFIG_40x */
994 /* Check that the core has been initied and if not, do it */
995 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
997 static int core_init;
1004 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1005 if (ppc440spe_revA())
1006 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1008 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1010 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1011 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1012 #endif /* CONFIG_44x */
1014 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1015 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1017 if (ppc4xx_pciex_hwops == NULL) {
1018 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1023 count = ppc4xx_pciex_hwops->core_init(np);
1025 ppc4xx_pciex_ports =
1026 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1028 if (ppc4xx_pciex_ports) {
1029 ppc4xx_pciex_port_count = count;
1032 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1038 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1040 /* We map PCI Express configuration based on the reg property */
1041 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1042 RES_TO_U32_HIGH(port->cfg_space.start));
1043 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1044 RES_TO_U32_LOW(port->cfg_space.start));
1046 /* XXX FIXME: Use size from reg property. For now, map 512M */
1047 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1049 /* We map UTL registers based on the reg property */
1050 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1051 RES_TO_U32_HIGH(port->utl_regs.start));
1052 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1053 RES_TO_U32_LOW(port->utl_regs.start));
1055 /* XXX FIXME: Use size from reg property */
1056 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1058 /* Disable all other outbound windows */
1059 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1060 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1061 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1062 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1065 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1066 unsigned int sdr_offset,
1073 while(timeout_ms--) {
1074 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1075 if ((val & mask) == value) {
1076 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1077 port->index, sdr_offset, timeout_ms, val);
1085 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1090 if (ppc4xx_pciex_hwops->port_init_hw)
1091 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1095 printk(KERN_INFO "PCIE%d: Checking link...\n",
1098 /* Wait for reset to complete */
1099 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1100 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1105 /* Check for card presence detect if supported, if not, just wait for
1106 * link unconditionally.
1108 * note that we don't fail if there is no link, we just filter out
1109 * config space accesses. That way, it will be easier to implement
1112 if (!port->has_ibpre ||
1113 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1114 1 << 28, 1 << 28, 100)) {
1116 "PCIE%d: Device detected, waiting for link...\n",
1118 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1119 0x1000, 0x1000, 2000))
1121 "PCIE%d: Link up failed\n", port->index);
1124 "PCIE%d: link is up !\n", port->index);
1128 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1131 * Initialize mapping: disable all regions and configure
1132 * CFG and REG regions based on resources in the device tree
1134 ppc4xx_pciex_port_init_mapping(port);
1139 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1140 BUG_ON(port->utl_base == NULL);
1143 * Setup UTL registers --BenH.
1145 if (ppc4xx_pciex_hwops->setup_utl)
1146 ppc4xx_pciex_hwops->setup_utl(port);
1149 * Check for VC0 active and assert RDY.
1152 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1153 1 << 16, 1 << 16, 5000)) {
1154 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1158 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1164 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1165 struct pci_bus *bus,
1170 /* Endpoint can not generate upstream(remote) config cycles */
1171 if (port->endpoint && bus->number != port->hose->first_busno)
1172 return PCIBIOS_DEVICE_NOT_FOUND;
1174 /* Check we are within the mapped range */
1175 if (bus->number > port->hose->last_busno) {
1177 printk(KERN_WARNING "Warning! Probing bus %u"
1178 " out of range !\n", bus->number);
1181 return PCIBIOS_DEVICE_NOT_FOUND;
1184 /* The root complex has only one device / function */
1185 if (bus->number == port->hose->first_busno && devfn != 0)
1186 return PCIBIOS_DEVICE_NOT_FOUND;
1188 /* The other side of the RC has only one device as well */
1189 if (bus->number == (port->hose->first_busno + 1) &&
1190 PCI_SLOT(devfn) != 0)
1191 return PCIBIOS_DEVICE_NOT_FOUND;
1193 /* Check if we have a link */
1194 if ((bus->number != port->hose->first_busno) && !port->link)
1195 return PCIBIOS_DEVICE_NOT_FOUND;
1200 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1201 struct pci_bus *bus,
1206 /* Remove the casts when we finally remove the stupid volatile
1207 * in struct pci_controller
1209 if (bus->number == port->hose->first_busno)
1210 return (void __iomem *)port->hose->cfg_addr;
1212 relbus = bus->number - (port->hose->first_busno + 1);
1213 return (void __iomem *)port->hose->cfg_data +
1214 ((relbus << 20) | (devfn << 12));
1217 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1218 int offset, int len, u32 *val)
1220 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1221 struct ppc4xx_pciex_port *port =
1222 &ppc4xx_pciex_ports[hose->indirect_type];
1226 BUG_ON(hose != port->hose);
1228 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1229 return PCIBIOS_DEVICE_NOT_FOUND;
1231 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1234 * Reading from configuration space of non-existing device can
1235 * generate transaction errors. For the read duration we suppress
1236 * assertion of machine check exceptions to avoid those.
1238 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1239 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1241 /* Make sure no CRS is recorded */
1242 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1246 *val = in_8((u8 *)(addr + offset));
1249 *val = in_le16((u16 *)(addr + offset));
1252 *val = in_le32((u32 *)(addr + offset));
1256 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1257 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1258 bus->number, hose->first_busno, hose->last_busno,
1259 devfn, offset, len, addr + offset, *val);
1261 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1262 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1263 pr_debug("Got CRS !\n");
1264 if (len != 4 || offset != 0)
1265 return PCIBIOS_DEVICE_NOT_FOUND;
1269 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1271 return PCIBIOS_SUCCESSFUL;
1274 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1275 int offset, int len, u32 val)
1277 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1278 struct ppc4xx_pciex_port *port =
1279 &ppc4xx_pciex_ports[hose->indirect_type];
1283 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1284 return PCIBIOS_DEVICE_NOT_FOUND;
1286 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1289 * Reading from configuration space of non-existing device can
1290 * generate transaction errors. For the read duration we suppress
1291 * assertion of machine check exceptions to avoid those.
1293 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1294 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1296 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1297 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1298 bus->number, hose->first_busno, hose->last_busno,
1299 devfn, offset, len, addr + offset, val);
1303 out_8((u8 *)(addr + offset), val);
1306 out_le16((u16 *)(addr + offset), val);
1309 out_le32((u32 *)(addr + offset), val);
1313 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1315 return PCIBIOS_SUCCESSFUL;
1318 static struct pci_ops ppc4xx_pciex_pci_ops =
1320 .read = ppc4xx_pciex_read_config,
1321 .write = ppc4xx_pciex_write_config,
1324 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1325 struct pci_controller *hose,
1326 void __iomem *mbase)
1328 u32 lah, lal, pciah, pcial, sa;
1331 /* Setup outbound memory windows */
1332 for (i = j = 0; i < 3; i++) {
1333 struct resource *res = &hose->mem_resources[i];
1335 /* we only care about memory windows */
1336 if (!(res->flags & IORESOURCE_MEM))
1339 printk(KERN_WARNING "%s: Too many ranges\n",
1340 port->node->full_name);
1344 /* Calculate register values */
1345 lah = RES_TO_U32_HIGH(res->start);
1346 lal = RES_TO_U32_LOW(res->start);
1347 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1348 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1349 sa = res->end + 1 - res->start;
1350 if (!is_power_of_2(sa) || sa < 0x100000 ||
1352 printk(KERN_WARNING "%s: Resource out of range\n",
1353 port->node->full_name);
1356 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1358 /* Program register values */
1361 out_le32(mbase + PECFG_POM0LAH, pciah);
1362 out_le32(mbase + PECFG_POM0LAL, pcial);
1363 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1364 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1365 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1366 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1369 out_le32(mbase + PECFG_POM1LAH, pciah);
1370 out_le32(mbase + PECFG_POM1LAL, pcial);
1371 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1372 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1373 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1374 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1380 /* Configure IO, always 64K starting at 0 */
1381 if (hose->io_resource.flags & IORESOURCE_IO) {
1382 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1383 lal = RES_TO_U32_LOW(hose->io_base_phys);
1384 out_le32(mbase + PECFG_POM2LAH, 0);
1385 out_le32(mbase + PECFG_POM2LAL, 0);
1386 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1387 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1388 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1389 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1393 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1394 struct pci_controller *hose,
1395 void __iomem *mbase,
1396 struct resource *res)
1398 resource_size_t size = res->end - res->start + 1;
1401 if (port->endpoint) {
1402 resource_size_t ep_addr = 0;
1403 resource_size_t ep_size = 32 << 20;
1405 /* Currently we map a fixed 64MByte window to PLB address
1406 * 0 (SDRAM). This should probably be configurable via a dts
1410 /* Calculate window size */
1411 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1414 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1415 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1416 PCI_BASE_ADDRESS_MEM_TYPE_64);
1418 /* Disable BAR1 & BAR2 */
1419 out_le32(mbase + PECFG_BAR1MPA, 0);
1420 out_le32(mbase + PECFG_BAR2HMPA, 0);
1421 out_le32(mbase + PECFG_BAR2LMPA, 0);
1423 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1424 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1426 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1427 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1429 /* Calculate window size */
1430 sa = (0xffffffffffffffffull << ilog2(size));;
1431 if (res->flags & IORESOURCE_PREFETCH)
1434 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1435 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1437 /* The setup of the split looks weird to me ... let's see
1440 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1441 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1442 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1443 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1444 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1445 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1447 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1448 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1451 /* Enable inbound mapping */
1452 out_le32(mbase + PECFG_PIMEN, 0x1);
1454 /* Enable I/O, Mem, and Busmaster cycles */
1455 out_le16(mbase + PCI_COMMAND,
1456 in_le16(mbase + PCI_COMMAND) |
1457 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1460 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1462 struct resource dma_window;
1463 struct pci_controller *hose = NULL;
1464 const int *bus_range;
1465 int primary = 0, busses;
1466 void __iomem *mbase = NULL, *cfg_data = NULL;
1470 /* Check if primary bridge */
1471 if (of_get_property(port->node, "primary", NULL))
1474 /* Get bus range if any */
1475 bus_range = of_get_property(port->node, "bus-range", NULL);
1477 /* Allocate the host controller data structure */
1478 hose = pcibios_alloc_controller(port->node);
1482 /* We stick the port number in "indirect_type" so the config space
1483 * ops can retrieve the port data structure easily
1485 hose->indirect_type = port->index;
1488 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1489 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1491 /* Because of how big mapping the config space is (1M per bus), we
1492 * limit how many busses we support. In the long run, we could replace
1493 * that with something akin to kmap_atomic instead. We set aside 1 bus
1494 * for the host itself too.
1496 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1497 if (busses > MAX_PCIE_BUS_MAPPED) {
1498 busses = MAX_PCIE_BUS_MAPPED;
1499 hose->last_busno = hose->first_busno + busses;
1502 if (!port->endpoint) {
1503 /* Only map the external config space in cfg_data for
1504 * PCIe root-complexes. External space is 1M per bus
1506 cfg_data = ioremap(port->cfg_space.start +
1507 (hose->first_busno + 1) * 0x100000,
1509 if (cfg_data == NULL) {
1510 printk(KERN_ERR "%s: Can't map external config space !",
1511 port->node->full_name);
1514 hose->cfg_data = cfg_data;
1517 /* Always map the host config space in cfg_addr.
1518 * Internal space is 4K
1520 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1521 if (mbase == NULL) {
1522 printk(KERN_ERR "%s: Can't map internal config space !",
1523 port->node->full_name);
1526 hose->cfg_addr = mbase;
1528 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1529 hose->first_busno, hose->last_busno);
1530 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1531 hose->cfg_addr, hose->cfg_data);
1533 /* Setup config space */
1534 hose->ops = &ppc4xx_pciex_pci_ops;
1536 mbase = (void __iomem *)hose->cfg_addr;
1538 if (!port->endpoint) {
1540 * Set bus numbers on our root port
1542 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1543 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1544 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1548 * OMRs are already reset, also disable PIMs
1550 out_le32(mbase + PECFG_PIMEN, 0);
1552 /* Parse outbound mapping resources */
1553 pci_process_bridge_OF_ranges(hose, port->node, primary);
1555 /* Parse inbound mapping resources */
1556 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1559 /* Configure outbound ranges POMs */
1560 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1562 /* Configure inbound ranges PIMs */
1563 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1565 /* The root complex doesn't show up if we don't set some vendor
1566 * and device IDs into it. The defaults below are the same bogus
1567 * one that the initial code in arch/ppc had. This can be
1568 * overwritten by setting the "vendor-id/device-id" properties
1569 * in the pciex node.
1572 /* Get the (optional) vendor-/device-id from the device-tree */
1573 pval = of_get_property(port->node, "vendor-id", NULL);
1577 if (!port->endpoint)
1578 val = 0xaaa0 + port->index;
1580 val = 0xeee0 + port->index;
1582 out_le16(mbase + 0x200, val);
1584 pval = of_get_property(port->node, "device-id", NULL);
1588 if (!port->endpoint)
1589 val = 0xbed0 + port->index;
1591 val = 0xfed0 + port->index;
1593 out_le16(mbase + 0x202, val);
1595 if (!port->endpoint) {
1596 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1597 out_le32(mbase + 0x208, 0x06040001);
1599 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1602 /* Set Class Code to Processor/PPC */
1603 out_le32(mbase + 0x208, 0x0b200001);
1605 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1612 pcibios_free_controller(hose);
1619 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1621 struct ppc4xx_pciex_port *port;
1627 /* First, proceed to core initialization as we assume there's
1628 * only one PCIe core in the system
1630 if (ppc4xx_pciex_check_core_init(np))
1633 /* Get the port number from the device-tree */
1634 pval = of_get_property(np, "port", NULL);
1636 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1641 if (portno >= ppc4xx_pciex_port_count) {
1642 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1646 port = &ppc4xx_pciex_ports[portno];
1647 port->index = portno;
1650 * Check if device is enabled
1652 if (!of_device_is_available(np)) {
1653 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1657 port->node = of_node_get(np);
1658 pval = of_get_property(np, "sdr-base", NULL);
1660 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1664 port->sdr_base = *pval;
1666 /* Check if device_type property is set to "pci" or "pci-endpoint".
1667 * Resulting from this setup this PCIe port will be configured
1668 * as root-complex or as endpoint.
1670 val = of_get_property(port->node, "device_type", NULL);
1671 if (!strcmp(val, "pci-endpoint")) {
1673 } else if (!strcmp(val, "pci")) {
1676 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1681 /* Fetch config space registers address */
1682 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1683 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1687 /* Fetch host bridge internal registers address */
1688 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1689 printk(KERN_ERR "%s: Can't get UTL register base !",
1695 dcrs = dcr_resource_start(np, 0);
1697 printk(KERN_ERR "%s: Can't get DCR register base !",
1701 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1703 /* Initialize the port specific registers */
1704 if (ppc4xx_pciex_port_init(port)) {
1705 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1709 /* Setup the linux hose data structure */
1710 ppc4xx_pciex_port_setup_hose(port);
1713 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1715 static int __init ppc4xx_pci_find_bridges(void)
1717 struct device_node *np;
1719 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1720 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1721 ppc4xx_probe_pciex_bridge(np);
1723 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1724 ppc4xx_probe_pcix_bridge(np);
1725 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1726 ppc4xx_probe_pci_bridge(np);
1730 arch_initcall(ppc4xx_pci_find_bridges);