2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@cs.anu.edu.au)
14 * This file handles the architecture-dependent parts of hardware exceptions
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/a.out.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/prctl.h>
31 #include <linux/bug.h>
33 #include <asm/pgtable.h>
34 #include <asm/uaccess.h>
35 #include <asm/system.h>
42 extern int xmon_bpt(struct pt_regs *regs);
43 extern int xmon_sstep(struct pt_regs *regs);
44 extern int xmon_iabr_match(struct pt_regs *regs);
45 extern int xmon_dabr_match(struct pt_regs *regs);
47 int (*debugger)(struct pt_regs *regs) = xmon;
48 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
49 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
50 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
51 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
52 void (*debugger_fault_handler)(struct pt_regs *regs);
55 int (*debugger)(struct pt_regs *regs);
56 int (*debugger_bpt)(struct pt_regs *regs);
57 int (*debugger_sstep)(struct pt_regs *regs);
58 int (*debugger_iabr_match)(struct pt_regs *regs);
59 int (*debugger_dabr_match)(struct pt_regs *regs);
60 void (*debugger_fault_handler)(struct pt_regs *regs);
62 #define debugger(regs) do { } while (0)
63 #define debugger_bpt(regs) 0
64 #define debugger_sstep(regs) 0
65 #define debugger_iabr_match(regs) 0
66 #define debugger_dabr_match(regs) 0
67 #define debugger_fault_handler ((void (*)(struct pt_regs *))0)
72 * Trap & Exception support
75 DEFINE_SPINLOCK(die_lock);
77 int die(const char * str, struct pt_regs * fp, long err)
79 static int die_counter;
82 spin_lock_irq(&die_lock);
83 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
89 printk("SMP NR_CPUS=%d ", NR_CPUS);
96 spin_unlock_irq(&die_lock);
97 /* do_exit() should take care of panic'ing from an interrupt
98 * context so we don't handle it here
103 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
107 if (!user_mode(regs)) {
109 die("Exception in kernel mode", regs, signr);
111 info.si_signo = signr;
114 info.si_addr = (void __user *) addr;
115 force_sig_info(signr, &info, current);
118 * Init gets no signals that it doesn't have a handler for.
119 * That's all very well, but if it has caused a synchronous
120 * exception and we ignore the resulting signal, it will just
121 * generate the same exception over and over again and we get
122 * nowhere. Better to kill it and let the kernel panic.
124 if (is_global_init(current)) {
125 __sighandler_t handler;
127 spin_lock_irq(¤t->sighand->siglock);
128 handler = current->sighand->action[signr-1].sa.sa_handler;
129 spin_unlock_irq(¤t->sighand->siglock);
130 if (handler == SIG_DFL) {
131 /* init has generated a synchronous exception
132 and it doesn't have a handler for the signal */
133 printk(KERN_CRIT "init has generated signal %d "
134 "but has no handler for it\n", signr);
141 * I/O accesses can cause machine checks on powermacs.
142 * Check if the NIP corresponds to the address of a sync
143 * instruction for which there is an entry in the exception
145 * Note that the 601 only takes a machine check on TEA
146 * (transfer error ack) signal assertion, and does not
147 * set any of the top 16 bits of SRR1.
150 static inline int check_io_access(struct pt_regs *regs)
152 #if defined CONFIG_8xx
153 unsigned long msr = regs->msr;
154 const struct exception_table_entry *entry;
155 unsigned int *nip = (unsigned int *)regs->nip;
157 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
158 && (entry = search_exception_tables(regs->nip)) != NULL) {
160 * Check that it's a sync instruction, or somewhere
161 * in the twi; isync; nop sequence that inb/inw/inl uses.
162 * As the address is in the exception table
163 * we should be able to read the instr there.
164 * For the debug message, we look at the preceding
167 if (*nip == 0x60000000) /* nop */
169 else if (*nip == 0x4c00012c) /* isync */
171 /* eieio from I/O string functions */
172 else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
174 if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
175 (*(nip+1) >> 26) == 3) {
180 rb = (*nip >> 11) & 0x1f;
181 printk(KERN_DEBUG "%s bad port %lx at %p\n",
182 (*nip & 0x100)? "OUT to": "IN from",
183 regs->gpr[rb] - _IO_BASE, nip);
185 regs->nip = entry->fixup;
189 #endif /* CONFIG_8xx */
193 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
194 /* On 4xx, the reason for the machine check or program exception
196 #define get_reason(regs) ((regs)->dsisr)
197 #ifndef CONFIG_FSL_BOOKE
198 #define get_mc_reason(regs) ((regs)->dsisr)
200 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
202 #define REASON_FP ESR_FP
203 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
204 #define REASON_PRIVILEGED ESR_PPR
205 #define REASON_TRAP ESR_PTR
207 /* single-step stuff */
208 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
209 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
212 /* On non-4xx, the reason for the machine check or program
213 exception is in the MSR. */
214 #define get_reason(regs) ((regs)->msr)
215 #define get_mc_reason(regs) ((regs)->msr)
216 #define REASON_FP 0x100000
217 #define REASON_ILLEGAL 0x80000
218 #define REASON_PRIVILEGED 0x40000
219 #define REASON_TRAP 0x20000
221 #define single_stepping(regs) ((regs)->msr & MSR_SE)
222 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
226 * This is "fall-back" implementation for configurations
227 * which don't provide platform-specific machine check info
229 void __attribute__ ((weak))
230 platform_machine_check(struct pt_regs *regs)
234 #if defined(CONFIG_4xx)
235 int machine_check_4xx(struct pt_regs *regs)
237 unsigned long reason = get_mc_reason(regs);
239 if (reason & ESR_IMCP) {
240 printk("Instruction");
241 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
244 printk(" machine check in kernel mode.\n");
249 int machine_check_440A(struct pt_regs *regs)
251 unsigned long reason = get_mc_reason(regs);
253 printk("Machine check in kernel mode.\n");
254 if (reason & ESR_IMCP){
255 printk("Instruction Synchronous Machine Check exception\n");
256 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
259 u32 mcsr = mfspr(SPRN_MCSR);
261 printk("Instruction Read PLB Error\n");
263 printk("Data Read PLB Error\n");
265 printk("Data Write PLB Error\n");
266 if (mcsr & MCSR_TLBP)
267 printk("TLB Parity Error\n");
268 if (mcsr & MCSR_ICP){
269 flush_instruction_cache();
270 printk("I-Cache Parity Error\n");
272 if (mcsr & MCSR_DCSP)
273 printk("D-Cache Search Parity Error\n");
274 if (mcsr & MCSR_DCFP)
275 printk("D-Cache Flush Parity Error\n");
276 if (mcsr & MCSR_IMPE)
277 printk("Machine Check exception is imprecise\n");
280 mtspr(SPRN_MCSR, mcsr);
284 #elif defined(CONFIG_E500)
285 int machine_check_e500(struct pt_regs *regs)
287 unsigned long reason = get_mc_reason(regs);
289 printk("Machine check in kernel mode.\n");
290 printk("Caused by (from MCSR=%lx): ", reason);
292 if (reason & MCSR_MCP)
293 printk("Machine Check Signal\n");
294 if (reason & MCSR_ICPERR)
295 printk("Instruction Cache Parity Error\n");
296 if (reason & MCSR_DCP_PERR)
297 printk("Data Cache Push Parity Error\n");
298 if (reason & MCSR_DCPERR)
299 printk("Data Cache Parity Error\n");
300 if (reason & MCSR_BUS_IAERR)
301 printk("Bus - Instruction Address Error\n");
302 if (reason & MCSR_BUS_RAERR)
303 printk("Bus - Read Address Error\n");
304 if (reason & MCSR_BUS_WAERR)
305 printk("Bus - Write Address Error\n");
306 if (reason & MCSR_BUS_IBERR)
307 printk("Bus - Instruction Data Error\n");
308 if (reason & MCSR_BUS_RBERR)
309 printk("Bus - Read Data Bus Error\n");
310 if (reason & MCSR_BUS_WBERR)
311 printk("Bus - Read Data Bus Error\n");
312 if (reason & MCSR_BUS_IPERR)
313 printk("Bus - Instruction Parity Error\n");
314 if (reason & MCSR_BUS_RPERR)
315 printk("Bus - Read Parity Error\n");
319 #elif defined(CONFIG_E200)
320 int machine_check_e200(struct pt_regs *regs)
322 unsigned long reason = get_mc_reason(regs);
324 printk("Machine check in kernel mode.\n");
325 printk("Caused by (from MCSR=%lx): ", reason);
327 if (reason & MCSR_MCP)
328 printk("Machine Check Signal\n");
329 if (reason & MCSR_CP_PERR)
330 printk("Cache Push Parity Error\n");
331 if (reason & MCSR_CPERR)
332 printk("Cache Parity Error\n");
333 if (reason & MCSR_EXCP_ERR)
334 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
335 if (reason & MCSR_BUS_IRERR)
336 printk("Bus - Read Bus Error on instruction fetch\n");
337 if (reason & MCSR_BUS_DRERR)
338 printk("Bus - Read Bus Error on data load\n");
339 if (reason & MCSR_BUS_WRERR)
340 printk("Bus - Write Bus Error on buffered store or cache line push\n");
345 int machine_check_generic(struct pt_regs *regs)
347 unsigned long reason = get_mc_reason(regs);
349 printk("Machine check in kernel mode.\n");
350 printk("Caused by (from SRR1=%lx): ", reason);
351 switch (reason & 0x601F0000) {
353 printk("Machine check signal\n");
355 case 0: /* for 601 */
357 case 0x140000: /* 7450 MSS error and TEA */
358 printk("Transfer error ack signal\n");
361 printk("Data parity error signal\n");
364 printk("Address parity error signal\n");
367 printk("L1 Data Cache error\n");
370 printk("L1 Instruction Cache error\n");
373 printk("L2 data cache parity error\n");
376 printk("Unknown values in msr\n");
380 #endif /* everything else */
382 void machine_check_exception(struct pt_regs *regs)
386 if (cur_cpu_spec->machine_check)
387 recover = cur_cpu_spec->machine_check(regs);
391 if (user_mode(regs)) {
393 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
397 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
398 /* the qspan pci read routines can cause machine checks -- Cort */
399 bad_page_fault(regs, regs->dar, SIGBUS);
403 if (debugger_fault_handler) {
404 debugger_fault_handler(regs);
409 if (check_io_access(regs))
413 * Optional platform-provided routine to print out
414 * additional info, e.g. bus error registers.
416 platform_machine_check(regs);
419 die("machine check", regs, SIGBUS);
422 void SMIException(struct pt_regs *regs)
425 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
427 panic("System Management Interrupt");
431 void unknown_exception(struct pt_regs *regs)
433 printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
434 regs->nip, regs->msr, regs->trap, print_tainted());
435 _exception(SIGTRAP, regs, 0, 0);
438 void instruction_breakpoint_exception(struct pt_regs *regs)
440 if (debugger_iabr_match(regs))
442 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
445 void RunModeException(struct pt_regs *regs)
447 _exception(SIGTRAP, regs, 0, 0);
450 /* Illegal instruction emulation support. Originally written to
451 * provide the PVR to user applications using the mfspr rd, PVR.
452 * Return non-zero if we can't emulate, or -EFAULT if the associated
453 * memory access caused an access fault. Return zero on success.
455 * There are a couple of ways to do this, either "decode" the instruction
456 * or directly match lots of bits. In this case, matching lots of
457 * bits is faster and easier.
460 #define INST_MFSPR_PVR 0x7c1f42a6
461 #define INST_MFSPR_PVR_MASK 0xfc1fffff
463 #define INST_DCBA 0x7c0005ec
464 #define INST_DCBA_MASK 0x7c0007fe
466 #define INST_MCRXR 0x7c000400
467 #define INST_MCRXR_MASK 0x7c0007fe
469 #define INST_STRING 0x7c00042a
470 #define INST_STRING_MASK 0x7c0007fe
471 #define INST_STRING_GEN_MASK 0x7c00067e
472 #define INST_LSWI 0x7c0004aa
473 #define INST_LSWX 0x7c00042a
474 #define INST_STSWI 0x7c0005aa
475 #define INST_STSWX 0x7c00052a
477 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
479 u8 rT = (instword >> 21) & 0x1f;
480 u8 rA = (instword >> 16) & 0x1f;
481 u8 NB_RB = (instword >> 11) & 0x1f;
486 /* Early out if we are an invalid form of lswx */
487 if ((instword & INST_STRING_MASK) == INST_LSWX)
488 if ((rT == rA) || (rT == NB_RB))
491 EA = (rA == 0) ? 0 : regs->gpr[rA];
493 switch (instword & INST_STRING_MASK) {
497 num_bytes = regs->xer & 0x7f;
501 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
507 while (num_bytes != 0)
510 u32 shift = 8 * (3 - (pos & 0x3));
512 switch ((instword & INST_STRING_MASK)) {
515 if (get_user(val, (u8 __user *)EA))
517 /* first time updating this reg,
521 regs->gpr[rT] |= val << shift;
525 val = regs->gpr[rT] >> shift;
526 if (put_user(val, (u8 __user *)EA))
530 /* move EA to next address */
534 /* manage our position within the register */
545 static int emulate_instruction(struct pt_regs *regs)
550 if (!user_mode(regs))
552 CHECK_FULL_REGS(regs);
554 if (get_user(instword, (u32 __user *)(regs->nip)))
557 /* Emulate the mfspr rD, PVR.
559 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
560 rd = (instword >> 21) & 0x1f;
561 regs->gpr[rd] = mfspr(SPRN_PVR);
565 /* Emulating the dcba insn is just a no-op. */
566 if ((instword & INST_DCBA_MASK) == INST_DCBA)
569 /* Emulate the mcrxr insn. */
570 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
571 int shift = (instword >> 21) & 0x1c;
572 unsigned long msk = 0xf0000000UL >> shift;
574 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
575 regs->xer &= ~0xf0000000UL;
579 /* Emulate load/store string insn. */
580 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
581 return emulate_string_inst(regs, instword);
587 * After we have successfully emulated an instruction, we have to
588 * check if the instruction was being single-stepped, and if so,
589 * pretend we got a single-step exception. This was pointed out
590 * by Kumar Gala. -- paulus
592 static void emulate_single_step(struct pt_regs *regs)
594 if (single_stepping(regs)) {
595 clear_single_step(regs);
596 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
600 int is_valid_bugaddr(unsigned long addr)
602 return addr >= PAGE_OFFSET;
605 void program_check_exception(struct pt_regs *regs)
607 unsigned int reason = get_reason(regs);
608 extern int do_mathemu(struct pt_regs *regs);
610 #ifdef CONFIG_MATH_EMULATION
611 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
612 * but there seems to be a hardware bug on the 405GP (RevD)
613 * that means ESR is sometimes set incorrectly - either to
614 * ESR_DST (!?) or 0. In the process of chasing this with the
615 * hardware people - not sure if it can happen on any illegal
616 * instruction or only on FP instructions, whether there is a
617 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
618 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
619 emulate_single_step(regs);
622 #endif /* CONFIG_MATH_EMULATION */
624 if (reason & REASON_FP) {
625 /* IEEE FP exception */
629 /* We must make sure the FP state is consistent with
633 if (regs->msr & MSR_FP)
637 fpscr = current->thread.fpscr.val;
638 fpscr &= fpscr << 22; /* mask summary bits with enables */
639 if (fpscr & FPSCR_VX)
641 else if (fpscr & FPSCR_OX)
643 else if (fpscr & FPSCR_UX)
645 else if (fpscr & FPSCR_ZX)
647 else if (fpscr & FPSCR_XX)
649 _exception(SIGFPE, regs, code, regs->nip);
653 if (reason & REASON_TRAP) {
655 if (debugger_bpt(regs))
658 if (!(regs->msr & MSR_PR) && /* not user-mode */
659 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
663 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
667 /* Try to emulate it if we should. */
668 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
669 switch (emulate_instruction(regs)) {
672 emulate_single_step(regs);
675 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
680 if (reason & REASON_PRIVILEGED)
681 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
683 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
686 void single_step_exception(struct pt_regs *regs)
688 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
689 if (debugger_sstep(regs))
691 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
694 void alignment_exception(struct pt_regs *regs)
696 int sig, code, fixed = 0;
698 fixed = fix_alignment(regs);
700 regs->nip += 4; /* skip over emulated instruction */
701 emulate_single_step(regs);
704 if (fixed == -EFAULT) {
712 _exception(sig, regs, code, regs->dar);
714 bad_page_fault(regs, regs->dar, sig);
717 void StackOverflow(struct pt_regs *regs)
719 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
720 current, regs->gpr[1]);
723 panic("kernel stack overflow");
726 void nonrecoverable_exception(struct pt_regs *regs)
728 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
729 regs->nip, regs->msr);
731 die("nonrecoverable exception", regs, SIGKILL);
734 void trace_syscall(struct pt_regs *regs)
736 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
737 current, current->pid, regs->nip, regs->link, regs->gpr[0],
738 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
742 void SoftwareEmulation(struct pt_regs *regs)
744 extern int do_mathemu(struct pt_regs *);
745 extern int Soft_emulate_8xx(struct pt_regs *);
748 CHECK_FULL_REGS(regs);
750 if (!user_mode(regs)) {
752 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
755 #ifdef CONFIG_MATH_EMULATION
756 errcode = do_mathemu(regs);
758 errcode = Soft_emulate_8xx(regs);
762 _exception(SIGFPE, regs, 0, 0);
763 else if (errcode == -EFAULT)
764 _exception(SIGSEGV, regs, 0, 0);
766 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
768 emulate_single_step(regs);
770 #endif /* CONFIG_8xx */
772 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
774 void DebugException(struct pt_regs *regs, unsigned long debug_status)
776 if (debug_status & DBSR_IC) { /* instruction completion */
777 regs->msr &= ~MSR_DE;
778 if (user_mode(regs)) {
779 current->thread.dbcr0 &= ~DBCR0_IC;
781 /* Disable instruction completion */
782 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
783 /* Clear the instruction completion event */
784 mtspr(SPRN_DBSR, DBSR_IC);
785 if (debugger_sstep(regs))
788 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
791 #endif /* CONFIG_4xx || CONFIG_BOOKE */
793 #if !defined(CONFIG_TAU_INT)
794 void TAUException(struct pt_regs *regs)
796 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
797 regs->nip, regs->msr, regs->trap, print_tainted());
799 #endif /* CONFIG_INT_TAU */
802 * FP unavailable trap from kernel - print a message, but let
803 * the task use FP in the kernel until it returns to user mode.
805 void kernel_fp_unavailable_exception(struct pt_regs *regs)
808 printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n",
812 void altivec_unavailable_exception(struct pt_regs *regs)
814 static int kernel_altivec_count;
816 #ifndef CONFIG_ALTIVEC
817 if (user_mode(regs)) {
818 /* A user program has executed an altivec instruction,
819 but this kernel doesn't support altivec. */
820 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
824 /* The kernel has executed an altivec instruction without
825 first enabling altivec. Whinge but let it do it. */
826 if (++kernel_altivec_count < 10)
827 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
829 regs->msr |= MSR_VEC;
832 #ifdef CONFIG_ALTIVEC
833 void altivec_assist_exception(struct pt_regs *regs)
838 if (regs->msr & MSR_VEC)
839 giveup_altivec(current);
841 if (!user_mode(regs)) {
842 printk(KERN_ERR "altivec assist exception in kernel mode"
843 " at %lx\n", regs->nip);
845 die("altivec assist exception", regs, SIGFPE);
849 err = emulate_altivec(regs);
851 regs->nip += 4; /* skip emulated instruction */
852 emulate_single_step(regs);
856 if (err == -EFAULT) {
857 /* got an error reading the instruction */
858 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
860 /* didn't recognize the instruction */
861 /* XXX quick hack for now: set the non-Java bit in the VSCR */
862 printk(KERN_ERR "unrecognized altivec instruction "
863 "in %s at %lx\n", current->comm, regs->nip);
864 current->thread.vscr.u[3] |= 0x10000;
867 #endif /* CONFIG_ALTIVEC */
870 void performance_monitor_exception(struct pt_regs *regs)
876 #ifdef CONFIG_FSL_BOOKE
877 void CacheLockingException(struct pt_regs *regs, unsigned long address,
878 unsigned long error_code)
880 /* We treat cache locking instructions from the user
881 * as priv ops, in the future we could try to do
884 if (error_code & (ESR_DLK|ESR_ILK))
885 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
888 #endif /* CONFIG_FSL_BOOKE */
891 void SPEFloatingPointException(struct pt_regs *regs)
893 unsigned long spefscr;
897 spefscr = current->thread.spefscr;
898 fpexc_mode = current->thread.fpexc_mode;
900 /* Hardware does not necessarily set sticky
901 * underflow/overflow/invalid flags */
902 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
904 spefscr |= SPEFSCR_FOVFS;
906 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
908 spefscr |= SPEFSCR_FUNFS;
910 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
912 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
914 spefscr |= SPEFSCR_FINVS;
916 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
919 current->thread.spefscr = spefscr;
921 _exception(SIGFPE, regs, code, regs->nip);
926 #ifdef CONFIG_BOOKE_WDT
928 * Default handler for a Watchdog exception,
929 * spins until a reboot occurs
931 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
933 /* Generic WatchdogHandler, implement your own */
934 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
938 void WatchdogException(struct pt_regs *regs)
940 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
941 WatchdogHandler(regs);
945 void __init trap_init(void)