arch/ppc/platforms/4xx/bamboo.c

   1 /*
   2  * arch/ppc/platforms/4xx/bamboo.c
   3  *
   4  * Bamboo board specific routines
   5  *
   6  * Wade Farnsworth <wfarnsworth@mvista.com>
   7  * Copyright 2004 MontaVista Software Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/types.h>
  24 #include <linux/major.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/console.h>
  27 #include <linux/delay.h>
  28 #include <linux/ide.h>
  29 #include <linux/initrd.h>
  30 #include <linux/irq.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33 #include <linux/tty.h>
  34 #include <linux/serial.h>
  35 #include <linux/serial_core.h>
  36 #include <linux/ethtool.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/dma.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/ocp.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/time.h>
  47 #include <asm/todc.h>
  48 #include <asm/bootinfo.h>
  49 #include <asm/ppc4xx_pic.h>
  50 #include <asm/ppcboot.h>
  51
  52 #include <syslib/gen550.h>
  53 #include <syslib/ibm440gx_common.h>
  54
  55 /*
  56  * This is a horrible kludge, we eventually need to abstract this
  57  * generic PHY stuff, so the  standard phy mode defines can be
  58  * easily used from arch code.
  59  */
  60 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
  61
  62 bd_t __res;
  63
  64 static struct ibm44x_clocks clocks __initdata;
  65
  66 /*
  67  * Bamboo external IRQ triggering/polarity settings
  68  */
  69 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
  76         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
  80 };
  81
  82 static void __init
  83 bamboo_calibrate_decr(void)
  84 {
  85         unsigned int freq;
  86
  87         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  88                 freq = BAMBOO_TMRCLK;
  89         else
  90                 freq = clocks.cpu;
  91
  92         ibm44x_calibrate_decr(freq);
  93
  94 }
  95
  96 static int
  97 bamboo_show_cpuinfo(struct seq_file *m)
  98 {
  99         seq_printf(m, "vendor\t\t: IBM\n");
 100         seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
 101
 102         return 0;
 103 }
 104
 105 static inline int
 106 bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 107 {
 108         static char pci_irq_table[][4] =
 109         /*
 110          *      PCI IDSEL/INTPIN->INTLINE
 111          *         A   B   C   D
 112          */
 113         {
 114                 { 28, 28, 28, 28 },     /* IDSEL 1 - PCI Slot 0 */
 115                 { 27, 27, 27, 27 },     /* IDSEL 2 - PCI Slot 1 */
 116                 { 26, 26, 26, 26 },     /* IDSEL 3 - PCI Slot 2 */
 117                 { 25, 25, 25, 25 },     /* IDSEL 4 - PCI Slot 3 */
 118         };
 119
 120         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 121         return PCI_IRQ_TABLE_LOOKUP;
 122 }
 123
 124 static void __init bamboo_set_emacdata(void)
 125 {
 126         u8 * base_addr;
 127         struct ocp_def *def;
 128         struct ocp_func_emac_data *emacdata;
 129         u8 val;
 130         int mode;
 131         u32 excluded = 0;
 132
 133         base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
 134         val = readb(base_addr);
 135         iounmap((void *) base_addr);
 136         if (BAMBOO_SEL_MII(val))
 137                 mode = PHY_MODE_MII;
 138         else if (BAMBOO_SEL_RMII(val))
 139                 mode = PHY_MODE_RMII;
 140         else
 141                 mode = PHY_MODE_SMII;
 142
 143         /*
 144          * SW2 on the Bamboo is used for ethernet configuration and is accessed
 145          * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
 146          * overwrite the supported features with the settings in SW2.
 147          *
 148          * This is used as a workaround for the improperly biased RJ-45 sockets
 149          * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
 150          * Removing inductors L17 and L18 from the board allows 100baseT, but
 151          * disables 10baseT.  The Rev. 1 has no such limitations.
 152          */
 153
 154         base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
 155         val = readb(base_addr);
 156         iounmap((void *) base_addr);
 157         if (!BAMBOO_AUTONEGOTIATE(val)) {
 158                 excluded |= SUPPORTED_Autoneg;
 159                 if (BAMBOO_FORCE_100Mbps(val)) {
 160                         excluded |= SUPPORTED_10baseT_Full;
 161                         excluded |= SUPPORTED_10baseT_Half;
 162                         if (BAMBOO_FULL_DUPLEX_EN(val))
 163                                 excluded |= SUPPORTED_100baseT_Half;
 164                         else
 165                                 excluded |= SUPPORTED_100baseT_Full;
 166                 } else {
 167                         excluded |= SUPPORTED_100baseT_Full;
 168                         excluded |= SUPPORTED_100baseT_Half;
 169                         if (BAMBOO_FULL_DUPLEX_EN(val))
 170                                 excluded |= SUPPORTED_10baseT_Half;
 171                         else
 172                                 excluded |= SUPPORTED_10baseT_Full;
 173                 }
 174         }
 175
 176         /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
 177
 178         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 179         emacdata = def->additions;
 180         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 181         emacdata->phy_mode = mode;
 182         emacdata->phy_feat_exc = excluded;
 183
 184         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 185         emacdata = def->additions;
 186         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 187         emacdata->phy_mode = mode;
 188         emacdata->phy_feat_exc = excluded;
 189 }
 190
 191 static int
 192 bamboo_exclude_device(unsigned char bus, unsigned char devfn)
 193 {
 194         return (bus == 0 && devfn == 0);
 195 }
 196
 197 #define PCI_READW(offset) \
 198         (readw((void *)((u32)pci_reg_base+offset)))
 199
 200 #define PCI_WRITEW(value, offset) \
 201         (writew(value, (void *)((u32)pci_reg_base+offset)))
 202
 203 #define PCI_WRITEL(value, offset) \
 204         (writel(value, (void *)((u32)pci_reg_base+offset)))
 205
 206 static void __init
 207 bamboo_setup_pci(void)
 208 {
 209         void *pci_reg_base;
 210         unsigned long memory_size;
 211         memory_size = ppc_md.find_end_of_memory();
 212
 213         pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
 214
 215         /* Enable PCI I/O, Mem, and Busmaster cycles */
 216         PCI_WRITEW(PCI_READW(PCI_COMMAND) |
 217                    PCI_COMMAND_MEMORY |
 218                    PCI_COMMAND_MASTER, PCI_COMMAND);
 219
 220         /* Disable region first */
 221         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
 222
 223         /* PLB starting addr: 0x00000000A0000000 */
 224         PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
 225
 226         /* PCI start addr, 0xA0000000 (PCI Address) */
 227         PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
 228         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
 229
 230         /* Enable no pre-fetch, enable region */
 231         PCI_WRITEL(((0xffffffff -
 232                      (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
 233                       BAMBOO_PCIL0_PMM0MA);
 234
 235         /* Disable region one */
 236         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 237         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
 238         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
 239         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
 240         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 241
 242         /* Disable region two */
 243         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 244         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
 245         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
 246         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
 247         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 248
 249         /* Now configure the PCI->PLB windows, we only use PTM1
 250          *
 251          * For Inbound flow, set the window size to all available memory
 252          * This is required because if size is smaller,
 253          * then Eth/PCI DD would fail as PCI card not able to access
 254          * the memory allocated by DD.
 255          */
 256
 257         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);     /* disabled region 1 */
 258         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);     /* begin of address map */
 259
 260         memory_size = 1 << fls(memory_size - 1);
 261
 262         /* Size low + Enabled */
 263         PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
 264
 265         eieio();
 266         iounmap(pci_reg_base);
 267 }
 268
 269 static void __init
 270 bamboo_setup_hose(void)
 271 {
 272         unsigned int bar_response, bar;
 273         struct pci_controller *hose;
 274
 275         bamboo_setup_pci();
 276
 277         hose = pcibios_alloc_controller();
 278
 279         if (!hose)
 280                 return;
 281
 282         hose->first_busno = 0;
 283         hose->last_busno = 0xff;
 284
 285         hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
 286
 287         pci_init_resource(&hose->io_resource,
 288                         BAMBOO_PCI_LOWER_IO,
 289                         BAMBOO_PCI_UPPER_IO,
 290                         IORESOURCE_IO,
 291                         "PCI host bridge");
 292
 293         pci_init_resource(&hose->mem_resources[0],
 294                         BAMBOO_PCI_LOWER_MEM,
 295                         BAMBOO_PCI_UPPER_MEM,
 296                         IORESOURCE_MEM,
 297                         "PCI host bridge");
 298
 299         ppc_md.pci_exclude_device = bamboo_exclude_device;
 300
 301         hose->io_space.start = BAMBOO_PCI_LOWER_IO;
 302         hose->io_space.end = BAMBOO_PCI_UPPER_IO;
 303         hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
 304         hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
 305         isa_io_base =
 306                 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
 307         hose->io_base_virt = (void *)isa_io_base;
 308
 309         setup_indirect_pci(hose,
 310                         BAMBOO_PCI_CFGA_PLB32,
 311                         BAMBOO_PCI_CFGD_PLB32);
 312         hose->set_cfg_type = 1;
 313
 314         /* Zero config bars */
 315         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 316                 early_write_config_dword(hose, hose->first_busno,
 317                                          PCI_FUNC(hose->first_busno), bar,
 318                                          0x00000000);
 319                 early_read_config_dword(hose, hose->first_busno,
 320                                         PCI_FUNC(hose->first_busno), bar,
 321                                         &bar_response);
 322         }
 323
 324         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 325
 326         ppc_md.pci_swizzle = common_swizzle;
 327         ppc_md.pci_map_irq = bamboo_map_irq;
 328 }
 329
 330 TODC_ALLOC();
 331
 332 static void __init
 333 bamboo_early_serial_map(void)
 334 {
 335         struct uart_port port;
 336
 337         /* Setup ioremapped serial port access */
 338         memset(&port, 0, sizeof(port));
 339         port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
 340         port.irq = 0;
 341         port.uartclk = clocks.uart0;
 342         port.regshift = 0;
 343         port.iotype = SERIAL_IO_MEM;
 344         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 345         port.line = 0;
 346
 347         if (early_serial_setup(&port) != 0) {
 348                 printk("Early serial init of port 0 failed\n");
 349         }
 350
 351 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 352         /* Configure debug serial access */
 353         gen550_init(0, &port);
 354 #endif
 355
 356         port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
 357         port.irq = 1;
 358         port.uartclk = clocks.uart1;
 359         port.line = 1;
 360
 361         if (early_serial_setup(&port) != 0) {
 362                 printk("Early serial init of port 1 failed\n");
 363         }
 364
 365 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 366         /* Configure debug serial access */
 367         gen550_init(1, &port);
 368 #endif
 369
 370         port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
 371         port.irq = 3;
 372         port.uartclk = clocks.uart2;
 373         port.line = 2;
 374
 375         if (early_serial_setup(&port) != 0) {
 376                 printk("Early serial init of port 2 failed\n");
 377         }
 378
 379 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 380         /* Configure debug serial access */
 381         gen550_init(2, &port);
 382 #endif
 383
 384         port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
 385         port.irq = 4;
 386         port.uartclk = clocks.uart3;
 387         port.line = 3;
 388
 389         if (early_serial_setup(&port) != 0) {
 390                 printk("Early serial init of port 3 failed\n");
 391         }
 392 }
 393
 394 static void __init
 395 bamboo_setup_arch(void)
 396 {
 397
 398         bamboo_set_emacdata();
 399
 400         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 401         ocp_sys_info.opb_bus_freq = clocks.opb;
 402
 403         /* Setup TODC access */
 404         TODC_INIT(TODC_TYPE_DS1743,
 405                         0,
 406                         0,
 407                         ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
 408                         8);
 409
 410         /* init to some ~sane value until calibrate_delay() runs */
 411         loops_per_jiffy = 50000000/HZ;
 412
 413         /* Setup PCI host bridge */
 414         bamboo_setup_hose();
 415
 416 #ifdef CONFIG_BLK_DEV_INITRD
 417         if (initrd_start)
 418                 ROOT_DEV = Root_RAM0;
 419         else
 420 #endif
 421 #ifdef CONFIG_ROOT_NFS
 422                 ROOT_DEV = Root_NFS;
 423 #else
 424                 ROOT_DEV = Root_HDA1;
 425 #endif
 426
 427         bamboo_early_serial_map();
 428
 429         /* Identify the system */
 430         printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
 431 }
 432
 433 void __init platform_init(unsigned long r3, unsigned long r4,
 434                 unsigned long r5, unsigned long r6, unsigned long r7)
 435 {
 436         parse_bootinfo(find_bootinfo());
 437
 438         /*
 439          * If we were passed in a board information, copy it into the
 440          * residual data area.
 441          */
 442         if (r3)
 443                 __res = *(bd_t *)(r3 + KERNELBASE);
 444
 445
 446         ibm44x_platform_init();
 447
 448         ppc_md.setup_arch = bamboo_setup_arch;
 449         ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
 450         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 451
 452         ppc_md.calibrate_decr = bamboo_calibrate_decr;
 453         ppc_md.time_init = todc_time_init;
 454         ppc_md.set_rtc_time = todc_set_rtc_time;
 455         ppc_md.get_rtc_time = todc_get_rtc_time;
 456
 457         ppc_md.nvram_read_val = todc_direct_read_val;
 458         ppc_md.nvram_write_val = todc_direct_write_val;
 459 #ifdef CONFIG_KGDB
 460         ppc_md.early_serial_map = bamboo_early_serial_map;
 461 #endif
 462 }
 463