2 * arch/ppc/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
8 * Further modified for generic 8xx by Dan.
12 * bootup setup stuff..
15 #include <linux/config.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/user.h>
25 #include <linux/a.out.h>
26 #include <linux/tty.h>
27 #include <linux/major.h>
28 #include <linux/interrupt.h>
29 #include <linux/reboot.h>
30 #include <linux/init.h>
31 #include <linux/initrd.h>
32 #include <linux/ioport.h>
33 #include <linux/bootmem.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
37 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
38 #include <linux/mtd/partitions.h>
39 #include <linux/mtd/physmap.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/map.h>
46 #include <asm/residual.h>
48 #include <asm/pgtable.h>
49 #include <asm/mpc8xx.h>
50 #include <asm/8xx_immap.h>
51 #include <asm/machdep.h>
52 #include <asm/bootinfo.h>
55 #include <asm/ppc_sys.h>
57 #include "ppc8xx_pic.h"
59 #ifdef CONFIG_MTD_PHYSMAP
60 #define MPC8xxADS_BANK_WIDTH 4
63 #define MPC8xxADS_U_BOOT_SIZE 0x80000
64 #define MPC8xxADS_FREE_AREA_OFFSET MPC8xxADS_U_BOOT_SIZE
66 #if defined(CONFIG_MTD_PARTITIONS)
68 NOTE: bank width and interleave relative to the installed flash
69 should have been chosen within MTD_CFI_GEOMETRY options.
71 static struct mtd_partition mpc8xxads_partitions[] = {
74 .size = MPC8xxADS_U_BOOT_SIZE,
76 .mask_flags = MTD_WRITEABLE, /* force read-only */
79 .offset = MPC8xxADS_FREE_AREA_OFFSET
83 #define mpc8xxads_part_num (sizeof (mpc8xxads_partitions) / sizeof (mpc8xxads_partitions[0]))
87 static int m8xx_set_rtc_time(unsigned long time);
88 static unsigned long m8xx_get_rtc_time(void);
89 void m8xx_calibrate_decr(void);
91 unsigned char __res[sizeof(bd_t)];
93 extern void m8xx_ide_init(void);
95 extern unsigned long find_available_memory(void);
96 extern void m8xx_cpm_reset(void);
97 extern void m8xx_wdt_handler_install(bd_t *bp);
98 extern void rpxfb_alloc_pages(void);
99 extern void cpm_interrupt_init(void);
101 void __attribute__ ((weak))
107 m8xx_setup_arch(void)
109 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
110 bd_t *binfo = (bd_t *)__res;
113 /* Reset the Communication Processor Module.
122 ROOT_DEV = Root_HDA1; /* hda1 */
125 #ifdef CONFIG_BLK_DEV_INITRD
127 ROOT_DEV = Root_FD0; /* floppy */
132 #if 0 /* XXX this may need to be updated for the new bootmem stuff,
133 or possibly just deleted (see set_phys_avail() in init.c).
135 /* initrd_start and size are setup by boot/head.S and kernel/head.S */
138 if (initrd_end > *memory_end_p)
140 printk("initrd extends beyond end of memory "
141 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
142 initrd_end,*memory_end_p);
149 #if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
150 #if defined(CONFIG_MTD_PHYSMAP)
151 physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
152 MPC8xxADS_BANK_WIDTH, NULL);
153 #ifdef CONFIG_MTD_PARTITIONS
154 physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
155 #endif /* CONFIG_MTD_PARTITIONS */
156 #endif /* CONFIG_MTD_PHYSMAP */
168 machine_restart(NULL);
174 /* A place holder for time base interrupts, if they are ever enabled. */
175 irqreturn_t timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
177 printk ("timebase_interrupt()\n");
182 static struct irqaction tbint_irqaction = {
183 .handler = timebase_interrupt,
184 .mask = CPU_MASK_NONE,
188 /* per-board overridable init_internal_rtc() function. */
189 void __init __attribute__ ((weak))
190 init_internal_rtc(void)
192 /* Disable the RTC one second and alarm interrupts. */
193 clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
196 setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
200 /* The decrementer counts at the system (internal) clock frequency divided by
201 * sixteen, or external oscillator divided by four. We force the processor
202 * to use system clock divided by sixteen.
204 void __init m8xx_calibrate_decr(void)
206 bd_t *binfo = (bd_t *)__res;
207 int freq, fp, divisor;
209 /* Unlock the SCCR. */
210 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
211 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
213 /* Force all 8xx processors to use divide by 16 processor clock. */
214 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
215 /* Processor frequency is MHz.
216 * The value 'fp' is the number of decrementer ticks per second.
218 fp = binfo->bi_intfreq / 16;
219 freq = fp*60; /* try to make freq/1e6 an integer */
221 printk("Decrementer Frequency = %d/%d\n", freq, divisor);
222 tb_ticks_per_jiffy = freq / HZ / divisor;
223 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
225 /* Perform some more timer/timebase initialization. This used
226 * to be done elsewhere, but other changes caused it to get
227 * called more than once....that is a bad thing.
229 * First, unlock all of the registers we are going to modify.
230 * To protect them from corruption during power down, registers
231 * that are maintained by keep alive power are "locked". To
232 * modify these registers we have to write the key value to
233 * the key location associated with the register.
234 * Some boards power up with these unlocked, while others
235 * are locked. Writing anything (including the unlock code?)
236 * to the unlocked registers will lock them again. So, here
237 * we guarantee the registers are locked, then we unlock them
240 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
241 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
242 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
243 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
244 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
245 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
249 /* Enabling the decrementer also enables the timebase interrupts
250 * (or from the other point of view, to get decrementer interrupts
251 * we have to enable the timebase). The decrementer interrupt
252 * is wired into the vector table, nothing to do here for that.
254 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
256 if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
257 panic("Could not allocate timer IRQ!");
259 #ifdef CONFIG_8xx_WDT
260 /* Install watchdog timer handler early because it might be
261 * already enabled by the bootloader
263 m8xx_wdt_handler_install(binfo);
267 /* The RTC on the MPC8xx is an internal register.
268 * We want to protect this during power down, so we need to unlock,
269 * modify, and re-lock.
272 m8xx_set_rtc_time(unsigned long time)
274 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
275 out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
276 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
281 m8xx_get_rtc_time(void)
283 /* Get time from the RTC. */
284 return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
288 m8xx_restart(char *cmd)
290 __volatile__ unsigned char dummy;
294 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
295 /* Clear the ME bit in MSR to cause checkstop on machine check
297 mtmsr(mfmsr() & ~0x1000);
299 dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
300 printk("Restart failed\n");
318 m8xx_show_percpuinfo(struct seq_file *m, int i)
324 seq_printf(m, "clock\t\t: %uMHz\n"
325 "bus clock\t: %uMHz\n",
326 bp->bi_intfreq / 1000000,
327 bp->bi_busfreq / 1000000);
333 static struct irqaction mbx_i8259_irqaction = {
334 .handler = mbx_i8259_action,
335 .mask = CPU_MASK_NONE,
336 .name = "i8259 cascade",
340 /* Initialize the internal interrupt controller. The number of
341 * interrupts supported can vary with the processor type, and the
342 * 82xx family can have up to 64.
343 * External interrupts can be either edge or level triggered, and
344 * need to be initialized by the appropriate driver.
351 for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
352 irq_desc[i].handler = &ppc8xx_pic;
354 cpm_interrupt_init();
356 #if defined(CONFIG_PCI)
357 for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
358 irq_desc[i].handler = &i8259_pic;
360 i8259_pic_irq_offset = I8259_IRQ_OFFSET;
363 /* The i8259 cascade interrupt must be level sensitive. */
365 clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
366 if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
367 enable_irq(ISA_BRIDGE_INT);
368 #endif /* CONFIG_PCI */
371 /* -------------------------------------------------------------------- */
374 * This is a big hack right now, but it may turn into something real
377 * For the 8xx boards (at this time anyway), there is nothing to initialize
378 * associated the PROM. Rather than include all of the prom.c
379 * functions in the image just to get prom_init, all we really need right
380 * now is the initialization of the physical memory region.
382 static unsigned long __init
383 m8xx_find_end_of_memory(void)
386 extern unsigned char __res[];
388 binfo = (bd_t *)__res;
390 return binfo->bi_memsize;
394 * Now map in some of the I/O space that is generically needed
395 * or shared with multiple devices.
396 * All of this fits into the same 4Mbyte region, so it only
397 * requires one page table page. (or at least it used to -- paulus)
402 io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
404 io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
405 io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
406 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
408 /* Map some of the PCI/ISA I/O space to get the IDE interface.
410 io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
411 io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
413 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
414 io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
415 #if !defined(CONFIG_PCI)
416 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
419 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
420 io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
423 io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
426 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
428 #if defined(CONFIG_NETTA)
429 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
434 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
435 unsigned long r6, unsigned long r7)
437 parse_bootinfo(find_bootinfo());
440 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
443 m8xx_setup_pci_ptrs();
446 #ifdef CONFIG_BLK_DEV_INITRD
447 /* take care of initrd if we have one */
450 initrd_start = r4 + KERNELBASE;
451 initrd_end = r5 + KERNELBASE;
453 #endif /* CONFIG_BLK_DEV_INITRD */
454 /* take care of cmd line */
457 *(char *)(r7+KERNELBASE) = 0;
458 strcpy(cmd_line, (char *)(r6+KERNELBASE));
461 identify_ppc_sys_by_name(BOARD_CHIP_NAME);
463 ppc_md.setup_arch = m8xx_setup_arch;
464 ppc_md.show_percpuinfo = m8xx_show_percpuinfo;
465 ppc_md.init_IRQ = m8xx_init_IRQ;
466 ppc_md.get_irq = m8xx_get_irq;
469 ppc_md.restart = m8xx_restart;
470 ppc_md.power_off = m8xx_power_off;
471 ppc_md.halt = m8xx_halt;
473 ppc_md.time_init = NULL;
474 ppc_md.set_rtc_time = m8xx_set_rtc_time;
475 ppc_md.get_rtc_time = m8xx_get_rtc_time;
476 ppc_md.calibrate_decr = m8xx_calibrate_decr;
478 ppc_md.find_end_of_memory = m8xx_find_end_of_memory;
479 ppc_md.setup_io_mappings = m8xx_map_io;
481 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE)