2 * MPC85xx Device descriptions
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/serial_8250.h>
18 #include <linux/fsl_devices.h>
19 #include <linux/fs_enet_pd.h>
20 #include <asm/mpc85xx.h>
22 #include <asm/ppc_sys.h>
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
28 struct gianfar_mdio_data mpc85xx_mdio_pdata = {
31 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
37 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
43 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
51 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
59 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
75 static struct gianfar_platform_data mpc85xx_fec_pdata = {
79 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
87 static struct fs_platform_info mpc85xx_fcc1_pdata = {
89 .cp_page = CPM_CR_FCC1_PAGE,
90 .cp_block = CPM_CR_FCC1_SBLOCK,
98 .clk_mask = CMX1_CLK_MASK,
99 .clk_route = CMX1_CLK_ROUTE,
100 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
102 .mem_offset = FCC1_MEM_OFFSET,
105 static struct fs_platform_info mpc85xx_fcc2_pdata = {
107 .cp_page = CPM_CR_FCC2_PAGE,
108 .cp_block = CPM_CR_FCC2_SBLOCK,
116 .clk_mask = CMX2_CLK_MASK,
117 .clk_route = CMX2_CLK_ROUTE,
118 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
120 .mem_offset = FCC2_MEM_OFFSET,
123 static struct fs_platform_info mpc85xx_fcc3_pdata = {
125 .cp_page = CPM_CR_FCC3_PAGE,
126 .cp_block = CPM_CR_FCC3_SBLOCK,
134 .clk_mask = CMX3_CLK_MASK,
135 .clk_route = CMX3_CLK_ROUTE,
136 .clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
138 .mem_offset = FCC3_MEM_OFFSET,
141 static struct plat_serial8250_port serial_platform_data[] = {
144 .irq = MPC85xx_IRQ_DUART,
146 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
150 .irq = MPC85xx_IRQ_DUART,
152 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
157 struct platform_device ppc_sys_platform_devices[] = {
159 .name = "fsl-gianfar",
161 .dev.platform_data = &mpc85xx_tsec1_pdata,
163 .resource = (struct resource[]) {
165 .start = MPC85xx_ENET1_OFFSET,
166 .end = MPC85xx_ENET1_OFFSET +
167 MPC85xx_ENET1_SIZE - 1,
168 .flags = IORESOURCE_MEM,
172 .start = MPC85xx_IRQ_TSEC1_TX,
173 .end = MPC85xx_IRQ_TSEC1_TX,
174 .flags = IORESOURCE_IRQ,
178 .start = MPC85xx_IRQ_TSEC1_RX,
179 .end = MPC85xx_IRQ_TSEC1_RX,
180 .flags = IORESOURCE_IRQ,
184 .start = MPC85xx_IRQ_TSEC1_ERROR,
185 .end = MPC85xx_IRQ_TSEC1_ERROR,
186 .flags = IORESOURCE_IRQ,
191 .name = "fsl-gianfar",
193 .dev.platform_data = &mpc85xx_tsec2_pdata,
195 .resource = (struct resource[]) {
197 .start = MPC85xx_ENET2_OFFSET,
198 .end = MPC85xx_ENET2_OFFSET +
199 MPC85xx_ENET2_SIZE - 1,
200 .flags = IORESOURCE_MEM,
204 .start = MPC85xx_IRQ_TSEC2_TX,
205 .end = MPC85xx_IRQ_TSEC2_TX,
206 .flags = IORESOURCE_IRQ,
210 .start = MPC85xx_IRQ_TSEC2_RX,
211 .end = MPC85xx_IRQ_TSEC2_RX,
212 .flags = IORESOURCE_IRQ,
216 .start = MPC85xx_IRQ_TSEC2_ERROR,
217 .end = MPC85xx_IRQ_TSEC2_ERROR,
218 .flags = IORESOURCE_IRQ,
223 .name = "fsl-gianfar",
225 .dev.platform_data = &mpc85xx_fec_pdata,
227 .resource = (struct resource[]) {
229 .start = MPC85xx_ENET3_OFFSET,
230 .end = MPC85xx_ENET3_OFFSET +
231 MPC85xx_ENET3_SIZE - 1,
232 .flags = IORESOURCE_MEM,
236 .start = MPC85xx_IRQ_FEC,
237 .end = MPC85xx_IRQ_FEC,
238 .flags = IORESOURCE_IRQ,
245 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
247 .resource = (struct resource[]) {
249 .start = MPC85xx_IIC1_OFFSET,
250 .end = MPC85xx_IIC1_OFFSET +
251 MPC85xx_IIC1_SIZE - 1,
252 .flags = IORESOURCE_MEM,
255 .start = MPC85xx_IRQ_IIC1,
256 .end = MPC85xx_IRQ_IIC1,
257 .flags = IORESOURCE_IRQ,
265 .resource = (struct resource[]) {
267 .start = MPC85xx_DMA0_OFFSET,
268 .end = MPC85xx_DMA0_OFFSET +
269 MPC85xx_DMA0_SIZE - 1,
270 .flags = IORESOURCE_MEM,
273 .start = MPC85xx_IRQ_DMA0,
274 .end = MPC85xx_IRQ_DMA0,
275 .flags = IORESOURCE_IRQ,
283 .resource = (struct resource[]) {
285 .start = MPC85xx_DMA1_OFFSET,
286 .end = MPC85xx_DMA1_OFFSET +
287 MPC85xx_DMA1_SIZE - 1,
288 .flags = IORESOURCE_MEM,
291 .start = MPC85xx_IRQ_DMA1,
292 .end = MPC85xx_IRQ_DMA1,
293 .flags = IORESOURCE_IRQ,
301 .resource = (struct resource[]) {
303 .start = MPC85xx_DMA2_OFFSET,
304 .end = MPC85xx_DMA2_OFFSET +
305 MPC85xx_DMA2_SIZE - 1,
306 .flags = IORESOURCE_MEM,
309 .start = MPC85xx_IRQ_DMA2,
310 .end = MPC85xx_IRQ_DMA2,
311 .flags = IORESOURCE_IRQ,
319 .resource = (struct resource[]) {
321 .start = MPC85xx_DMA3_OFFSET,
322 .end = MPC85xx_DMA3_OFFSET +
323 MPC85xx_DMA3_SIZE - 1,
324 .flags = IORESOURCE_MEM,
327 .start = MPC85xx_IRQ_DMA3,
328 .end = MPC85xx_IRQ_DMA3,
329 .flags = IORESOURCE_IRQ,
334 .name = "serial8250",
335 .id = PLAT8250_DEV_PLATFORM,
336 .dev.platform_data = serial_platform_data,
338 [MPC85xx_PERFMON] = {
339 .name = "fsl-perfmon",
342 .resource = (struct resource[]) {
344 .start = MPC85xx_PERFMON_OFFSET,
345 .end = MPC85xx_PERFMON_OFFSET +
346 MPC85xx_PERFMON_SIZE - 1,
347 .flags = IORESOURCE_MEM,
350 .start = MPC85xx_IRQ_PERFMON,
351 .end = MPC85xx_IRQ_PERFMON,
352 .flags = IORESOURCE_IRQ,
360 .resource = (struct resource[]) {
362 .start = MPC85xx_SEC2_OFFSET,
363 .end = MPC85xx_SEC2_OFFSET +
364 MPC85xx_SEC2_SIZE - 1,
365 .flags = IORESOURCE_MEM,
368 .start = MPC85xx_IRQ_SEC2,
369 .end = MPC85xx_IRQ_SEC2,
370 .flags = IORESOURCE_IRQ,
374 [MPC85xx_CPM_FCC1] = {
375 .name = "fsl-cpm-fcc",
378 .dev.platform_data = &mpc85xx_fcc1_pdata,
379 .resource = (struct resource[]) {
384 .flags = IORESOURCE_MEM,
387 .name = "fcc_regs_c",
390 .flags = IORESOURCE_MEM,
396 .flags = IORESOURCE_MEM,
399 .start = SIU_INT_FCC1,
401 .flags = IORESOURCE_IRQ,
405 [MPC85xx_CPM_FCC2] = {
406 .name = "fsl-cpm-fcc",
409 .dev.platform_data = &mpc85xx_fcc2_pdata,
410 .resource = (struct resource[]) {
415 .flags = IORESOURCE_MEM,
418 .name = "fcc_regs_c",
421 .flags = IORESOURCE_MEM,
427 .flags = IORESOURCE_MEM,
430 .start = SIU_INT_FCC2,
432 .flags = IORESOURCE_IRQ,
436 [MPC85xx_CPM_FCC3] = {
437 .name = "fsl-cpm-fcc",
440 .dev.platform_data = &mpc85xx_fcc3_pdata,
441 .resource = (struct resource[]) {
446 .flags = IORESOURCE_MEM,
449 .name = "fcc_regs_c",
452 .flags = IORESOURCE_MEM,
458 .flags = IORESOURCE_MEM,
461 .start = SIU_INT_FCC3,
463 .flags = IORESOURCE_IRQ,
467 [MPC85xx_CPM_I2C] = {
468 .name = "fsl-cpm-i2c",
471 .resource = (struct resource[]) {
475 .flags = IORESOURCE_MEM,
478 .start = SIU_INT_I2C,
480 .flags = IORESOURCE_IRQ,
484 [MPC85xx_CPM_SCC1] = {
485 .name = "fsl-cpm-scc",
488 .resource = (struct resource[]) {
492 .flags = IORESOURCE_MEM,
495 .start = SIU_INT_SCC1,
497 .flags = IORESOURCE_IRQ,
501 [MPC85xx_CPM_SCC2] = {
502 .name = "fsl-cpm-scc",
505 .resource = (struct resource[]) {
509 .flags = IORESOURCE_MEM,
512 .start = SIU_INT_SCC2,
514 .flags = IORESOURCE_IRQ,
518 [MPC85xx_CPM_SCC3] = {
519 .name = "fsl-cpm-scc",
522 .resource = (struct resource[]) {
526 .flags = IORESOURCE_MEM,
529 .start = SIU_INT_SCC3,
531 .flags = IORESOURCE_IRQ,
535 [MPC85xx_CPM_SCC4] = {
536 .name = "fsl-cpm-scc",
539 .resource = (struct resource[]) {
543 .flags = IORESOURCE_MEM,
546 .start = SIU_INT_SCC4,
548 .flags = IORESOURCE_IRQ,
552 [MPC85xx_CPM_SPI] = {
553 .name = "fsl-cpm-spi",
556 .resource = (struct resource[]) {
560 .flags = IORESOURCE_MEM,
563 .start = SIU_INT_SPI,
565 .flags = IORESOURCE_IRQ,
569 [MPC85xx_CPM_MCC1] = {
570 .name = "fsl-cpm-mcc",
573 .resource = (struct resource[]) {
577 .flags = IORESOURCE_MEM,
580 .start = SIU_INT_MCC1,
582 .flags = IORESOURCE_IRQ,
586 [MPC85xx_CPM_MCC2] = {
587 .name = "fsl-cpm-mcc",
590 .resource = (struct resource[]) {
594 .flags = IORESOURCE_MEM,
597 .start = SIU_INT_MCC2,
599 .flags = IORESOURCE_IRQ,
603 [MPC85xx_CPM_SMC1] = {
604 .name = "fsl-cpm-smc",
607 .resource = (struct resource[]) {
611 .flags = IORESOURCE_MEM,
614 .start = SIU_INT_SMC1,
616 .flags = IORESOURCE_IRQ,
620 [MPC85xx_CPM_SMC2] = {
621 .name = "fsl-cpm-smc",
624 .resource = (struct resource[]) {
628 .flags = IORESOURCE_MEM,
631 .start = SIU_INT_SMC2,
633 .flags = IORESOURCE_IRQ,
637 [MPC85xx_CPM_USB] = {
638 .name = "fsl-cpm-usb",
641 .resource = (struct resource[]) {
645 .flags = IORESOURCE_MEM,
648 .start = SIU_INT_USB,
650 .flags = IORESOURCE_IRQ,
655 .name = "fsl-gianfar",
657 .dev.platform_data = &mpc85xx_etsec1_pdata,
659 .resource = (struct resource[]) {
661 .start = MPC85xx_ENET1_OFFSET,
662 .end = MPC85xx_ENET1_OFFSET +
663 MPC85xx_ENET1_SIZE - 1,
664 .flags = IORESOURCE_MEM,
668 .start = MPC85xx_IRQ_TSEC1_TX,
669 .end = MPC85xx_IRQ_TSEC1_TX,
670 .flags = IORESOURCE_IRQ,
674 .start = MPC85xx_IRQ_TSEC1_RX,
675 .end = MPC85xx_IRQ_TSEC1_RX,
676 .flags = IORESOURCE_IRQ,
680 .start = MPC85xx_IRQ_TSEC1_ERROR,
681 .end = MPC85xx_IRQ_TSEC1_ERROR,
682 .flags = IORESOURCE_IRQ,
687 .name = "fsl-gianfar",
689 .dev.platform_data = &mpc85xx_etsec2_pdata,
691 .resource = (struct resource[]) {
693 .start = MPC85xx_ENET2_OFFSET,
694 .end = MPC85xx_ENET2_OFFSET +
695 MPC85xx_ENET2_SIZE - 1,
696 .flags = IORESOURCE_MEM,
700 .start = MPC85xx_IRQ_TSEC2_TX,
701 .end = MPC85xx_IRQ_TSEC2_TX,
702 .flags = IORESOURCE_IRQ,
706 .start = MPC85xx_IRQ_TSEC2_RX,
707 .end = MPC85xx_IRQ_TSEC2_RX,
708 .flags = IORESOURCE_IRQ,
712 .start = MPC85xx_IRQ_TSEC2_ERROR,
713 .end = MPC85xx_IRQ_TSEC2_ERROR,
714 .flags = IORESOURCE_IRQ,
719 .name = "fsl-gianfar",
721 .dev.platform_data = &mpc85xx_etsec3_pdata,
723 .resource = (struct resource[]) {
725 .start = MPC85xx_ENET3_OFFSET,
726 .end = MPC85xx_ENET3_OFFSET +
727 MPC85xx_ENET3_SIZE - 1,
728 .flags = IORESOURCE_MEM,
732 .start = MPC85xx_IRQ_TSEC3_TX,
733 .end = MPC85xx_IRQ_TSEC3_TX,
734 .flags = IORESOURCE_IRQ,
738 .start = MPC85xx_IRQ_TSEC3_RX,
739 .end = MPC85xx_IRQ_TSEC3_RX,
740 .flags = IORESOURCE_IRQ,
744 .start = MPC85xx_IRQ_TSEC3_ERROR,
745 .end = MPC85xx_IRQ_TSEC3_ERROR,
746 .flags = IORESOURCE_IRQ,
751 .name = "fsl-gianfar",
753 .dev.platform_data = &mpc85xx_etsec4_pdata,
755 .resource = (struct resource[]) {
759 .flags = IORESOURCE_MEM,
763 .start = MPC85xx_IRQ_TSEC4_TX,
764 .end = MPC85xx_IRQ_TSEC4_TX,
765 .flags = IORESOURCE_IRQ,
769 .start = MPC85xx_IRQ_TSEC4_RX,
770 .end = MPC85xx_IRQ_TSEC4_RX,
771 .flags = IORESOURCE_IRQ,
775 .start = MPC85xx_IRQ_TSEC4_ERROR,
776 .end = MPC85xx_IRQ_TSEC4_ERROR,
777 .flags = IORESOURCE_IRQ,
784 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
786 .resource = (struct resource[]) {
790 .flags = IORESOURCE_MEM,
793 .start = MPC85xx_IRQ_IIC1,
794 .end = MPC85xx_IRQ_IIC1,
795 .flags = IORESOURCE_IRQ,
800 .name = "fsl-gianfar_mdio",
802 .dev.platform_data = &mpc85xx_mdio_pdata,
804 .resource = (struct resource[]) {
808 .flags = IORESOURCE_MEM,
814 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
816 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
820 static int __init mach_mpc85xx_init(void)
822 ppc_sys_device_fixup = mach_mpc85xx_fixup;
826 postcore_initcall(mach_mpc85xx_init);