4 * Copyright (C) 2001 Allan Trautman, IBM Corporation
6 * iSeries specific routines for PCI.
8 * Based on code from pci.c and iSeries_pci.c 32bit
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/string.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/ide.h>
30 #include <linux/pci.h>
35 #include <asm/machdep.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/ppcdebug.h>
38 #include <asm/iommu.h>
40 #include <asm/iSeries/HvCallPci.h>
41 #include <asm/iSeries/HvCallSm.h>
42 #include <asm/iSeries/HvCallXm.h>
43 #include <asm/iSeries/iSeries_irq.h>
44 #include <asm/iSeries/iSeries_pci.h>
45 #include <asm/iSeries/mf.h>
49 extern unsigned long io_page_mask;
52 * Forward declares of prototypes.
54 static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
55 static void scan_PHB_slots(struct pci_controller *Phb);
56 static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
57 static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
59 LIST_HEAD(iSeries_Global_Device_List);
61 static int DeviceCount;
63 /* Counters and control flags. */
64 static long Pci_Io_Read_Count;
65 static long Pci_Io_Write_Count;
67 static long Pci_Cfg_Read_Count;
68 static long Pci_Cfg_Write_Count;
70 static long Pci_Error_Count;
72 static int Pci_Retry_Max = 3; /* Only retry 3 times */
73 static int Pci_Error_Flag = 1; /* Set Retry Error on. */
75 static struct pci_ops iSeries_pci_ops;
79 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
81 #define IOMM_TABLE_MAX_ENTRIES 1024
82 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
83 #define BASE_IO_MEMORY 0xE000000000000000UL
85 static unsigned long max_io_memory = 0xE000000000000000UL;
86 static long current_iomm_table_entry;
91 static struct iSeries_Device_Node **iomm_table;
92 static u8 *iobar_table;
95 * Static and Global variables
97 static char *pci_io_text = "iSeries PCI I/O";
98 static DEFINE_SPINLOCK(iomm_table_lock);
101 * iomm_table_initialize
103 * Allocates and initalizes the Address Translation Table and Bar
104 * Tables to get them ready for use. Must be called before any
105 * I/O space is handed out to the device BARs.
107 static void iomm_table_initialize(void)
109 spin_lock(&iomm_table_lock);
110 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
112 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
114 spin_unlock(&iomm_table_lock);
115 if ((iomm_table == NULL) || (iobar_table == NULL))
116 panic("PCI: I/O tables allocation failed.\n");
120 * iomm_table_allocate_entry
122 * Adds pci_dev entry in address translation table
124 * - Allocates the number of entries required in table base on BAR
126 * - Allocates starting at BASE_IO_MEMORY and increases.
127 * - The size is round up to be a multiple of entry size.
128 * - CurrentIndex is incremented to keep track of the last entry.
129 * - Builds the resource entry for allocated BARs.
131 static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
133 struct resource *bar_res = &dev->resource[bar_num];
134 long bar_size = pci_resource_len(dev, bar_num);
137 * No space to allocate, quick exit, skip Allocation.
142 * Set Resource values.
144 spin_lock(&iomm_table_lock);
145 bar_res->name = pci_io_text;
147 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
148 bar_res->start += BASE_IO_MEMORY;
149 bar_res->end = bar_res->start + bar_size - 1;
151 * Allocate the number of table entries needed for BAR.
153 while (bar_size > 0 ) {
154 iomm_table[current_iomm_table_entry] = dev->sysdata;
155 iobar_table[current_iomm_table_entry] = bar_num;
156 bar_size -= IOMM_TABLE_ENTRY_SIZE;
157 ++current_iomm_table_entry;
159 max_io_memory = BASE_IO_MEMORY +
160 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
161 spin_unlock(&iomm_table_lock);
165 * allocate_device_bars
167 * - Allocates ALL pci_dev BAR's and updates the resources with the
168 * BAR value. BARS with zero length will have the resources
169 * The HvCallPci_getBarParms is used to get the size of the BAR
170 * space. It calls iomm_table_allocate_entry to allocate
172 * - Loops through The Bar resources(0 - 5) including the ROM
175 static void allocate_device_bars(struct pci_dev *dev)
177 struct resource *bar_res;
180 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
181 bar_res = &dev->resource[bar_num];
182 iomm_table_allocate_entry(dev, bar_num);
187 * Log error information to system console.
188 * Filter out the device not there errors.
189 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
190 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
191 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
193 static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
194 int AgentId, int HvRc)
198 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
199 Error_Text, Bus, SubBus, AgentId, HvRc);
203 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
205 static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
206 HvSubBusNumber SubBus, int AgentId, int Function)
208 struct iSeries_Device_Node *node;
210 PPCDBG(PPCDBG_BUSWALK,
211 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
212 Bus, SubBus, AgentId, Function);
214 node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
218 memset(node, 0, sizeof(struct iSeries_Device_Node));
219 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
221 node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
223 node->DsaAddr.DsaAddr = 0;
224 node->DsaAddr.Dsa.busNumber = Bus;
225 node->DsaAddr.Dsa.subBusNumber = SubBus;
226 node->DsaAddr.Dsa.deviceId = 0x10;
227 node->AgentId = AgentId;
228 node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
230 iSeries_Get_Location_Code(node);
235 * unsigned long __init find_and_init_phbs(void)
238 * This function checks for all possible system PCI host bridges that connect
239 * PCI buses. The system hypervisor is queried as to the guest partition
240 * ownership status. A pci_controller is built for any bus which is partially
241 * owned or fully owned by this guest partition.
243 unsigned long __init find_and_init_phbs(void)
245 struct pci_controller *phb;
248 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
250 /* Check all possible buses. */
251 for (bus = 0; bus < 256; bus++) {
252 int ret = HvCallXm_testBus(bus);
254 printk("bus %d appears to exist\n", bus);
256 phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
259 pci_setup_pci_controller(phb);
261 phb->pci_mem_offset = phb->local_number = bus;
262 phb->first_busno = bus;
263 phb->last_busno = bus;
264 phb->ops = &iSeries_pci_ops;
266 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
269 /* Find and connect the devices. */
273 * Check for Unexpected Return code, a clue that something
276 else if (ret != 0x0301)
277 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
284 * iSeries_pcibios_init
286 * Chance to initialize and structures or variable before PCI Bus walk.
288 void iSeries_pcibios_init(void)
290 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
291 iomm_table_initialize();
292 find_and_init_phbs();
294 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
298 * iSeries_pci_final_fixup(void)
300 void __init iSeries_pci_final_fixup(void)
302 struct pci_dev *pdev = NULL;
303 struct iSeries_Device_Node *node;
307 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
309 /* Fix up at the device node and pci_dev relationship */
310 mf_display_src(0xC9000100);
312 printk("pcibios_final_fixup\n");
313 for_each_pci_dev(pdev) {
314 node = find_Device_Node(pdev->bus->number, pdev->devfn);
315 printk("pci dev %p (%x.%x), node %p\n", pdev,
316 pdev->bus->number, pdev->devfn, node);
320 pdev->sysdata = (void *)node;
322 PPCDBG(PPCDBG_BUSWALK,
323 "pdev 0x%p <==> DevNode 0x%p\n",
325 allocate_device_bars(pdev);
326 iSeries_Device_Information(pdev, Buffer,
328 printk("%d. %s\n", DeviceCount, Buffer);
329 iommu_devnode_init_iSeries(node);
331 printk("PCI: Device Tree not found for 0x%016lX\n",
332 (unsigned long)pdev);
333 pdev->irq = node->Irq;
335 iSeries_activate_IRQs();
336 mf_display_src(0xC9000200);
339 void pcibios_fixup_bus(struct pci_bus *PciBus)
341 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
345 void pcibios_fixup_resources(struct pci_dev *pdev)
347 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
351 * Loop through each node function to find usable EADs bridges.
353 static void scan_PHB_slots(struct pci_controller *Phb)
355 struct HvCallPci_DeviceInfo *DevInfo;
356 HvBusNumber bus = Phb->local_number; /* System Bus */
357 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
360 const int MaxAgents = 8;
362 DevInfo = (struct HvCallPci_DeviceInfo*)
363 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
368 * Probe for EADs Bridges
370 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
371 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
372 ISERIES_HV_ADDR(DevInfo),
373 sizeof(struct HvCallPci_DeviceInfo));
375 if (DevInfo->deviceType == HvCallPci_NodeDevice)
376 scan_EADS_bridge(bus, SubBus, IdSel);
378 printk("PCI: Invalid System Configuration(0x%02X)"
379 " for bus 0x%02x id 0x%02x.\n",
380 DevInfo->deviceType, bus, IdSel);
383 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
388 static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
391 struct HvCallPci_BridgeInfo *BridgeInfo;
396 BridgeInfo = (struct HvCallPci_BridgeInfo *)
397 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
398 if (BridgeInfo == NULL)
401 /* Note: hvSubBus and irq is always be 0 at this level! */
402 for (Function = 0; Function < 8; ++Function) {
403 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
404 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
406 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
407 bus, IdSel, Function, AgentId);
408 /* Connect EADs: 0x18.00.12 = 0x00 */
409 PPCDBG(PPCDBG_BUSWALK,
410 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
411 bus, SubBus, AgentId);
412 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
413 ISERIES_HV_ADDR(BridgeInfo),
414 sizeof(struct HvCallPci_BridgeInfo));
416 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
417 BridgeInfo->busUnitInfo.deviceType,
418 BridgeInfo->subBusNumber,
419 BridgeInfo->maxAgents,
420 BridgeInfo->maxSubBusNumber,
421 BridgeInfo->logicalSlotNumber);
422 PPCDBG(PPCDBG_BUSWALK,
423 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
424 BridgeInfo->busUnitInfo.deviceType,
425 BridgeInfo->subBusNumber,
426 BridgeInfo->maxAgents,
427 BridgeInfo->maxSubBusNumber,
428 BridgeInfo->logicalSlotNumber);
430 if (BridgeInfo->busUnitInfo.deviceType ==
431 HvCallPci_BridgeDevice) {
432 /* Scan_Bridge_Slot...: 0x18.00.12 */
433 scan_bridge_slot(bus, BridgeInfo);
435 printk("PCI: Invalid Bridge Configuration(0x%02X)",
436 BridgeInfo->busUnitInfo.deviceType);
438 } else if (HvRc != 0x000B)
439 pci_Log_Error("EADs Connect",
440 bus, SubBus, AgentId, HvRc);
446 * This assumes that the node slot is always on the primary bus!
448 static int scan_bridge_slot(HvBusNumber Bus,
449 struct HvCallPci_BridgeInfo *BridgeInfo)
451 struct iSeries_Device_Node *node;
452 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
456 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
457 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
458 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
460 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
461 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
462 PPCDBG(PPCDBG_BUSWALK,
463 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
464 Bus, 0, EADsIdSel, Irq);
467 * Connect all functions of any device found.
469 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
470 for (Function = 0; Function < 8; ++Function) {
471 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
472 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
475 pci_Log_Error("Connect Bus Unit",
476 Bus, SubBus, AgentId, HvRc);
480 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
481 PCI_VENDOR_ID, &VendorId);
483 pci_Log_Error("Read Vendor",
484 Bus, SubBus, AgentId, HvRc);
487 printk("read vendor ID: %x\n", VendorId);
489 /* FoundDevice: 0x18.28.10 = 0x12AE */
490 PPCDBG(PPCDBG_BUSWALK,
491 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
492 Bus, SubBus, AgentId, VendorId, Irq);
493 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
494 PCI_INTERRUPT_LINE, Irq);
496 pci_Log_Error("PciCfgStore Irq Failed!",
497 Bus, SubBus, AgentId, HvRc);
500 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
501 node->Vendor = VendorId;
503 node->LogicalSlot = BridgeInfo->logicalSlotNumber;
505 } /* for (Function = 0; Function < 8; ++Function) */
506 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
511 * I/0 Memory copy MUST use mmio commands on iSeries
512 * To do; For performance, include the hv call directly
514 void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
517 long NumberOfBytes = Count;
519 while (NumberOfBytes > 0) {
520 iSeries_Write_Byte(ByteValue, dest++);
524 EXPORT_SYMBOL(iSeries_memset_io);
526 void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
529 long NumberOfBytes = count;
531 while (NumberOfBytes > 0) {
532 iSeries_Write_Byte(*src++, dest++);
536 EXPORT_SYMBOL(iSeries_memcpy_toio);
538 void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
541 long NumberOfBytes = count;
543 while (NumberOfBytes > 0) {
544 *dst++ = iSeries_Read_Byte(src++);
548 EXPORT_SYMBOL(iSeries_memcpy_fromio);
551 * Look down the chain to find the matching Device Device
553 static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
555 struct list_head *pos;
557 list_for_each(pos, &iSeries_Global_Device_List) {
558 struct iSeries_Device_Node *node =
559 list_entry(pos, struct iSeries_Device_Node, Device_List);
561 if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
569 * Returns the device node for the passed pci_dev
570 * Sanity Check Node PciDev to passed pci_dev
571 * If none is found, returns a NULL which the client must handle.
573 static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
575 struct iSeries_Device_Node *node;
577 node = pdev->sysdata;
578 if (node == NULL || node->PciDev != pdev)
579 node = find_Device_Node(pdev->bus->number, pdev->devfn);
585 * Config space read and write functions.
586 * For now at least, we look for the device node for the bus and devfn
587 * that we are asked to access. It may be possible to translate the devfn
588 * to a subbus and deviceid more directly.
590 static u64 hv_cfg_read_func[4] = {
591 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
592 HvCallPciConfigLoad32, HvCallPciConfigLoad32
595 static u64 hv_cfg_write_func[4] = {
596 HvCallPciConfigStore8, HvCallPciConfigStore16,
597 HvCallPciConfigStore32, HvCallPciConfigStore32
601 * Read PCI config space
603 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
604 int offset, int size, u32 *val)
606 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
608 struct HvCallPci_LoadReturn ret;
611 return PCIBIOS_DEVICE_NOT_FOUND;
614 return PCIBIOS_BAD_REGISTER_NUMBER;
617 fn = hv_cfg_read_func[(size - 1) & 3];
618 HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);
622 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
630 * Write PCI config space
633 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
634 int offset, int size, u32 val)
636 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
641 return PCIBIOS_DEVICE_NOT_FOUND;
643 return PCIBIOS_BAD_REGISTER_NUMBER;
645 fn = hv_cfg_write_func[(size - 1) & 3];
646 ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);
649 return PCIBIOS_DEVICE_NOT_FOUND;
654 static struct pci_ops iSeries_pci_ops = {
655 .read = iSeries_pci_read_config,
656 .write = iSeries_pci_write_config
661 * -> On Failure, print and log information.
662 * Increment Retry Count, if exceeds max, panic partition.
663 * -> If in retry, print and log success
665 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
666 * PCI: Device 23.90 ReadL Retry( 1)
667 * PCI: Device 23.90 ReadL Retry Successful(1)
669 static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
675 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
676 TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
677 DevNode->IoRetry, (int)ret);
679 * Bump the retry and check for retry count exceeded.
680 * If, Exceeded, panic the system.
682 if ((DevNode->IoRetry > Pci_Retry_Max) &&
683 (Pci_Error_Flag > 0)) {
684 mf_display_src(0xB6000103);
686 panic("PCI: Hardware I/O Error, SRC B6000103, "
687 "Automatic Reboot Disabled.\n");
689 return -1; /* Retry Try */
691 /* If retry was in progress, log success and rest retry count */
692 if (DevNode->IoRetry > 0)
693 DevNode->IoRetry = 0;
698 * Translate the I/O Address into a device node, bar, and bar offset.
699 * Note: Make sure the passed variable end up on the stack to avoid
700 * the exposure of being device global.
702 static inline struct iSeries_Device_Node *xlate_iomm_address(
703 const volatile void __iomem *IoAddress,
704 u64 *dsaptr, u64 *BarOffsetPtr)
706 unsigned long OrigIoAddr;
707 unsigned long BaseIoAddr;
708 unsigned long TableIndex;
709 struct iSeries_Device_Node *DevNode;
711 OrigIoAddr = (unsigned long __force)IoAddress;
712 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
714 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
715 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
716 DevNode = iomm_table[TableIndex];
718 if (DevNode != NULL) {
719 int barnum = iobar_table[TableIndex];
720 *dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
721 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
723 panic("PCI: Invalid PCI IoAddress detected!\n");
728 * Read MM I/O Instructions for the iSeries
729 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
730 * else, data is returned in big Endian format.
732 * iSeries_Read_Byte = Read Byte ( 8 bit)
733 * iSeries_Read_Word = Read Word (16 bit)
734 * iSeries_Read_Long = Read Long (32 bit)
736 u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
740 struct HvCallPci_LoadReturn ret;
741 struct iSeries_Device_Node *DevNode =
742 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
744 if (DevNode == NULL) {
745 static unsigned long last_jiffies;
746 static int num_printed;
748 if ((jiffies - last_jiffies) > 60 * HZ) {
749 last_jiffies = jiffies;
752 if (num_printed++ < 10)
753 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
758 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
759 } while (CheckReturnCode("RDB", DevNode, ret.rc) != 0);
761 return (u8)ret.value;
763 EXPORT_SYMBOL(iSeries_Read_Byte);
765 u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
769 struct HvCallPci_LoadReturn ret;
770 struct iSeries_Device_Node *DevNode =
771 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
773 if (DevNode == NULL) {
774 static unsigned long last_jiffies;
775 static int num_printed;
777 if ((jiffies - last_jiffies) > 60 * HZ) {
778 last_jiffies = jiffies;
781 if (num_printed++ < 10)
782 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
787 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
789 } while (CheckReturnCode("RDW", DevNode, ret.rc) != 0);
791 return swab16((u16)ret.value);
793 EXPORT_SYMBOL(iSeries_Read_Word);
795 u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
799 struct HvCallPci_LoadReturn ret;
800 struct iSeries_Device_Node *DevNode =
801 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
803 if (DevNode == NULL) {
804 static unsigned long last_jiffies;
805 static int num_printed;
807 if ((jiffies - last_jiffies) > 60 * HZ) {
808 last_jiffies = jiffies;
811 if (num_printed++ < 10)
812 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
817 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
819 } while (CheckReturnCode("RDL", DevNode, ret.rc) != 0);
821 return swab32((u32)ret.value);
823 EXPORT_SYMBOL(iSeries_Read_Long);
826 * Write MM I/O Instructions for the iSeries
828 * iSeries_Write_Byte = Write Byte (8 bit)
829 * iSeries_Write_Word = Write Word(16 bit)
830 * iSeries_Write_Long = Write Long(32 bit)
832 void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
837 struct iSeries_Device_Node *DevNode =
838 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
840 if (DevNode == NULL) {
841 static unsigned long last_jiffies;
842 static int num_printed;
844 if ((jiffies - last_jiffies) > 60 * HZ) {
845 last_jiffies = jiffies;
848 if (num_printed++ < 10)
849 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
853 ++Pci_Io_Write_Count;
854 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
855 } while (CheckReturnCode("WWB", DevNode, rc) != 0);
857 EXPORT_SYMBOL(iSeries_Write_Byte);
859 void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
864 struct iSeries_Device_Node *DevNode =
865 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
867 if (DevNode == NULL) {
868 static unsigned long last_jiffies;
869 static int num_printed;
871 if ((jiffies - last_jiffies) > 60 * HZ) {
872 last_jiffies = jiffies;
875 if (num_printed++ < 10)
876 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
880 ++Pci_Io_Write_Count;
881 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
882 } while (CheckReturnCode("WWW", DevNode, rc) != 0);
884 EXPORT_SYMBOL(iSeries_Write_Word);
886 void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
891 struct iSeries_Device_Node *DevNode =
892 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
894 if (DevNode == NULL) {
895 static unsigned long last_jiffies;
896 static int num_printed;
898 if ((jiffies - last_jiffies) > 60 * HZ) {
899 last_jiffies = jiffies;
902 if (num_printed++ < 10)
903 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
907 ++Pci_Io_Write_Count;
908 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
909 } while (CheckReturnCode("WWL", DevNode, rc) != 0);
911 EXPORT_SYMBOL(iSeries_Write_Long);