2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/config.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 * Stack layout for the system_call stack entry.
26 * The first few entries are identical to the user_regs_struct.
28 SP_PTREGS = STACK_FRAME_OVERHEAD
29 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
30 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
31 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
32 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
34 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
35 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
36 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
37 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
38 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
39 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
40 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
41 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
42 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
43 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
44 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
45 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
46 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
47 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
48 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
49 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
50 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
52 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
53 STACK_SIZE = 1 << STACK_SHIFT
55 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
56 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
57 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
60 #define BASED(name) name-system_call(%r13)
62 .macro STORE_TIMER lc_offset
63 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
68 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
69 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
78 * Register usage in interrupt handlers:
79 * R9 - pointer to current task structure
80 * R13 - pointer to literal pool
81 * R14 - return register for function calls
82 * R15 - kernel stack pointer
85 .macro SAVE_ALL_BASE savearea
86 stmg %r12,%r15,\savearea
90 .macro SAVE_ALL_SYNC psworg,savearea
92 tm \psworg+1,0x01 # test problem state bit
93 jz 2f # skip stack setup save
94 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
95 #ifdef CONFIG_CHECK_STACK
97 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
104 .macro SAVE_ALL_ASYNC psworg,savearea
106 tm \psworg+1,0x01 # test problem state bit
107 jnz 1f # from user -> load kernel stack
108 clc \psworg+8(8),BASED(.Lcritical_end)
110 clc \psworg+8(8),BASED(.Lcritical_start)
112 brasl %r14,cleanup_critical
113 tm 1(%r12),0x01 # retest problem state after cleanup
115 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
117 srag %r14,%r14,STACK_SHIFT
119 1: lg %r15,__LC_ASYNC_STACK # load async stack
120 #ifdef CONFIG_CHECK_STACK
122 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
129 .macro CREATE_STACK_FRAME psworg,savearea
130 aghi %r15,-SP_SIZE # make room for registers & psw
131 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
133 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
134 icm %r12,12,__LC_SVC_ILC
135 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
137 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
139 stg %r12,__SF_BACKCHAIN(%r15)
142 .macro RESTORE_ALL psworg,sync
143 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
145 ni \psworg+1,0xfd # clear wait state bit
147 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
148 STORE_TIMER __LC_EXIT_TIMER
149 lpswe \psworg # back to caller
153 * Scheduler resume function, called by switch_to
154 * gpr2 = (task_struct *) prev
155 * gpr3 = (task_struct *) next
161 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
162 jz __switch_to_noper # if not we're fine
163 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
164 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
165 je __switch_to_noper # we got away without bashing TLB's
166 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
168 lg %r4,__THREAD_info(%r2) # get thread_info of prev
169 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
170 jz __switch_to_no_mcck
171 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
172 lg %r4,__THREAD_info(%r3) # get thread_info of next
173 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
175 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
176 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
177 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
178 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
179 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
180 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
181 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
182 stg %r3,__LC_THREAD_INFO
184 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
189 * SVC interrupt handler routine. System calls are synchronous events and
190 * are executed with interrupts enabled.
195 STORE_TIMER __LC_SYNC_ENTER_TIMER
197 SAVE_ALL_BASE __LC_SAVE_AREA
198 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
199 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
200 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
201 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
203 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
205 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
207 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
209 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
212 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
213 slag %r7,%r7,2 # *4 and test for svc 0
215 # svc 0: system call number in %r1
216 cl %r1,BASED(.Lnr_syscalls)
218 lgfr %r7,%r1 # clear high word in r1
219 slag %r7,%r7,2 # svc 0: system call number in %r1
221 mvc SP_ARGS(8,%r15),SP_R7(%r15)
223 larl %r10,sys_call_table
225 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
227 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
230 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
231 lgf %r8,0(%r7,%r10) # load address of system call routine
233 basr %r14,%r8 # call sys_xxxx
234 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
235 # ATTENTION: check sys_execve_glue before
236 # changing anything here !!
239 tm SP_PSW+1(%r15),0x01 # returning to user ?
241 tm __TI_flags+7(%r9),_TIF_WORK_SVC
242 jnz sysc_work # there is work to do (signals etc.)
244 RESTORE_ALL __LC_RETURN_PSW,1
247 # recheck if there is more work to do
250 tm __TI_flags+7(%r9),_TIF_WORK_SVC
251 jz sysc_leave # there is no work to do
253 # One of the work bits is on. Find out which one.
256 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
258 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
260 tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
262 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
264 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
269 # _TIF_NEED_RESCHED is set, call schedule
272 larl %r14,sysc_work_loop
273 jg schedule # return point is sysc_return
276 # _TIF_MCCK_PENDING is set, call handler
279 larl %r14,sysc_work_loop
280 jg s390_handle_mcck # TIF bit will be cleared by handler
283 # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
286 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
287 la %r2,SP_PTREGS(%r15) # load pt_regs
288 brasl %r14,do_signal # call do_signal
289 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
291 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
296 # _TIF_RESTART_SVC is set, set up registers and restart svc
299 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
300 lg %r7,SP_R2(%r15) # load new svc number
302 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
303 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
304 j sysc_do_restart # restart svc
307 # _TIF_SINGLE_STEP is set, call do_single_step
310 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
311 lhi %r0,__LC_PGM_OLD_PSW
312 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
313 la %r2,SP_PTREGS(%r15) # address of register-save area
314 larl %r14,sysc_return # load adr. of system return
315 jg do_single_step # branch to do_sigtrap
319 # call syscall_trace before and after system call
320 # special linkage: %r12 contains the return address for trace_svc
323 la %r2,SP_PTREGS(%r15) # load pt_regs
327 brasl %r14,syscall_trace
331 lg %r7,SP_R2(%r15) # strace might have changed the
332 sll %r7,2 # system call
335 lmg %r3,%r6,SP_R3(%r15)
336 lg %r2,SP_ORIG_R2(%r15)
337 basr %r14,%r8 # call sys_xxx
338 stg %r2,SP_R2(%r15) # store return value
340 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
342 la %r2,SP_PTREGS(%r15) # load pt_regs
344 larl %r14,sysc_return # return point is sysc_return
348 # a new process exits the kernel with ret_from_fork
352 lg %r13,__LC_SVC_NEW_PSW+8
353 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
354 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
356 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
357 0: brasl %r14,schedule_tail
358 stosm 24(%r15),0x03 # reenable interrupts
362 # clone, fork, vfork, exec and sigreturn need glue,
363 # because they all expect pt_regs as parameter,
364 # but are called with different parameter.
365 # return-address is set up above
368 la %r2,SP_PTREGS(%r15) # load pt_regs
369 jg sys_clone # branch to sys_clone
373 la %r2,SP_PTREGS(%r15) # load pt_regs
374 jg sys32_clone # branch to sys32_clone
378 la %r2,SP_PTREGS(%r15) # load pt_regs
379 jg sys_fork # branch to sys_fork
382 la %r2,SP_PTREGS(%r15) # load pt_regs
383 jg sys_vfork # branch to sys_vfork
386 la %r2,SP_PTREGS(%r15) # load pt_regs
387 lgr %r12,%r14 # save return address
388 brasl %r14,sys_execve # call sys_execve
389 ltgr %r2,%r2 # check if execve failed
390 bnz 0(%r12) # it did fail -> store result in gpr2
391 b 6(%r12) # SKIP STG 2,SP_R2(15) in
392 # system_call/sysc_tracesys
395 la %r2,SP_PTREGS(%r15) # load pt_regs
396 lgr %r12,%r14 # save return address
397 brasl %r14,sys32_execve # call sys32_execve
398 ltgr %r2,%r2 # check if execve failed
399 bnz 0(%r12) # it did fail -> store result in gpr2
400 b 6(%r12) # SKIP STG 2,SP_R2(15) in
401 # system_call/sysc_tracesys
405 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
406 jg sys_sigreturn # branch to sys_sigreturn
409 sys32_sigreturn_glue:
410 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
411 jg sys32_sigreturn # branch to sys32_sigreturn
414 sys_rt_sigreturn_glue:
415 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
416 jg sys_rt_sigreturn # branch to sys_sigreturn
419 sys32_rt_sigreturn_glue:
420 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
421 jg sys32_rt_sigreturn # branch to sys32_sigreturn
424 sys_sigaltstack_glue:
425 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
426 jg sys_sigaltstack # branch to sys_sigreturn
429 sys32_sigaltstack_glue:
430 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
431 jg sys32_sigaltstack_wrapper # branch to sys_sigreturn
435 * Program check handler routine
438 .globl pgm_check_handler
441 * First we need to check for a special case:
442 * Single stepping an instruction that disables the PER event mask will
443 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
444 * For a single stepped SVC the program check handler gets control after
445 * the SVC new PSW has been loaded. But we want to execute the SVC first and
446 * then handle the PER event. Therefore we update the SVC old PSW to point
447 * to the pgm_check_handler and branch to the SVC handler after we checked
448 * if we have to load the kernel stack register.
449 * For every other possible cause for PER event without the PER mask set
450 * we just ignore the PER event (FIXME: is there anything we have to do
453 STORE_TIMER __LC_SYNC_ENTER_TIMER
454 SAVE_ALL_BASE __LC_SAVE_AREA
455 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
456 jnz pgm_per # got per exception -> special case
457 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
458 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
459 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
460 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
462 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
463 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
464 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
467 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
468 lgf %r3,__LC_PGM_ILC # load program interruption code
473 larl %r1,pgm_check_table
474 lg %r1,0(%r8,%r1) # load address of handler routine
475 la %r2,SP_PTREGS(%r15) # address of register-save area
476 larl %r14,sysc_return
477 br %r1 # branch to interrupt-handler
480 # handle per exception
483 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
484 jnz pgm_per_std # ok, normal per event from user space
485 # ok its one of the special cases, now we need to find out which one
486 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
488 # no interesting special case, ignore PER event
489 lmg %r12,%r15,__LC_SAVE_AREA
490 lpswe __LC_PGM_OLD_PSW
493 # Normal per exception
496 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
497 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
498 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
499 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
501 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
502 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
503 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
506 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
507 lg %r1,__TI_task(%r9)
508 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
509 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
510 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
511 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
512 lgf %r3,__LC_PGM_ILC # load program interruption code
514 ngr %r8,%r3 # clear per-event-bit and ilc
519 # it was a single stepped SVC that is causing all the trouble
522 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
523 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
524 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
525 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
527 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
528 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
529 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
532 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
533 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
534 lg %r1,__TI_task(%r9)
535 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
536 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
537 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
538 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
539 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
543 * IO interrupt handler routine
545 .globl io_int_handler
547 STORE_TIMER __LC_ASYNC_ENTER_TIMER
549 SAVE_ALL_BASE __LC_SAVE_AREA+32
550 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
551 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
552 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
553 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
555 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
556 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
557 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
560 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
561 la %r2,SP_PTREGS(%r15) # address of register-save area
562 brasl %r14,do_IRQ # call standard irq handler
565 tm SP_PSW+1(%r15),0x01 # returning to user ?
566 #ifdef CONFIG_PREEMPT
567 jno io_preempt # no -> check for preemptive scheduling
569 jno io_leave # no-> skip resched & signal
571 tm __TI_flags+7(%r9),_TIF_WORK_INT
572 jnz io_work # there is work to do (signals etc.)
574 RESTORE_ALL __LC_RETURN_PSW,0
577 #ifdef CONFIG_PREEMPT
579 icm %r0,15,__TI_precount(%r9)
581 # switch to kernel stack
584 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
585 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
588 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
591 mvc __TI_precount(4,%r9),0(%r1)
592 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
593 brasl %r14,schedule # call schedule
594 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
595 xc __TI_precount(4,%r9),__TI_precount(%r9)
600 # switch to kernel stack, then check TIF bits
603 lg %r1,__LC_KERNEL_STACK
605 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
606 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
609 # One of the work bits is on. Find out which one.
610 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
611 # and _TIF_MCCK_PENDING
614 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
616 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
618 tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
623 # _TIF_MCCK_PENDING is set, call handler
626 larl %r14,io_work_loop
627 jg s390_handle_mcck # TIF bit will be cleared by handler
630 # _TIF_NEED_RESCHED is set, call schedule
633 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
634 brasl %r14,schedule # call scheduler
635 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
636 tm __TI_flags+7(%r9),_TIF_WORK_INT
637 jz io_leave # there is no work to do
641 # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
644 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
645 la %r2,SP_PTREGS(%r15) # load pt_regs
646 brasl %r14,do_signal # call do_signal
647 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
651 * External interrupt handler routine
653 .globl ext_int_handler
655 STORE_TIMER __LC_ASYNC_ENTER_TIMER
657 SAVE_ALL_BASE __LC_SAVE_AREA+32
658 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
659 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
660 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
661 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
663 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
664 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
665 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
668 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
669 la %r2,SP_PTREGS(%r15) # address of register-save area
670 llgh %r3,__LC_EXT_INT_CODE # get interruption code
677 * Machine check handler routines
679 .globl mcck_int_handler
681 la %r1,4095 # revalidate r1
682 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
683 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
684 SAVE_ALL_BASE __LC_SAVE_AREA+64
685 la %r12,__LC_MCK_OLD_PSW
686 tm __LC_MCCK_CODE,0x80 # system damage?
687 jo mcck_int_main # yes -> rest of mcck code invalid
688 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
690 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
691 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
692 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
694 la %r14,__LC_SYNC_ENTER_TIMER
695 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
697 la %r14,__LC_ASYNC_ENTER_TIMER
698 0: clc 0(8,%r14),__LC_EXIT_TIMER
700 la %r14,__LC_EXIT_TIMER
701 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
703 la %r14,__LC_LAST_UPDATE_TIMER
705 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
708 tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
709 jno mcck_int_main # no -> skip cleanup critical
710 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
711 jnz mcck_int_main # from user -> load kernel stack
712 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
714 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
716 brasl %r14,cleanup_critical
718 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
720 srag %r14,%r14,PAGE_SHIFT
722 lg %r15,__LC_PANIC_STACK # load panic stack
723 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
724 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
725 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
726 jno mcck_no_vtime # no -> no timer update
727 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
729 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
730 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
731 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
734 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
735 la %r2,SP_PTREGS(%r15) # load pt_regs
736 brasl %r14,s390_do_machine_check
737 tm SP_PSW+1(%r15),0x01 # returning to user ?
739 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
741 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
742 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
744 stosm __SF_EMPTY(%r15),0x04 # turn dat on
745 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
747 brasl %r14,s390_handle_mcck
749 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
750 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
751 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
752 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
753 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
754 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
759 lpswe __LC_RETURN_MCCK_PSW # back to caller
763 * Restart interruption handler, kick starter for additional CPUs
765 .globl restart_int_handler
767 lg %r15,__LC_SAVE_AREA+120 # load ksp
768 lghi %r10,__LC_CREGS_SAVE_AREA
769 lctlg %c0,%c15,0(%r10) # get new ctl regs
770 lghi %r10,__LC_AREGS_SAVE_AREA
772 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
773 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
777 * If we do not run with SMP enabled, let the new CPU crash ...
779 .globl restart_int_handler
783 lpswe restart_crash-restart_base(%r1)
786 .long 0x000a0000,0x00000000,0x00000000,0x00000000
790 #ifdef CONFIG_CHECK_STACK
792 * The synchronous or the asynchronous stack overflowed. We are dead.
793 * No need to properly save the registers, we are going to panic anyway.
794 * Setup a pt_regs so that show_trace can provide a good call trace.
797 lg %r15,__LC_PANIC_STACK # change to panic stack
799 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
800 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
801 la %r1,__LC_SAVE_AREA
802 chi %r12,__LC_SVC_OLD_PSW
804 chi %r12,__LC_PGM_OLD_PSW
806 la %r1,__LC_SAVE_AREA+16
807 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
808 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
809 la %r2,SP_PTREGS(%r15) # load pt_regs
810 jg kernel_stack_overflow
813 cleanup_table_system_call:
814 .quad system_call, sysc_do_svc
815 cleanup_table_sysc_return:
816 .quad sysc_return, sysc_leave
817 cleanup_table_sysc_leave:
818 .quad sysc_leave, sysc_work_loop
819 cleanup_table_sysc_work_loop:
820 .quad sysc_work_loop, sysc_reschedule
821 cleanup_table_io_return:
822 .quad io_return, io_leave
823 cleanup_table_io_leave:
824 .quad io_leave, io_done
825 cleanup_table_io_work_loop:
826 .quad io_work_loop, io_mcck_pending
829 clc 8(8,%r12),BASED(cleanup_table_system_call)
831 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
832 jl cleanup_system_call
834 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
836 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
837 jl cleanup_sysc_return
839 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
841 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
842 jl cleanup_sysc_leave
844 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
846 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
847 jl cleanup_sysc_return
849 clc 8(8,%r12),BASED(cleanup_table_io_return)
851 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
854 clc 8(8,%r12),BASED(cleanup_table_io_leave)
856 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
859 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
861 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
867 mvc __LC_RETURN_PSW(16),0(%r12)
868 cghi %r12,__LC_MCK_OLD_PSW
870 la %r12,__LC_SAVE_AREA+32
872 0: la %r12,__LC_SAVE_AREA+64
874 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
875 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
877 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
878 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
881 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
883 mvc __LC_SAVE_AREA(32),0(%r12)
885 stg %r12,__LC_SAVE_AREA+96 # argh
886 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
887 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
888 lg %r12,__LC_SAVE_AREA+96 # argh
890 llgh %r7,__LC_SVC_INT_CODE
891 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
893 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
895 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
897 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
899 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
901 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
903 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
906 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
907 la %r12,__LC_RETURN_PSW
909 cleanup_system_call_insn:
911 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
919 mvc __LC_RETURN_PSW(8),0(%r12)
920 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
921 la %r12,__LC_RETURN_PSW
925 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
927 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
928 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
929 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
932 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
933 cghi %r12,__LC_MCK_OLD_PSW
935 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
937 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
938 1: lmg %r0,%r11,SP_R0(%r15)
940 2: la %r12,__LC_RETURN_PSW
942 cleanup_sysc_leave_insn:
943 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
944 .quad sysc_leave + 16
946 .quad sysc_leave + 12
949 mvc __LC_RETURN_PSW(8),0(%r12)
950 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
951 la %r12,__LC_RETURN_PSW
955 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
957 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
958 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
959 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
962 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
963 cghi %r12,__LC_MCK_OLD_PSW
965 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
967 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
968 1: lmg %r0,%r11,SP_R0(%r15)
970 2: la %r12,__LC_RETURN_PSW
972 cleanup_io_leave_insn:
973 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
983 .Lc_pactive: .long PREEMPT_ACTIVE
984 .Lnr_syscalls: .long NR_syscalls
985 .L0x0130: .short 0x130
986 .L0x0140: .short 0x140
987 .L0x0150: .short 0x150
988 .L0x0160: .short 0x160
989 .L0x0170: .short 0x170
991 .quad __critical_start
995 #define SYSCALL(esa,esame,emu) .long esame
997 #include "syscalls.S"
1000 #ifdef CONFIG_COMPAT
1002 #define SYSCALL(esa,esame,emu) .long emu
1004 #include "syscalls.S"