2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
25 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
29 #define _INTC_SHIFT(h) (h & 0x1f)
30 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31 #define _INTC_FN(h) ((h >> 9) & 0xf)
32 #define _INTC_MODE(h) ((h >> 13) & 0x7)
33 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
36 struct intc_handle_int {
41 struct intc_desc_int {
47 struct intc_handle_int *prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
55 #define IS_SMP(x) x.smp
56 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
60 #define INTC_REG(d, x, c) (d->reg[(x)])
61 #define SMP_NR(d, x) 1
64 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
66 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
68 struct irq_chip *chip = get_irq_chip(irq);
69 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
72 static inline unsigned int set_field(unsigned int value,
73 unsigned int field_value,
76 unsigned int width = _INTC_WIDTH(handle);
77 unsigned int shift = _INTC_SHIFT(handle);
79 value &= ~(((1 << width) - 1) << shift);
80 value |= field_value << shift;
84 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
86 ctrl_outb(set_field(0, data, h), addr);
89 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
91 ctrl_outw(set_field(0, data, h), addr);
94 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
96 ctrl_outl(set_field(0, data, h), addr);
99 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
101 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
104 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
106 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
109 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
111 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
114 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
116 static void (*intc_reg_fns[])(unsigned long addr,
118 unsigned long data) = {
119 [REG_FN_WRITE_BASE + 0] = write_8,
120 [REG_FN_WRITE_BASE + 1] = write_16,
121 [REG_FN_WRITE_BASE + 3] = write_32,
122 [REG_FN_MODIFY_BASE + 0] = modify_8,
123 [REG_FN_MODIFY_BASE + 1] = modify_16,
124 [REG_FN_MODIFY_BASE + 3] = modify_32,
127 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
128 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
129 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
130 MODE_PRIO_REG, /* Priority value written to enable interrupt */
131 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
134 static void intc_mode_field(unsigned long addr,
135 unsigned long handle,
136 void (*fn)(unsigned long,
141 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
144 static void intc_mode_zero(unsigned long addr,
145 unsigned long handle,
146 void (*fn)(unsigned long,
154 static void intc_mode_prio(unsigned long addr,
155 unsigned long handle,
156 void (*fn)(unsigned long,
161 fn(addr, handle, intc_prio_level[irq]);
164 static void (*intc_enable_fns[])(unsigned long addr,
165 unsigned long handle,
166 void (*fn)(unsigned long,
169 unsigned int irq) = {
170 [MODE_ENABLE_REG] = intc_mode_field,
171 [MODE_MASK_REG] = intc_mode_zero,
172 [MODE_DUAL_REG] = intc_mode_field,
173 [MODE_PRIO_REG] = intc_mode_prio,
174 [MODE_PCLR_REG] = intc_mode_prio,
177 static void (*intc_disable_fns[])(unsigned long addr,
178 unsigned long handle,
179 void (*fn)(unsigned long,
182 unsigned int irq) = {
183 [MODE_ENABLE_REG] = intc_mode_zero,
184 [MODE_MASK_REG] = intc_mode_field,
185 [MODE_DUAL_REG] = intc_mode_field,
186 [MODE_PRIO_REG] = intc_mode_zero,
187 [MODE_PCLR_REG] = intc_mode_field,
190 static inline void _intc_enable(unsigned int irq, unsigned long handle)
192 struct intc_desc_int *d = get_intc_desc(irq);
196 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
197 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
198 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
199 [_INTC_FN(handle)], irq);
203 static void intc_enable(unsigned int irq)
205 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
208 static void intc_disable(unsigned int irq)
210 struct intc_desc_int *d = get_intc_desc(irq);
211 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
215 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
216 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
217 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
218 [_INTC_FN(handle)], irq);
222 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
228 /* this doesn't scale well, but...
230 * this function should only be used for cerain uncommon
231 * operations such as intc_set_priority() and intc_set_sense()
232 * and in those rare cases performance doesn't matter that much.
233 * keeping the memory footprint low is more important.
235 * one rather simple way to speed this up and still keep the
236 * memory footprint down is to make sure the array is sorted
237 * and then perform a bisect to lookup the irq.
240 for (i = 0; i < nr_hp; i++) {
241 if ((hp + i)->irq != irq)
250 int intc_set_priority(unsigned int irq, unsigned int prio)
252 struct intc_desc_int *d = get_intc_desc(irq);
253 struct intc_handle_int *ihp;
255 if (!intc_prio_level[irq] || prio <= 1)
258 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
260 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
263 intc_prio_level[irq] = prio;
266 * only set secondary masking method directly
267 * primary masking method is using intc_prio_level[irq]
268 * priority level will be set during next enable()
271 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
272 _intc_enable(irq, ihp->handle);
277 #define VALID(x) (x | 0x80)
279 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
280 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
281 [IRQ_TYPE_EDGE_RISING] = VALID(1),
282 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
283 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
286 static int intc_set_sense(unsigned int irq, unsigned int type)
288 struct intc_desc_int *d = get_intc_desc(irq);
289 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
290 struct intc_handle_int *ihp;
296 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
298 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
299 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
304 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
305 unsigned long address)
309 for (k = 0; k < d->nr_reg; k++) {
310 if (d->reg[k] == address)
318 static intc_enum __init intc_grp_id(struct intc_desc *desc,
321 struct intc_group *g = desc->groups;
324 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
325 g = desc->groups + i;
327 for (j = 0; g->enum_ids[j]; j++) {
328 if (g->enum_ids[j] != enum_id)
338 static unsigned int __init intc_prio_value(struct intc_desc *desc,
339 intc_enum enum_id, int do_grps)
341 struct intc_prio *p = desc->priorities;
344 for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
345 p = desc->priorities + i;
347 if (p->enum_id != enum_id)
354 return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
356 /* default to the lowest priority possible if no priority is set
357 * - this needs to be at least 2 for 5-bit priorities on 7780
363 static unsigned int __init intc_mask_data(struct intc_desc *desc,
364 struct intc_desc_int *d,
365 intc_enum enum_id, int do_grps)
367 struct intc_mask_reg *mr = desc->mask_regs;
368 unsigned int i, j, fn, mode;
369 unsigned long reg_e, reg_d;
371 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
372 mr = desc->mask_regs + i;
374 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
375 if (mr->enum_ids[j] != enum_id)
378 if (mr->set_reg && mr->clr_reg) {
379 fn = REG_FN_WRITE_BASE;
380 mode = MODE_DUAL_REG;
384 fn = REG_FN_MODIFY_BASE;
386 mode = MODE_ENABLE_REG;
390 mode = MODE_MASK_REG;
396 fn += (mr->reg_width >> 3) - 1;
397 return _INTC_MK(fn, mode,
398 intc_get_reg(d, reg_e),
399 intc_get_reg(d, reg_d),
401 (mr->reg_width - 1) - j);
406 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
411 static unsigned int __init intc_prio_data(struct intc_desc *desc,
412 struct intc_desc_int *d,
413 intc_enum enum_id, int do_grps)
415 struct intc_prio_reg *pr = desc->prio_regs;
416 unsigned int i, j, fn, mode, bit;
417 unsigned long reg_e, reg_d;
419 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
420 pr = desc->prio_regs + i;
422 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
423 if (pr->enum_ids[j] != enum_id)
426 if (pr->set_reg && pr->clr_reg) {
427 fn = REG_FN_WRITE_BASE;
428 mode = MODE_PCLR_REG;
432 fn = REG_FN_MODIFY_BASE;
433 mode = MODE_PRIO_REG;
440 fn += (pr->reg_width >> 3) - 1;
441 bit = pr->reg_width - ((j + 1) * pr->field_width);
445 return _INTC_MK(fn, mode,
446 intc_get_reg(d, reg_e),
447 intc_get_reg(d, reg_d),
448 pr->field_width, bit);
453 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
458 static unsigned int __init intc_sense_data(struct intc_desc *desc,
459 struct intc_desc_int *d,
462 struct intc_sense_reg *sr = desc->sense_regs;
463 unsigned int i, j, fn, bit;
465 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
466 sr = desc->sense_regs + i;
468 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
469 if (sr->enum_ids[j] != enum_id)
472 fn = REG_FN_MODIFY_BASE;
473 fn += (sr->reg_width >> 3) - 1;
474 bit = sr->reg_width - ((j + 1) * sr->field_width);
478 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
479 0, sr->field_width, bit);
486 static void __init intc_register_irq(struct intc_desc *desc,
487 struct intc_desc_int *d,
491 struct intc_handle_int *hp;
492 unsigned int data[2], primary;
494 /* Prefer single interrupt source bitmap over other combinations:
495 * 1. bitmap, single interrupt source
496 * 2. priority, single interrupt source
497 * 3. bitmap, multiple interrupt sources (groups)
498 * 4. priority, multiple interrupt sources (groups)
501 data[0] = intc_mask_data(desc, d, enum_id, 0);
502 data[1] = intc_prio_data(desc, d, enum_id, 0);
505 if (!data[0] && data[1])
508 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
509 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
514 BUG_ON(!data[primary]); /* must have primary masking method */
516 disable_irq_nosync(irq);
517 set_irq_chip_and_handler_name(irq, &d->chip,
518 handle_level_irq, "level");
519 set_irq_chip_data(irq, (void *)data[primary]);
521 /* record the desired priority level */
522 intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
524 /* enable secondary masking method if present */
526 _intc_enable(irq, data[!primary]);
528 /* add irq to d->prio list if priority is available */
530 hp = d->prio + d->nr_prio;
532 hp->handle = data[1];
536 * only secondary priority should access registers, so
537 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
540 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
541 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
546 /* add irq to d->sense list if sense is available */
547 data[0] = intc_sense_data(desc, d, enum_id);
549 (d->sense + d->nr_sense)->irq = irq;
550 (d->sense + d->nr_sense)->handle = data[0];
554 /* irq should be disabled by default */
558 static unsigned int __init save_reg(struct intc_desc_int *d,
575 void __init register_intc_controller(struct intc_desc *desc)
577 unsigned int i, k, smp;
578 struct intc_desc_int *d;
580 d = alloc_bootmem(sizeof(*d));
582 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
583 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
584 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
586 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
588 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
592 if (desc->mask_regs) {
593 for (i = 0; i < desc->nr_mask_regs; i++) {
594 smp = IS_SMP(desc->mask_regs[i]);
595 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
596 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
600 if (desc->prio_regs) {
601 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
603 for (i = 0; i < desc->nr_prio_regs; i++) {
604 smp = IS_SMP(desc->prio_regs[i]);
605 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
606 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
610 if (desc->sense_regs) {
611 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
613 for (i = 0; i < desc->nr_sense_regs; i++) {
614 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
618 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
620 d->chip.name = desc->name;
621 d->chip.mask = intc_disable;
622 d->chip.unmask = intc_enable;
623 d->chip.mask_ack = intc_disable;
624 d->chip.set_type = intc_set_sense;
626 for (i = 0; i < desc->nr_vectors; i++) {
627 struct intc_vect *vect = desc->vectors + i;
629 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));