2 * SH3 Setup code for SH7710, SH7712
4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/serial.h>
20 /* interrupt sources */
21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
22 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
23 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
24 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
27 EDMAC0, EDMAC1, EDMAC2,
28 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
29 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 RTC_ATI, RTC_PRI, RTC_CUI,
35 /* interrupt groups */
36 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
39 static struct intc_vect vectors[] = {
40 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
41 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
42 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
43 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
44 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
45 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
46 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
47 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
48 #ifdef CONFIG_CPU_SUBTYPE_SH7710
49 INTC_VECT(IPSEC, 0xbe0),
51 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
52 INTC_VECT(EDMAC2, 0xc40),
53 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
54 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
55 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
56 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
57 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
58 INTC_VECT(TMU2, 0x440),
59 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
60 INTC_VECT(RTC_CUI, 0x4c0),
61 INTC_VECT(WDT, 0x560),
62 INTC_VECT(REF, 0x580),
65 static struct intc_group groups[] = {
66 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
67 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
68 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
69 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
70 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
71 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
72 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
75 static struct intc_prio priorities[] = {
87 static struct intc_prio_reg prio_registers[] = {
88 { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
89 { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
90 { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
91 { 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
92 { 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
93 { 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } },
94 #ifdef CONFIG_CPU_SUBTYPE_SH7710
95 { 0xa4080000, 16, 4, /* IPRF */ { IPSEC } },
97 { 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
98 { 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
99 { 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
102 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
103 priorities, NULL, prio_registers, NULL);
105 static struct intc_vect vectors_irq[] = {
106 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
107 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
110 static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
111 priorities, NULL, prio_registers, NULL);
113 static struct resource rtc_resources[] = {
116 .end = 0xa413fec0 + 0x1e,
117 .flags = IORESOURCE_IO,
121 .flags = IORESOURCE_IRQ,
125 .flags = IORESOURCE_IRQ,
129 .flags = IORESOURCE_IRQ,
133 static struct platform_device rtc_device = {
136 .num_resources = ARRAY_SIZE(rtc_resources),
137 .resource = rtc_resources,
140 static struct plat_sci_port sci_platform_data[] = {
142 .mapbase = 0xa4400000,
143 .flags = UPF_BOOT_AUTOCONF,
145 .irqs = { 52, 53, 55, 54 },
147 .mapbase = 0xa4410000,
148 .flags = UPF_BOOT_AUTOCONF,
150 .irqs = { 56, 57, 59, 58 },
157 static struct platform_device sci_device = {
161 .platform_data = sci_platform_data,
165 static struct platform_device *sh7710_devices[] __initdata = {
170 static int __init sh7710_devices_setup(void)
172 return platform_add_devices(sh7710_devices,
173 ARRAY_SIZE(sh7710_devices));
175 __initcall(sh7710_devices_setup);
177 void __init plat_irq_setup_pins(int mode)
179 if (mode == IRQ_MODE_IRQ) {
180 register_intc_controller(&intc_desc_irq);
186 void __init plat_irq_setup(void)
188 register_intc_controller(&intc_desc);