2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/kexec.h>
25 #include <linux/limits.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
31 #define CHK_REMOTE_DEBUG(regs) \
33 if (kgdb_debug_hook && !user_mode(regs))\
34 (*kgdb_debug_hook)(regs); \
37 #define CHK_REMOTE_DEBUG(regs)
41 # define TRAP_RESERVED_INST 4
42 # define TRAP_ILLEGAL_SLOT_INST 6
43 # define TRAP_ADDRESS_ERROR 9
44 # ifdef CONFIG_CPU_SH2A
45 # define TRAP_DIVZERO_ERROR 17
46 # define TRAP_DIVOVF_ERROR 18
49 #define TRAP_RESERVED_INST 12
50 #define TRAP_ILLEGAL_SLOT_INST 13
53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
58 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
60 for (p = bottom & ~31; p < top; ) {
61 printk("%04lx: ", p & 0xffff);
63 for (i = 0; i < 8; i++, p += 4) {
66 if (p < bottom || p >= top)
69 if (__get_user(val, (unsigned int __user *)p)) {
80 static DEFINE_SPINLOCK(die_lock);
82 void die(const char * str, struct pt_regs * regs, long err)
84 static int die_counter;
87 spin_lock_irq(&die_lock);
90 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
92 CHK_REMOTE_DEBUG(regs);
96 printk("Process: %s (pid: %d, stack limit = %p)\n",
97 current->comm, current->pid, task_stack_page(current) + 1);
99 if (!user_mode(regs) || in_interrupt())
100 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
101 (unsigned long)task_stack_page(current));
104 spin_unlock_irq(&die_lock);
106 if (kexec_should_crash(current))
110 panic("Fatal exception in interrupt");
113 panic("Fatal exception");
118 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
121 if (!user_mode(regs))
126 * try and fix up kernelspace address errors
127 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
128 * - kernel/userspace interfaces cause a jump to an appropriate handler
129 * - other kernel errors are bad
130 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
132 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
134 if (!user_mode(regs)) {
135 const struct exception_table_entry *fixup;
136 fixup = search_exception_tables(regs->pc);
138 regs->pc = fixup->fixup;
147 * handle an instruction that does an unaligned memory access by emulating the
149 * - note that PC _may not_ point to the faulting instruction
150 * (if that instruction is in a branch delay slot)
151 * - return 0 if emulation okay, -EFAULT on existential error
153 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs)
155 int ret, index, count;
156 unsigned long *rm, *rn;
157 unsigned char *src, *dst;
159 index = (instruction>>8)&15; /* 0x0F00 */
160 rn = ®s->regs[index];
162 index = (instruction>>4)&15; /* 0x00F0 */
163 rm = ®s->regs[index];
165 count = 1<<(instruction&3);
168 switch (instruction>>12) {
169 case 0: /* mov.[bwl] to/from memory via r0+rn */
170 if (instruction & 8) {
172 src = (unsigned char*) *rm;
173 src += regs->regs[0];
174 dst = (unsigned char*) rn;
175 *(unsigned long*)dst = 0;
177 #ifdef __LITTLE_ENDIAN__
178 if (copy_from_user(dst, src, count))
181 if ((count == 2) && dst[1] & 0x80) {
188 if (__copy_user(dst, src, count))
191 if ((count == 2) && dst[2] & 0x80) {
198 src = (unsigned char*) rm;
199 #if !defined(__LITTLE_ENDIAN__)
202 dst = (unsigned char*) *rn;
203 dst += regs->regs[0];
205 if (copy_to_user(dst, src, count))
211 case 1: /* mov.l Rm,@(disp,Rn) */
212 src = (unsigned char*) rm;
213 dst = (unsigned char*) *rn;
214 dst += (instruction&0x000F)<<2;
216 if (copy_to_user(dst,src,4))
221 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
224 src = (unsigned char*) rm;
225 dst = (unsigned char*) *rn;
226 #if !defined(__LITTLE_ENDIAN__)
229 if (copy_to_user(dst, src, count))
234 case 5: /* mov.l @(disp,Rm),Rn */
235 src = (unsigned char*) *rm;
236 src += (instruction&0x000F)<<2;
237 dst = (unsigned char*) rn;
238 *(unsigned long*)dst = 0;
240 if (copy_from_user(dst,src,4))
245 case 6: /* mov.[bwl] from memory, possibly with post-increment */
246 src = (unsigned char*) *rm;
249 dst = (unsigned char*) rn;
250 *(unsigned long*)dst = 0;
252 #ifdef __LITTLE_ENDIAN__
253 if (copy_from_user(dst, src, count))
256 if ((count == 2) && dst[1] & 0x80) {
263 if (copy_from_user(dst, src, count))
266 if ((count == 2) && dst[2] & 0x80) {
275 switch ((instruction&0xFF00)>>8) {
276 case 0x81: /* mov.w R0,@(disp,Rn) */
277 src = (unsigned char*) ®s->regs[0];
278 #if !defined(__LITTLE_ENDIAN__)
281 dst = (unsigned char*) *rm; /* called Rn in the spec */
282 dst += (instruction&0x000F)<<1;
284 if (copy_to_user(dst, src, 2))
289 case 0x85: /* mov.w @(disp,Rm),R0 */
290 src = (unsigned char*) *rm;
291 src += (instruction&0x000F)<<1;
292 dst = (unsigned char*) ®s->regs[0];
293 *(unsigned long*)dst = 0;
295 #if !defined(__LITTLE_ENDIAN__)
299 if (copy_from_user(dst, src, 2))
302 #ifdef __LITTLE_ENDIAN__
321 /* Argh. Address not only misaligned but also non-existent.
322 * Raise an EFAULT and see if it's trapped
324 return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
328 * emulate the instruction in the delay slot
329 * - fetches the instruction from PC+2
331 static inline int handle_unaligned_delayslot(struct pt_regs *regs)
335 if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) {
336 /* the instruction-fetch faulted */
341 die("delay-slot-insn faulting in handle_unaligned_delayslot",
345 return handle_unaligned_ins(instruction,regs);
349 * handle an instruction that does an unaligned memory access
350 * - have to be careful of branch delay-slot instructions that fault
352 * - if the branch would be taken PC points to the branch
353 * - if the branch would not be taken, PC points to delay-slot
355 * - PC always points to delayed branch
356 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
359 /* Macros to determine offset from current PC for branch instructions */
360 /* Explicit type coercion is used to force sign extension where needed */
361 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
362 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
365 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
368 #ifndef CONFIG_CPU_SH2A
369 static int handle_unaligned_notify_count = 10;
371 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
376 index = (instruction>>8)&15; /* 0x0F00 */
377 rm = regs->regs[index];
379 /* shout about the first ten userspace fixups */
380 if (user_mode(regs) && handle_unaligned_notify_count>0) {
381 handle_unaligned_notify_count--;
383 printk(KERN_NOTICE "Fixing up unaligned userspace access "
384 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
385 current->comm,current->pid,(u16*)regs->pc,instruction);
389 switch (instruction&0xF000) {
391 if (instruction==0x000B) {
393 ret = handle_unaligned_delayslot(regs);
397 else if ((instruction&0x00FF)==0x0023) {
399 ret = handle_unaligned_delayslot(regs);
403 else if ((instruction&0x00FF)==0x0003) {
405 ret = handle_unaligned_delayslot(regs);
407 regs->pr = regs->pc + 4;
412 /* mov.[bwl] to/from memory via r0+rn */
417 case 0x1000: /* mov.l Rm,@(disp,Rn) */
420 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
424 if ((instruction&0x00FF)==0x002B) {
426 ret = handle_unaligned_delayslot(regs);
430 else if ((instruction&0x00FF)==0x000B) {
432 ret = handle_unaligned_delayslot(regs);
434 regs->pr = regs->pc + 4;
439 /* mov.[bwl] to/from memory via r0+rn */
444 case 0x5000: /* mov.l @(disp,Rm),Rn */
447 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
450 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
451 switch (instruction&0x0F00) {
452 case 0x0100: /* mov.w R0,@(disp,Rm) */
454 case 0x0500: /* mov.w @(disp,Rm),R0 */
456 case 0x0B00: /* bf lab - no delayslot*/
458 case 0x0F00: /* bf/s lab */
459 ret = handle_unaligned_delayslot(regs);
461 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
462 if ((regs->sr & 0x00000001) != 0)
463 regs->pc += 4; /* next after slot */
466 regs->pc += SH_PC_8BIT_OFFSET(instruction);
469 case 0x0900: /* bt lab - no delayslot */
471 case 0x0D00: /* bt/s lab */
472 ret = handle_unaligned_delayslot(regs);
474 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
475 if ((regs->sr & 0x00000001) == 0)
476 regs->pc += 4; /* next after slot */
479 regs->pc += SH_PC_8BIT_OFFSET(instruction);
485 case 0xA000: /* bra label */
486 ret = handle_unaligned_delayslot(regs);
488 regs->pc += SH_PC_12BIT_OFFSET(instruction);
491 case 0xB000: /* bsr label */
492 ret = handle_unaligned_delayslot(regs);
494 regs->pr = regs->pc + 4;
495 regs->pc += SH_PC_12BIT_OFFSET(instruction);
501 /* handle non-delay-slot instruction */
503 ret = handle_unaligned_ins(instruction,regs);
505 regs->pc += instruction_size(instruction);
508 #endif /* CONFIG_CPU_SH2A */
510 #ifdef CONFIG_CPU_HAS_SR_RB
511 #define lookup_exception_vector(x) \
512 __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
514 #define lookup_exception_vector(x) \
515 __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
519 * Handle various address error exceptions:
520 * - instruction address error:
522 * PC >= 0x80000000 in user mode
523 * - data address error (read and write)
524 * misaligned data access
525 * access to >= 0x80000000 is user mode
526 * Unfortuntaly we can't distinguish between instruction address error
527 * and data address errors caused by read accesses.
529 asmlinkage void do_address_error(struct pt_regs *regs,
530 unsigned long writeaccess,
531 unsigned long address)
533 unsigned long error_code = 0;
536 #ifndef CONFIG_CPU_SH2A
541 /* Intentional ifdef */
542 #ifdef CONFIG_CPU_HAS_SR_RB
543 lookup_exception_vector(error_code);
548 if (user_mode(regs)) {
549 int si_code = BUS_ADRERR;
553 /* bad PC is not something we can fix */
555 si_code = BUS_ADRALN;
559 #ifndef CONFIG_CPU_SH2A
561 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
562 /* Argh. Fault on the instruction itself.
563 This should never happen non-SMP
569 tmp = handle_unaligned_access(instruction, regs);
577 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
578 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
581 info.si_signo = SIGBUS;
583 info.si_code = si_code;
584 info.si_addr = (void *) address;
585 force_sig_info(SIGBUS, &info, current);
588 die("unaligned program counter", regs, error_code);
590 #ifndef CONFIG_CPU_SH2A
592 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
593 /* Argh. Fault on the instruction itself.
594 This should never happen non-SMP
597 die("insn faulting in do_address_error", regs, 0);
600 handle_unaligned_access(instruction, regs);
603 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned "
604 "access\n", current->comm);
606 force_sig(SIGSEGV, current);
613 * SH-DSP support gerg@snapgear.com.
615 int is_dsp_inst(struct pt_regs *regs)
620 * Safe guard if DSP mode is already enabled or we're lacking
621 * the DSP altogether.
623 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
626 get_user(inst, ((unsigned short *) regs->pc));
630 /* Check for any type of DSP or support instruction */
631 if ((inst == 0xf000) || (inst == 0x4000))
637 #define is_dsp_inst(regs) (0)
638 #endif /* CONFIG_SH_DSP */
640 #ifdef CONFIG_CPU_SH2A
641 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
642 unsigned long r6, unsigned long r7,
643 struct pt_regs __regs)
645 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
649 case TRAP_DIVZERO_ERROR:
650 info.si_code = FPE_INTDIV;
652 case TRAP_DIVOVF_ERROR:
653 info.si_code = FPE_INTOVF;
657 force_sig_info(SIGFPE, &info, current);
661 /* arch/sh/kernel/cpu/sh4/fpu.c */
662 extern int do_fpu_inst(unsigned short, struct pt_regs *);
663 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
664 unsigned long r6, unsigned long r7, struct pt_regs __regs);
666 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
667 unsigned long r6, unsigned long r7,
668 struct pt_regs __regs)
670 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
671 unsigned long error_code;
672 struct task_struct *tsk = current;
674 #ifdef CONFIG_SH_FPU_EMU
675 unsigned short inst = 0;
678 get_user(inst, (unsigned short*)regs->pc);
680 err = do_fpu_inst(inst, regs);
682 regs->pc += instruction_size(inst);
685 /* not a FPU inst. */
689 /* Check if it's a DSP instruction */
690 if (is_dsp_inst(regs)) {
691 /* Enable DSP mode, and restart instruction. */
697 lookup_exception_vector(error_code);
700 CHK_REMOTE_DEBUG(regs);
701 force_sig(SIGILL, tsk);
702 die_if_no_fixup("reserved instruction", regs, error_code);
705 #ifdef CONFIG_SH_FPU_EMU
706 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
709 * bfs: 8fxx: PC+=d*2+4;
710 * bts: 8dxx: PC+=d*2+4;
711 * bra: axxx: PC+=D*2+4;
712 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
713 * braf:0x23: PC+=Rn*2+4;
714 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
716 * jsr: 4x0b: PC=Rn after PR=PC+4;
719 if ((inst & 0xfd00) == 0x8d00) {
720 regs->pc += SH_PC_8BIT_OFFSET(inst);
724 if ((inst & 0xe000) == 0xa000) {
725 regs->pc += SH_PC_12BIT_OFFSET(inst);
729 if ((inst & 0xf0df) == 0x0003) {
730 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
734 if ((inst & 0xf0df) == 0x400b) {
735 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
739 if ((inst & 0xffff) == 0x000b) {
748 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
749 unsigned long r6, unsigned long r7,
750 struct pt_regs __regs)
752 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
753 unsigned long error_code;
754 struct task_struct *tsk = current;
755 #ifdef CONFIG_SH_FPU_EMU
756 unsigned short inst = 0;
758 get_user(inst, (unsigned short *)regs->pc + 1);
759 if (!do_fpu_inst(inst, regs)) {
760 get_user(inst, (unsigned short *)regs->pc);
761 if (!emulate_branch(inst, regs))
763 /* fault in branch.*/
765 /* not a FPU inst. */
768 lookup_exception_vector(error_code);
771 CHK_REMOTE_DEBUG(regs);
772 force_sig(SIGILL, tsk);
773 die_if_no_fixup("illegal slot instruction", regs, error_code);
776 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
777 unsigned long r6, unsigned long r7,
778 struct pt_regs __regs)
780 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
783 lookup_exception_vector(ex);
784 die_if_kernel("exception", regs, ex);
787 #if defined(CONFIG_SH_STANDARD_BIOS)
788 void *gdb_vbr_vector;
790 static inline void __init gdb_vbr_init(void)
792 register unsigned long vbr;
795 * Read the old value of the VBR register to initialise
796 * the vector through which debug and BIOS traps are
797 * delegated by the Linux trap handler.
799 asm volatile("stc vbr, %0" : "=r" (vbr));
801 gdb_vbr_vector = (void *)(vbr + 0x100);
802 printk("Setting GDB trap vector to 0x%08lx\n",
803 (unsigned long)gdb_vbr_vector);
807 void __init per_cpu_trap_init(void)
809 extern void *vbr_base;
811 #ifdef CONFIG_SH_STANDARD_BIOS
815 /* NOTE: The VBR value should be at P1
816 (or P2, virtural "fixed" address space).
817 It's definitely should not in physical address. */
819 asm volatile("ldc %0, vbr"
825 void *set_exception_table_vec(unsigned int vec, void *handler)
827 extern void *exception_handling_table[];
830 old_handler = exception_handling_table[vec];
831 exception_handling_table[vec] = handler;
835 extern asmlinkage void address_error_handler(unsigned long r4, unsigned long r5,
836 unsigned long r6, unsigned long r7,
837 struct pt_regs __regs);
839 void __init trap_init(void)
841 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
842 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
844 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
845 defined(CONFIG_SH_FPU_EMU)
847 * For SH-4 lacking an FPU, treat floating point instructions as
848 * reserved. They'll be handled in the math-emu case, or faulted on
851 set_exception_table_evt(0x800, do_reserved_inst);
852 set_exception_table_evt(0x820, do_illegal_slot_inst);
853 #elif defined(CONFIG_SH_FPU)
854 set_exception_table_evt(0x800, do_fpu_state_restore);
855 set_exception_table_evt(0x820, do_fpu_state_restore);
858 #ifdef CONFIG_CPU_SH2
859 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_handler);
861 #ifdef CONFIG_CPU_SH2A
862 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
863 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
866 /* Setup VBR for boot cpu */
871 void handle_BUG(struct pt_regs *regs)
873 enum bug_trap_type tt;
874 tt = report_bug(regs->pc);
875 if (tt == BUG_TRAP_TYPE_WARN) {
880 die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff);
883 int is_valid_bugaddr(unsigned long addr)
885 return addr >= PAGE_OFFSET;
889 void show_trace(struct task_struct *tsk, unsigned long *sp,
890 struct pt_regs *regs)
894 if (regs && user_mode(regs))
897 printk("\nCall trace: ");
898 #ifdef CONFIG_KALLSYMS
902 while (!kstack_end(sp)) {
904 if (kernel_text_address(addr))
913 debug_show_held_locks(tsk);
916 void show_stack(struct task_struct *tsk, unsigned long *sp)
923 sp = (unsigned long *)current_stack_pointer;
925 sp = (unsigned long *)tsk->thread.sp;
927 stack = (unsigned long)sp;
928 dump_mem("Stack: ", stack, THREAD_SIZE +
929 (unsigned long)task_stack_page(tsk));
930 show_trace(tsk, sp, NULL);
933 void dump_stack(void)
935 show_stack(NULL, NULL);
937 EXPORT_SYMBOL(dump_stack);