1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
24 #include <asm/sfafsr.h>
28 #define NR_SYSCALLS 284 /* Each OS is different... */
33 /* This is trivial with the new code... */
36 sethi %hi(TSTATE_PEF), %g4 ! IEU0
42 andcc %g5, FPRS_FEF, %g0
46 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
49 109: or %g7, %lo(109b), %g7
51 ba,a,pt %xcc, rtrap_clr_l6
53 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
54 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
55 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
56 be,a,pt %icc, 1f ! CTI
58 ldx [%g6 + TI_GSR], %g7 ! Load Group
59 1: andcc %g5, FPRS_DL, %g0 ! IEU1
62 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
93 b,pt %xcc, fpdis_exit2
95 1: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
99 ldxa [%g3] ASI_DMMU, %g5
102 stxa %g2, [%g3] ASI_DMMU
104 add %g6, TI_FPREGS + 0xc0, %g2
107 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
108 ldda [%g2] ASI_BLK_S, %f48
120 b,pt %xcc, fpdis_exit
122 2: andcc %g5, FPRS_DU, %g0
125 mov SECONDARY_CONTEXT, %g3
127 ldxa [%g3] ASI_DMMU, %g5
128 add %g6, TI_FPREGS, %g1
131 stxa %g2, [%g3] ASI_DMMU
133 add %g6, TI_FPREGS + 0x40, %g2
134 faddd %f32, %f34, %f36
135 fmuld %f32, %f34, %f38
136 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
137 ldda [%g2] ASI_BLK_S, %f16
138 faddd %f32, %f34, %f40
139 fmuld %f32, %f34, %f42
140 faddd %f32, %f34, %f44
141 fmuld %f32, %f34, %f46
142 faddd %f32, %f34, %f48
143 fmuld %f32, %f34, %f50
144 faddd %f32, %f34, %f52
145 fmuld %f32, %f34, %f54
146 faddd %f32, %f34, %f56
147 fmuld %f32, %f34, %f58
148 faddd %f32, %f34, %f60
149 fmuld %f32, %f34, %f62
151 ba,pt %xcc, fpdis_exit
153 3: mov SECONDARY_CONTEXT, %g3
154 add %g6, TI_FPREGS, %g1
155 ldxa [%g3] ASI_DMMU, %g5
158 stxa %g2, [%g3] ASI_DMMU
161 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
162 ldda [%g1 + %g2] ASI_BLK_S, %f16
164 ldda [%g1] ASI_BLK_S, %f32
165 ldda [%g1 + %g2] ASI_BLK_S, %f48
168 stxa %g5, [%g3] ASI_DMMU
172 ldx [%g6 + TI_XFSR], %fsr
174 or %g3, %g4, %g3 ! anal...
176 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
182 add %sp, PTREGS_OFF, %o0
186 .globl do_fpother_check_fitos
188 do_fpother_check_fitos:
189 sethi %hi(fp_other_bounce - 4), %g7
190 or %g7, %lo(fp_other_bounce - 4), %g7
192 /* NOTE: Need to preserve %g7 until we fully commit
193 * to the fitos fixup.
195 stx %fsr, [%g6 + TI_XFSR]
197 andcc %g3, TSTATE_PRIV, %g0
198 bne,pn %xcc, do_fptrap_after_fsr
200 ldx [%g6 + TI_XFSR], %g3
203 cmp %g1, 2 ! Unfinished FP-OP
204 bne,pn %xcc, do_fptrap_after_fsr
205 sethi %hi(1 << 23), %g1 ! Inexact
207 bne,pn %xcc, do_fptrap_after_fsr
209 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
210 #define FITOS_MASK 0xc1f83fe0
211 #define FITOS_COMPARE 0x81a01880
212 sethi %hi(FITOS_MASK), %g1
213 or %g1, %lo(FITOS_MASK), %g1
215 sethi %hi(FITOS_COMPARE), %g2
216 or %g2, %lo(FITOS_COMPARE), %g2
218 bne,pn %xcc, do_fptrap_after_fsr
220 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
221 sethi %hi(fitos_table_1), %g1
223 or %g1, %lo(fitos_table_1), %g1
226 ba,pt %xcc, fitos_emul_continue
263 sethi %hi(fitos_table_2), %g1
265 or %g1, %lo(fitos_table_2), %g1
269 ba,pt %xcc, fitos_emul_fini
306 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
312 stx %fsr, [%g6 + TI_XFSR]
314 ldub [%g6 + TI_FPSAVED], %g3
317 stb %g3, [%g6 + TI_FPSAVED]
319 stx %g3, [%g6 + TI_GSR]
320 mov SECONDARY_CONTEXT, %g3
321 ldxa [%g3] ASI_DMMU, %g5
324 stxa %g2, [%g3] ASI_DMMU
326 add %g6, TI_FPREGS, %g2
327 andcc %g1, FPRS_DL, %g0
330 stda %f0, [%g2] ASI_BLK_S
331 stda %f16, [%g2 + %g3] ASI_BLK_S
332 andcc %g1, FPRS_DU, %g0
335 stda %f32, [%g2] ASI_BLK_S
336 stda %f48, [%g2 + %g3] ASI_BLK_S
337 5: mov SECONDARY_CONTEXT, %g1
339 stxa %g5, [%g1] ASI_DMMU
345 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
347 .globl cheetah_plus_patch_fpdis
348 cheetah_plus_patch_fpdis:
349 /* We configure the dTLB512_0 for 4MB pages and the
350 * dTLB512_1 for 8K pages when in context zero.
352 sethi %hi(cplus_fptrap_1), %o0
353 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
355 set cplus_fptrap_insn_1, %o2
358 set cplus_fptrap_insn_2, %o2
361 set cplus_fptrap_insn_3, %o2
364 set cplus_fptrap_insn_4, %o2
371 /* The registers for cross calls will be:
373 * DATA 0: [low 32-bits] Address of function to call, jmp to this
374 * [high 32-bits] MMU Context Argument 0, place in %g5
375 * DATA 1: Address Argument 1, place in %g1
376 * DATA 2: Address Argument 2, place in %g7
378 * With this method we can do most of the cross-call tlb/cache
379 * flushing very quickly.
381 * Current CPU's IRQ worklist table is locked into %g6, don't touch.
388 ldxa [%g3 + %g0] ASI_INTR_R, %g3
389 sethi %hi(KERNBASE), %g4
391 bgeu,pn %xcc, do_ivec_xcall
393 stxa %g0, [%g0] ASI_INTR_RECEIVE
396 sethi %hi(ivector_table), %g2
398 or %g2, %lo(ivector_table), %g2
400 ldub [%g3 + 0x04], %g4 /* pil */
405 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
406 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
407 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
408 wr %g2, 0x0, %set_softint
412 ldxa [%g1 + %g0] ASI_INTR_R, %g1
416 ldxa [%g7 + %g0] ASI_INTR_R, %g7
417 stxa %g0, [%g0] ASI_INTR_RECEIVE
426 .globl save_alternate_globals
427 save_alternate_globals: /* %o0 = save_area */
429 andn %o5, PSTATE_IE, %o1
430 wrpr %o1, PSTATE_AG, %pstate
431 stx %g0, [%o0 + 0x00]
432 stx %g1, [%o0 + 0x08]
433 stx %g2, [%o0 + 0x10]
434 stx %g3, [%o0 + 0x18]
435 stx %g4, [%o0 + 0x20]
436 stx %g5, [%o0 + 0x28]
437 stx %g6, [%o0 + 0x30]
438 stx %g7, [%o0 + 0x38]
439 wrpr %o1, PSTATE_IG, %pstate
440 stx %g0, [%o0 + 0x40]
441 stx %g1, [%o0 + 0x48]
442 stx %g2, [%o0 + 0x50]
443 stx %g3, [%o0 + 0x58]
444 stx %g4, [%o0 + 0x60]
445 stx %g5, [%o0 + 0x68]
446 stx %g6, [%o0 + 0x70]
447 stx %g7, [%o0 + 0x78]
448 wrpr %o1, PSTATE_MG, %pstate
449 stx %g0, [%o0 + 0x80]
450 stx %g1, [%o0 + 0x88]
451 stx %g2, [%o0 + 0x90]
452 stx %g3, [%o0 + 0x98]
453 stx %g4, [%o0 + 0xa0]
454 stx %g5, [%o0 + 0xa8]
455 stx %g6, [%o0 + 0xb0]
456 stx %g7, [%o0 + 0xb8]
457 wrpr %o5, 0x0, %pstate
461 .globl restore_alternate_globals
462 restore_alternate_globals: /* %o0 = save_area */
464 andn %o5, PSTATE_IE, %o1
465 wrpr %o1, PSTATE_AG, %pstate
466 ldx [%o0 + 0x00], %g0
467 ldx [%o0 + 0x08], %g1
468 ldx [%o0 + 0x10], %g2
469 ldx [%o0 + 0x18], %g3
470 ldx [%o0 + 0x20], %g4
471 ldx [%o0 + 0x28], %g5
472 ldx [%o0 + 0x30], %g6
473 ldx [%o0 + 0x38], %g7
474 wrpr %o1, PSTATE_IG, %pstate
475 ldx [%o0 + 0x40], %g0
476 ldx [%o0 + 0x48], %g1
477 ldx [%o0 + 0x50], %g2
478 ldx [%o0 + 0x58], %g3
479 ldx [%o0 + 0x60], %g4
480 ldx [%o0 + 0x68], %g5
481 ldx [%o0 + 0x70], %g6
482 ldx [%o0 + 0x78], %g7
483 wrpr %o1, PSTATE_MG, %pstate
484 ldx [%o0 + 0x80], %g0
485 ldx [%o0 + 0x88], %g1
486 ldx [%o0 + 0x90], %g2
487 ldx [%o0 + 0x98], %g3
488 ldx [%o0 + 0xa0], %g4
489 ldx [%o0 + 0xa8], %g5
490 ldx [%o0 + 0xb0], %g6
491 ldx [%o0 + 0xb8], %g7
492 wrpr %o5, 0x0, %pstate
498 ldx [%o0 + PT_V9_TSTATE], %o1
502 stx %o1, [%o0 + PT_V9_G1]
504 ldx [%o0 + PT_V9_TSTATE], %o1
505 ldx [%o0 + PT_V9_G1], %o2
506 or %g0, %ulo(TSTATE_ICC), %o3
513 stx %o1, [%o0 + PT_V9_TSTATE]
515 .globl utrap, utrap_ill
516 utrap: brz,pn %g1, etrap
521 andn %l6, TSTATE_CWP, %l6
522 wrpr %l6, %l7, %tstate
529 add %sp, PTREGS_OFF, %o0
533 /* XXX Here is stuff we still need to write... -DaveM XXX */
534 .globl netbsd_syscall
539 /* We need to carefully read the error status, ACK
540 * the errors, prevent recursive traps, and pass the
541 * information on to C code for logging.
543 * We pass the AFAR in as-is, and we encode the status
544 * information as described in asm-sparc64/sfafsr.h
546 .globl __spitfire_access_error
547 __spitfire_access_error:
548 /* Disable ESTATE error reporting so that we do not
549 * take recursive traps and RED state the processor.
551 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
555 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
557 /* __spitfire_cee_trap branches here with AFSR in %g4 and
558 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
559 * ESTATE Error Enable register.
561 __spitfire_cee_trap_continue:
562 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
565 and %g3, 0x1ff, %g3 ! Paranoia
566 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
572 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
576 /* Read in the UDB error register state, clearing the
577 * sticky error bits as-needed. We only clear them if
578 * the UE bit is set. Likewise, __spitfire_cee_trap
579 * below will only do so if the CE bit is set.
581 * NOTE: UltraSparc-I/II have high and low UDB error
582 * registers, corresponding to the two UDB units
583 * present on those chips. UltraSparc-IIi only
584 * has a single UDB, called "SDB" in the manual.
585 * For IIi the upper UDB register always reads
586 * as zero so for our purposes things will just
587 * work with the checks below.
589 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
590 and %g3, 0x3ff, %g7 ! Paranoia
591 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
593 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
596 stxa %g3, [%g0] ASI_UDB_ERROR_W
600 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
601 and %g3, 0x3ff, %g7 ! Paranoia
602 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
604 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
608 stxa %g3, [%g7] ASI_UDB_ERROR_W
611 1: /* Ok, now that we've latched the error state,
612 * clear the sticky bits in the AFSR.
614 stxa %g4, [%g0] ASI_AFSR
629 1: ba,pt %xcc, etrap_irq
634 call spitfire_access_error
635 add %sp, PTREGS_OFF, %o0
639 /* This is the trap handler entry point for ECC correctable
640 * errors. They are corrected, but we listen for the trap
641 * so that the event can be logged.
643 * Disrupting errors are either:
644 * 1) single-bit ECC errors during UDB reads to system
646 * 2) data parity errors during write-back events
648 * As far as I can make out from the manual, the CEE trap
649 * is only for correctable errors during memory read
650 * accesses by the front-end of the processor.
652 * The code below is only for trap level 1 CEE events,
653 * as it is the only situation where we can safely record
654 * and log. For trap level >1 we just clear the CE bit
655 * in the AFSR and return.
657 * This is just like __spiftire_access_error above, but it
658 * specifically handles correctable errors. If an
659 * uncorrectable error is indicated in the AFSR we
660 * will branch directly above to __spitfire_access_error
661 * to handle it instead. Uncorrectable therefore takes
662 * priority over correctable, and the error logging
663 * C code will notice this case by inspecting the
666 .globl __spitfire_cee_trap
668 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
670 sllx %g3, SFAFSR_UE_SHIFT, %g3
671 andcc %g4, %g3, %g0 ! Check for UE
672 bne,pn %xcc, __spitfire_access_error
675 /* Ok, in this case we only have a correctable error.
676 * Indicate we only wish to capture that state in register
677 * %g1, and we only disable CE error reporting unlike UE
678 * handling which disables all errors.
680 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
681 andn %g3, ESTATE_ERR_CE, %g3
682 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
685 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
686 ba,pt %xcc, __spitfire_cee_trap_continue
689 .globl __spitfire_data_access_exception
690 .globl __spitfire_data_access_exception_tl1
691 __spitfire_data_access_exception_tl1:
693 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
696 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
697 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
698 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
701 cmp %g3, 0x80 ! first win spill/fill trap
703 cmp %g3, 0xff ! last win spill/fill trap
706 ba,pt %xcc, winfix_dax
708 1: sethi %hi(109f), %g7
710 109: or %g7, %lo(109b), %g7
713 call spitfire_data_access_exception_tl1
714 add %sp, PTREGS_OFF, %o0
718 __spitfire_data_access_exception:
720 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
723 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
724 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
725 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
729 109: or %g7, %lo(109b), %g7
732 call spitfire_data_access_exception
733 add %sp, PTREGS_OFF, %o0
737 .globl __spitfire_insn_access_exception
738 .globl __spitfire_insn_access_exception_tl1
739 __spitfire_insn_access_exception_tl1:
741 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
743 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
744 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
745 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
749 109: or %g7, %lo(109b), %g7
752 call spitfire_insn_access_exception_tl1
753 add %sp, PTREGS_OFF, %o0
757 __spitfire_insn_access_exception:
759 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
761 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
762 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
763 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
767 109: or %g7, %lo(109b), %g7
770 call spitfire_insn_access_exception
771 add %sp, PTREGS_OFF, %o0
775 /* These get patched into the trap table at boot time
776 * once we know we have a cheetah processor.
778 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
779 cheetah_fecc_trap_vector:
781 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
782 andn %g1, DCU_DC | DCU_IC, %g1
783 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 sethi %hi(cheetah_fast_ecc), %g2
786 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
788 cheetah_fecc_trap_vector_tl1:
790 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
791 andn %g1, DCU_DC | DCU_IC, %g1
792 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
794 sethi %hi(cheetah_fast_ecc), %g2
795 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
797 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
798 cheetah_cee_trap_vector:
800 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
801 andn %g1, DCU_IC, %g1
802 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
804 sethi %hi(cheetah_cee), %g2
805 jmpl %g2 + %lo(cheetah_cee), %g0
807 cheetah_cee_trap_vector_tl1:
809 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
810 andn %g1, DCU_IC, %g1
811 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
813 sethi %hi(cheetah_cee), %g2
814 jmpl %g2 + %lo(cheetah_cee), %g0
816 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
817 cheetah_deferred_trap_vector:
819 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
820 andn %g1, DCU_DC | DCU_IC, %g1;
821 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
823 sethi %hi(cheetah_deferred_trap), %g2
824 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
826 cheetah_deferred_trap_vector_tl1:
828 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
829 andn %g1, DCU_DC | DCU_IC, %g1;
830 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
832 sethi %hi(cheetah_deferred_trap), %g2
833 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
836 /* Cheetah+ specific traps. These are for the new I/D cache parity
837 * error traps. The first argument to cheetah_plus_parity_handler
838 * is encoded as follows:
840 * Bit0: 0=dcache,1=icache
841 * Bit1: 0=recoverable,1=unrecoverable
843 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
844 cheetah_plus_dcpe_trap_vector:
846 sethi %hi(do_cheetah_plus_data_parity), %g7
847 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
854 do_cheetah_plus_data_parity:
857 ba,pt %xcc, etrap_irq
860 call cheetah_plus_parity_error
861 add %sp, PTREGS_OFF, %o1
862 ba,a,pt %xcc, rtrap_irq
864 cheetah_plus_dcpe_trap_vector_tl1:
866 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
867 sethi %hi(do_dcpe_tl1), %g3
868 jmpl %g3 + %lo(do_dcpe_tl1), %g0
874 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
875 cheetah_plus_icpe_trap_vector:
877 sethi %hi(do_cheetah_plus_insn_parity), %g7
878 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
885 do_cheetah_plus_insn_parity:
888 ba,pt %xcc, etrap_irq
891 call cheetah_plus_parity_error
892 add %sp, PTREGS_OFF, %o1
893 ba,a,pt %xcc, rtrap_irq
895 cheetah_plus_icpe_trap_vector_tl1:
897 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
898 sethi %hi(do_icpe_tl1), %g3
899 jmpl %g3 + %lo(do_icpe_tl1), %g0
905 /* If we take one of these traps when tl >= 1, then we
906 * jump to interrupt globals. If some trap level above us
907 * was also using interrupt globals, we cannot recover.
908 * We may use all interrupt global registers except %g6.
910 .globl do_dcpe_tl1, do_icpe_tl1
912 rdpr %tl, %g1 ! Save original trap level
913 mov 1, %g2 ! Setup TSTATE checking loop
914 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
915 1: wrpr %g2, %tl ! Set trap level to check
916 rdpr %tstate, %g4 ! Read TSTATE for this level
917 andcc %g4, %g3, %g0 ! Interrupt globals in use?
918 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
919 wrpr %g1, %tl ! Restore original trap level
920 add %g2, 1, %g2 ! Next trap level
921 cmp %g2, %g1 ! Hit them all yet?
922 ble,pt %icc, 1b ! Not yet
924 wrpr %g1, %tl ! Restore original trap level
925 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
926 sethi %hi(dcache_parity_tl1_occurred), %g2
927 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
929 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
930 /* Reset D-cache parity */
931 sethi %hi(1 << 16), %g1 ! D-cache size
932 mov (1 << 5), %g2 ! D-cache line size
933 sub %g1, %g2, %g1 ! Move down 1 cacheline
934 1: srl %g1, 14, %g3 ! Compute UTAG
936 stxa %g3, [%g1] ASI_DCACHE_UTAG
938 sub %g2, 8, %g3 ! 64-bit data word within line
940 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
942 subcc %g3, 8, %g3 ! Next 64-bit data word
945 subcc %g1, %g2, %g1 ! Next cacheline
948 ba,pt %xcc, dcpe_icpe_tl1_common
954 1: or %g7, %lo(1b), %g7
956 call cheetah_plus_parity_error
957 add %sp, PTREGS_OFF, %o1
962 rdpr %tl, %g1 ! Save original trap level
963 mov 1, %g2 ! Setup TSTATE checking loop
964 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
965 1: wrpr %g2, %tl ! Set trap level to check
966 rdpr %tstate, %g4 ! Read TSTATE for this level
967 andcc %g4, %g3, %g0 ! Interrupt globals in use?
968 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
969 wrpr %g1, %tl ! Restore original trap level
970 add %g2, 1, %g2 ! Next trap level
971 cmp %g2, %g1 ! Hit them all yet?
972 ble,pt %icc, 1b ! Not yet
974 wrpr %g1, %tl ! Restore original trap level
975 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
976 sethi %hi(icache_parity_tl1_occurred), %g2
977 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
979 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
981 sethi %hi(1 << 15), %g1 ! I-cache size
982 mov (1 << 5), %g2 ! I-cache line size
984 1: or %g1, (2 << 3), %g3
985 stxa %g0, [%g3] ASI_IC_TAG
990 ba,pt %xcc, dcpe_icpe_tl1_common
996 1: or %g7, %lo(1b), %g7
998 call cheetah_plus_parity_error
999 add %sp, PTREGS_OFF, %o1
1003 dcpe_icpe_tl1_common:
1004 /* Flush D-cache, re-enable D/I caches in DCU and finally
1005 * retry the trapping instruction.
1007 sethi %hi(1 << 16), %g1 ! D-cache size
1008 mov (1 << 5), %g2 ! D-cache line size
1010 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1015 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1016 or %g1, (DCU_DC | DCU_IC), %g1
1017 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1021 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1023 * %g1: (TL>=0) ? 1 : 0
1028 * %g6: current thread ptr
1031 __cheetah_log_error:
1032 /* Put "TL1" software bit into AFSR. */
1037 /* Get log entry pointer for this cpu at this trap level. */
1038 BRANCH_IF_JALAPENO(g2,g3,50f)
1039 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1044 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1048 60: sllx %g2, 9, %g2
1049 sethi %hi(cheetah_error_log), %g3
1050 ldx [%g3 + %lo(cheetah_error_log)], %g3
1058 /* %g1 holds pointer to the top of the logging scoreboard */
1059 ldx [%g1 + 0x0], %g7
1064 stx %g4, [%g1 + 0x0]
1065 stx %g5, [%g1 + 0x8]
1068 /* %g1 now points to D-cache logging area */
1069 set 0x3ff8, %g2 /* DC_addr mask */
1070 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1072 or %g3, 1, %g3 /* PHYS tag + valid */
1074 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
1075 cmp %g3, %g7 /* TAG match? */
1079 /* Yep, what we want, capture state. */
1080 stx %g2, [%g1 + 0x20]
1081 stx %g7, [%g1 + 0x28]
1083 /* A membar Sync is required before and after utag access. */
1085 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1087 stx %g7, [%g1 + 0x30]
1088 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1089 stx %g7, [%g1 + 0x38]
1092 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1094 add %g3, (1 << 5), %g3
1102 13: sethi %hi(1 << 14), %g7
1111 /* %g1 now points to I-cache logging area */
1112 20: set 0x1fe0, %g2 /* IC_addr mask */
1113 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1114 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1115 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1116 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1118 21: ldxa [%g2] ASI_IC_TAG, %g7
1124 /* Yep, what we want, capture state. */
1125 stx %g2, [%g1 + 0x40]
1126 stx %g7, [%g1 + 0x48]
1127 add %g2, (1 << 3), %g2
1128 ldxa [%g2] ASI_IC_TAG, %g7
1129 add %g2, (1 << 3), %g2
1130 stx %g7, [%g1 + 0x50]
1131 ldxa [%g2] ASI_IC_TAG, %g7
1132 add %g2, (1 << 3), %g2
1133 stx %g7, [%g1 + 0x60]
1134 ldxa [%g2] ASI_IC_TAG, %g7
1135 stx %g7, [%g1 + 0x68]
1136 sub %g2, (3 << 3), %g2
1137 ldxa [%g2] ASI_IC_STAG, %g7
1138 stx %g7, [%g1 + 0x58]
1142 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1144 add %g3, (1 << 3), %g3
1152 23: sethi %hi(1 << 14), %g7
1161 /* %g1 now points to E-cache logging area */
1162 30: andn %g5, (32 - 1), %g2
1163 stx %g2, [%g1 + 0x20]
1164 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1165 stx %g7, [%g1 + 0x28]
1166 ldxa [%g2] ASI_EC_R, %g0
1169 31: ldxa [%g3] ASI_EC_DATA, %g7
1170 stx %g7, [%g1 + %g3]
1183 ba,pt %xcc, c_deferred
1185 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1186 * in the trap table. That code has done a memory barrier
1187 * and has disabled both the I-cache and D-cache in the DCU
1188 * control register. The I-cache is disabled so that we may
1189 * capture the corrupted cache line, and the D-cache is disabled
1190 * because corrupt data may have been placed there and we don't
1191 * want to reference it.
1193 * %g1 is one if this trap occurred at %tl >= 1.
1195 * Next, we turn off error reporting so that we don't recurse.
1197 .globl cheetah_fast_ecc
1199 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1200 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1201 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1204 /* Fetch and clear AFSR/AFAR */
1205 ldxa [%g0] ASI_AFSR, %g4
1206 ldxa [%g0] ASI_AFAR, %g5
1207 stxa %g4, [%g0] ASI_AFSR
1210 ba,pt %xcc, __cheetah_log_error
1216 ba,pt %xcc, etrap_irq
1220 call cheetah_fecc_handler
1221 add %sp, PTREGS_OFF, %o0
1222 ba,a,pt %xcc, rtrap_irq
1224 /* Our caller has disabled I-cache and performed membar Sync. */
1227 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1228 andn %g2, ESTATE_ERROR_CEEN, %g2
1229 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1232 /* Fetch and clear AFSR/AFAR */
1233 ldxa [%g0] ASI_AFSR, %g4
1234 ldxa [%g0] ASI_AFAR, %g5
1235 stxa %g4, [%g0] ASI_AFSR
1238 ba,pt %xcc, __cheetah_log_error
1244 ba,pt %xcc, etrap_irq
1248 call cheetah_cee_handler
1249 add %sp, PTREGS_OFF, %o0
1250 ba,a,pt %xcc, rtrap_irq
1252 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1253 .globl cheetah_deferred_trap
1254 cheetah_deferred_trap:
1255 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1256 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1257 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1260 /* Fetch and clear AFSR/AFAR */
1261 ldxa [%g0] ASI_AFSR, %g4
1262 ldxa [%g0] ASI_AFAR, %g5
1263 stxa %g4, [%g0] ASI_AFSR
1266 ba,pt %xcc, __cheetah_log_error
1272 ba,pt %xcc, etrap_irq
1276 call cheetah_deferred_handler
1277 add %sp, PTREGS_OFF, %o0
1278 ba,a,pt %xcc, rtrap_irq
1283 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1285 sethi %hi(109f), %g7
1287 109: or %g7, %lo(109b), %g7
1289 add %sp, PTREGS_OFF, %o0
1298 /* Setup %g4/%g5 now as they are used in the
1303 ldxa [%g4] ASI_DMMU, %g4
1304 ldxa [%g3] ASI_DMMU, %g5
1305 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1307 bgu,pn %icc, winfix_mna
1310 1: sethi %hi(109f), %g7
1312 109: or %g7, %lo(109b), %g7
1315 call mem_address_unaligned
1316 add %sp, PTREGS_OFF, %o0
1322 sethi %hi(109f), %g7
1324 ldxa [%g4] ASI_DMMU, %g5
1325 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1328 ldxa [%g4] ASI_DMMU, %g4
1330 109: or %g7, %lo(109b), %g7
1334 add %sp, PTREGS_OFF, %o0
1340 sethi %hi(109f), %g7
1342 ldxa [%g4] ASI_DMMU, %g5
1343 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1346 ldxa [%g4] ASI_DMMU, %g4
1348 109: or %g7, %lo(109b), %g7
1352 add %sp, PTREGS_OFF, %o0
1356 .globl breakpoint_trap
1358 call sparc_breakpoint
1359 add %sp, PTREGS_OFF, %o0
1363 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1364 defined(CONFIG_SOLARIS_EMUL_MODULE)
1365 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1366 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1367 * This is complete brain damage.
1373 cmp %o0, NR_SYSCALLS
1376 sethi %hi(sunos_nosys), %l6
1378 or %l6, %lo(sunos_nosys), %l6
1379 1: sethi %hi(sunos_sys_table), %l7
1380 or %l7, %lo(sunos_sys_table), %l7
1381 lduw [%l7 + %o0], %l6
1395 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1396 b,pt %xcc, ret_sys_call
1397 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1399 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1402 call sys32_geteuid16
1405 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1406 b,pt %xcc, ret_sys_call
1407 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1409 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1412 call sys32_getegid16
1415 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1416 b,pt %xcc, ret_sys_call
1417 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1420 /* SunOS's execv() call only specifies the argv argument, the
1421 * environment settings are the same as the calling processes.
1425 sethi %hi(sparc_execve), %g1
1426 ba,pt %xcc, execve_merge
1427 or %g1, %lo(sparc_execve), %g1
1428 #ifdef CONFIG_COMPAT
1431 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1434 sethi %hi(sparc32_execve), %g1
1435 or %g1, %lo(sparc32_execve), %g1
1440 add %sp, PTREGS_OFF, %o0
1442 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1443 .globl sys_sigsuspend, sys_rt_sigsuspend
1444 .globl sys_rt_sigreturn
1446 .globl sys_sigaltstack
1448 sys_pipe: ba,pt %xcc, sparc_pipe
1449 add %sp, PTREGS_OFF, %o0
1450 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1451 add %sp, PTREGS_OFF, %o0
1452 sys_memory_ordering:
1453 ba,pt %xcc, sparc_memory_ordering
1454 add %sp, PTREGS_OFF, %o1
1455 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1456 add %i6, STACK_BIAS, %o2
1457 #ifdef CONFIG_COMPAT
1458 .globl sys32_sigstack
1459 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1461 .globl sys32_sigaltstack
1463 ba,pt %xcc, do_sys32_sigaltstack
1467 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1469 add %o7, 1f-.-4, %o7
1471 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1472 add %sp, PTREGS_OFF, %o2
1473 call do_rt_sigsuspend
1474 add %o7, 1f-.-4, %o7
1476 #ifdef CONFIG_COMPAT
1477 .globl sys32_rt_sigsuspend
1478 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1480 add %sp, PTREGS_OFF, %o2
1481 call do_rt_sigsuspend32
1482 add %o7, 1f-.-4, %o7
1484 /* NOTE: %o0 has a correct value already */
1485 sys_sigpause: add %sp, PTREGS_OFF, %o1
1487 add %o7, 1f-.-4, %o7
1489 #ifdef CONFIG_COMPAT
1490 .globl sys32_sigreturn
1492 add %sp, PTREGS_OFF, %o0
1494 add %o7, 1f-.-4, %o7
1498 add %sp, PTREGS_OFF, %o0
1499 call do_rt_sigreturn
1500 add %o7, 1f-.-4, %o7
1502 #ifdef CONFIG_COMPAT
1503 .globl sys32_rt_sigreturn
1505 add %sp, PTREGS_OFF, %o0
1506 call do_rt_sigreturn32
1507 add %o7, 1f-.-4, %o7
1510 sys_ptrace: add %sp, PTREGS_OFF, %o0
1512 add %o7, 1f-.-4, %o7
1515 1: ldx [%curptr + TI_FLAGS], %l5
1516 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1519 add %sp, PTREGS_OFF, %o0
1526 /* This is how fork() was meant to be done, 8 instruction entry.
1528 * I questioned the following code briefly, let me clear things
1529 * up so you must not reason on it like I did.
1531 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1532 * need it here because the only piece of window state we copy to
1533 * the child is the CWP register. Even if the parent sleeps,
1534 * we are safe because we stuck it into pt_regs of the parent
1535 * so it will not change.
1537 * XXX This raises the question, whether we can do the same on
1538 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1539 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1540 * XXX fork_kwim in UREG_G1 (global registers are considered
1541 * XXX volatile across a system call in the sparc ABI I think
1542 * XXX if it isn't we can use regs->y instead, anyone who depends
1543 * XXX upon the Y register being preserved across a fork deserves
1546 * In fact we should take advantage of that fact for other things
1547 * during system calls...
1549 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1550 .globl ret_from_syscall
1552 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1553 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1554 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1555 ba,pt %xcc, sys_clone
1561 ba,pt %xcc, sparc_do_fork
1562 add %sp, PTREGS_OFF, %o2
1564 /* Clear current_thread_info()->new_child, and
1565 * check performance counter stuff too.
1567 stb %g0, [%g6 + TI_NEW_CHILD]
1568 ldx [%g6 + TI_FLAGS], %l0
1571 andcc %l0, _TIF_PERFCTR, %g0
1574 ldx [%g6 + TI_PCR], %o7
1577 /* Blackbird errata workaround. See commentary in
1578 * smp.c:smp_percpu_timer_interrupt() for more
1584 99: wr %g0, %g0, %pic
1587 1: b,pt %xcc, ret_sys_call
1588 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1589 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1593 wrpr %g3, 0x0, %cansave
1594 wrpr %g0, 0x0, %otherwin
1595 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1596 ba,pt %xcc, sys_exit
1597 stb %g0, [%g6 + TI_WSAVED]
1599 linux_sparc_ni_syscall:
1600 sethi %hi(sys_ni_syscall), %l7
1602 or %l7, %lo(sys_ni_syscall), %l7
1604 linux_syscall_trace32:
1605 add %sp, PTREGS_OFF, %o0
1615 linux_syscall_trace:
1616 add %sp, PTREGS_OFF, %o0
1627 /* Linux 32-bit and SunOS system calls enter here... */
1629 .globl linux_sparc_syscall32
1630 linux_sparc_syscall32:
1631 /* Direct access to user regs, much faster. */
1632 cmp %g1, NR_SYSCALLS ! IEU1 Group
1633 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1634 srl %i0, 0, %o0 ! IEU0
1635 sll %g1, 2, %l4 ! IEU0 Group
1636 srl %i4, 0, %o4 ! IEU1
1637 lduw [%l7 + %l4], %l7 ! Load
1638 srl %i1, 0, %o1 ! IEU0 Group
1639 ldx [%curptr + TI_FLAGS], %l0 ! Load
1641 srl %i5, 0, %o5 ! IEU1
1642 srl %i2, 0, %o2 ! IEU0 Group
1643 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1644 bne,pn %icc, linux_syscall_trace32 ! CTI
1646 call %l7 ! CTI Group brk forced
1647 srl %i3, 0, %o3 ! IEU0
1650 /* Linux native and SunOS system calls enter here... */
1652 .globl linux_sparc_syscall, ret_sys_call
1653 linux_sparc_syscall:
1654 /* Direct access to user regs, much faster. */
1655 cmp %g1, NR_SYSCALLS ! IEU1 Group
1656 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1658 sll %g1, 2, %l4 ! IEU0 Group
1660 lduw [%l7 + %l4], %l7 ! Load
1661 4: mov %i2, %o2 ! IEU0 Group
1662 ldx [%curptr + TI_FLAGS], %l0 ! Load
1665 mov %i4, %o4 ! IEU0 Group
1666 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1667 bne,pn %icc, linux_syscall_trace ! CTI Group
1669 2: call %l7 ! CTI Group brk forced
1673 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1675 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1676 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1678 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1681 /* Check if force_successful_syscall_return()
1684 ldub [%curptr + TI_SYS_NOERROR], %l0
1688 stb %g0, [%curptr + TI_SYS_NOERROR]
1691 cmp %o0, -ERESTART_RESTARTBLOCK
1693 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1695 /* System call success, clear Carry condition code. */
1697 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1698 bne,pn %icc, linux_syscall_trace2
1699 add %l1, 0x4, %l2 ! npc = npc+4
1700 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1701 ba,pt %xcc, rtrap_clr_l6
1702 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1705 /* System call failure, set Carry condition code.
1706 * Also, get abs(errno) to return to the process.
1708 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1711 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1713 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1714 bne,pn %icc, linux_syscall_trace2
1715 add %l1, 0x4, %l2 ! npc = npc+4
1716 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1719 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1720 linux_syscall_trace2:
1721 add %sp, PTREGS_OFF, %o0
1724 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1726 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1729 .globl __flushw_user
1734 1: save %sp, -128, %sp
1740 restore %g0, %g0, %g0