1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/config.h>
11 #include <asm/pstate.h>
12 #include <asm/ptrace.h>
14 #include <asm/spitfire.h>
16 #include <asm/processor.h>
19 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
20 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
21 #define ETRAP_PSTATE2 \
22 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
25 * On entry, %g7 is return address - 0x4.
26 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
31 .globl etrap, etrap_irq, etraptl1
34 TRAP_LOAD_THREAD_REG(%g6, %g1)
37 andcc %g1, TSTATE_PRIV, %g0
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
57 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
60 brnz,pt %g1, etrap_save
66 be,pt %xcc, etrap_user_spill
70 brz %g3, etrap_kernel_spill
76 ldx [%g6 + TI_FLAGS], %g3
77 and %g3, _TIF_32BIT, %g3
78 brnz,pt %g3, etrap_user_spill_32bit
80 ba,a,pt %xcc, etrap_user_spill_64bit
82 etrap_save: save %g2, -STACK_BIAS, %sp
86 mov PRIMARY_CONTEXT, %l4
89 wrpr %g0, 0, %canrestore
92 stb %l5, [%l6 + TI_FPDEPTH]
94 wrpr %g3, 0, %otherwin
96 sethi %hi(sparc64_kern_pri_context), %g2
97 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
98 stxa %g3, [%l4] ASI_DMMU
99 sethi %hi(KERNBASE), %l4
105 wrpr %g0, ETRAP_PSTATE1, %pstate
106 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
107 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
109 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
111 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
112 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
113 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
114 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
116 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
119 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
120 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
121 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
122 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
123 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
124 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
125 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
126 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
128 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
129 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
130 ldx [%g6 + TI_TASK], %g4
134 ldub [%l6 + TI_FPDEPTH], %l5
135 add %l6, TI_FPSAVED + 1, %l4
138 stb %l5, [%l6 + TI_FPDEPTH]
143 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
144 * We place this right after pt_regs on the trap stack.
154 TRAP_LOAD_THREAD_REG(%g6, %g1)
155 sub %sp, ((4 * 8) * 4) + 8, %g2
160 stx %g3, [%g2 + STACK_BIAS + 0x00]
162 stx %g3, [%g2 + STACK_BIAS + 0x08]
164 stx %g3, [%g2 + STACK_BIAS + 0x10]
166 stx %g3, [%g2 + STACK_BIAS + 0x18]
170 stx %g3, [%g2 + STACK_BIAS + 0x20]
172 stx %g3, [%g2 + STACK_BIAS + 0x28]
174 stx %g3, [%g2 + STACK_BIAS + 0x30]
176 stx %g3, [%g2 + STACK_BIAS + 0x38]
180 stx %g3, [%g2 + STACK_BIAS + 0x40]
182 stx %g3, [%g2 + STACK_BIAS + 0x48]
184 stx %g3, [%g2 + STACK_BIAS + 0x50]
186 stx %g3, [%g2 + STACK_BIAS + 0x58]
190 stx %g3, [%g2 + STACK_BIAS + 0x60]
192 stx %g3, [%g2 + STACK_BIAS + 0x68]
194 stx %g3, [%g2 + STACK_BIAS + 0x70]
196 stx %g3, [%g2 + STACK_BIAS + 0x78]
199 stx %g1, [%g2 + STACK_BIAS + 0x80]
202 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
204 andcc %g1, TSTATE_PRIV, %g0